Process for Producing Semiconductor Devices

This invention relates to a process for producing a semiconductor device, more particularly to a process for forming a multilevel interconnection.

A process for forming a multilevel interconnection in the conventional process for forming a semiconductor device will be described referring to FIG. 1.

A first Al wiring 3A is first formed on the semiconductor substrate 1A, and then a first insulator film (CVD-SiO.sub.2 film) 14, a spin-on glass (SOG) film 5A and a second insulator film 16 are formed successively to form as a whole a three-layered structure insulator film. Subsequently, after via holes are formed at predetermined positions, a second Al wiring 8A is formed. Thus, a semiconductor device having a double level Al interconnection structure is completed. Such process is disclosed, for example, in Japanese Unexamined Patent Publication No. 100748/1982.

However, the conventional process for forming multilevel interconnection described above involves the following problems.

First, in the formation of the oxide film by chemical vapor deposition, a high film-forming temperature of 300.degree. C. or more is needed, so that cracking is liable to occur in the film thus formed due to thermal stress. Meanwhile, voids are liable to be formed in the Al wirings by the stress and thus the interconnections are easily disconnected when charged. Further, since a heat treatment at 300.degree. C. or more is required when the SOG film is formed, the insulator films are liable to be cracked due to the tensile stress caused by the volume shrinkage of the SOG film and voids are liable to be formed in the Al wirings due to the thermal stress increasing during the heat treatment and the like. Accordingly, not only the yield of the semiconductor devices but also reliability thereof are degraded, disadvantageously.

With a view to overcoming the above problems, the present invention is directed to provide a process for producing semiconductor devices having high yield and high reliability.

To describe in detail, the process for producing a semiconductor device according to this invention includes a step of forming a lower level wiring on the surface of a semiconductor substrate with an insulator film interposed therebetween; a step of forming a first insulator film on the lower level wiring using an alkoxyfluorosilane vapor and a water vapor at a temperature of 50.degree. C. or less; a step of forming a spin-on glass film by applying a coating solution containing at least one of the compounds represented by the formula Si(OH).sub.4, Si(OR).sub.4 and R.sub.n Si(OR).sub.4-n (wherein R represents an alkyl group; and n is an integer of 1 to 3), followed by heat treatment at a temperature of 200.degree. C. or less; a step of exposing the spin-on glass film to a vapor primarily containing a fluorine compound such as alkoxyfluorosilanes in a reaction chamber; a step of forming a second insulator film on the spin-on glass film using an alkoxyfluorosilane vapor and a water vapor; a step of forming via holes at predetermined positions through these insulator films; and a step of forming an upper level wiring which is connected to the lower level wiring through the via holes.

It should be noted that when an alkoxyfluorosilane is hydrolyzed with a water vapor, it readily undergoes a condensation reaction at a temperature of 50.degree. C. or less to form a fluorine-containing silicon oxide film. Further, when a spin-on glass film baked at a low temperature of 100.degree. C. is exposed to the alkoxyfluorosilane vapor, the condensation reaction is accelerated even at room temperature. Accordingly, the heat treatment at a high temperature of 300.degree. C. or more which has been needed in the conventional process becomes unnecessary, and almost no volume shrinkage occurs for spin-on glass films.

Therefore, formation and planarization of the insulator films can be achieved at a temperature of 200.degree. C. or less, particularly even at room temperature, and thus cracking in the insulator films or formation of voids in the Al wirings attributed to the thermal stress applied and volume shrinkage when the insulator films are formed can be prevented from occurring.

The features of this invention that are believed to be novel are set forth with particularity in the appended claims. The invention, together with the objects and advantages thereof, may best be understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings in which:

FIG. 1 shows in cross section a part of semiconductor chip formed according to a prior art technique; and

FIGS. 2 (a) to (c) show in cross section a process for forming a semiconductor chip according to one embodiment of the invention.

In the preferred embodiment, triethoxyfluorosilane {FSi(OC.sub.2 H.sub.5).sub.3 } and an alcoholic solution of silanol {Si(OH).sub.4 } (concentration of solid content: 10 wt %) were used as the alkoxyfluorosilane and the SOG film forming coating liquid, respectively.

As shown in FIG. 2 (a), a first Al wiring 3 having a thickness of about 1 .mu.m was first formed on a semiconductor substrate 1 such as of Si with an insulator film 2 such as of BPSG and PSG interposed therebetween. Next, a triethoxyfluorosilane solution and a pure water were independently subjected to bubbling to generate vapors, which were introduced to a reaction chamber at a flow rate of 1 SLM, respectively. The resulting semiconductor substrate 1 was maintained at 25.degree. C. under 700 Torr in this reaction chamber for one hour to form a first fluorine-containing silicon oxide film 4 having a thickness of about 0.5 .mu.m.

Subsequently, as shown in FIG. 2 (b), an alcoholic solution of silanol was dropped on the thus treated substrate to carry out spin coating at a rate of 4000 rpm for 20 seconds, and the resulting substrate was subjected to heat treatment on a hot plate at 100.degree. C. in a nitrogen gas atmosphere for 60 seconds to form an SOG film 5 having a thickness of about 0.3 .mu.m. Only the triethoxyfluorosilane vapor was fed to the same reaction chamber as used for forming the first fluorine-containing silicon oxide film 4, and the SOG film 5 was exposed to the triethoxyfluorosilane vapor therein for 30 minutes, followed by formation of a second fluorine-containing silicon oxide film 6 having a thickness of about 0.5 .mu.m in the same reaction chamber under the same conditions as in the formation of the first fluorine-containing silicon oxide film by feeding the triethoxyfluorosilane vapor and a water vapor.

Via holes 7 were then formed at predetermined positions through the thus formed insulator films, as shown in FIG. 2 (c), according to the known photoetching technique, and finally a second Al wiring 8 having a thickness of about 1 .mu.m was formed according to the known sputtering and photoetching methods.

As described above, since the interlayer silicon oxide films can be formed at a low temperature with reduced stress according to this embodiment, the first Al wiring was absolutely free from void and disconnection. In addition, since the insulator films are planarized by the SOG film, no disconnection occurred in the second Al wiring.

When the double level Al interconnection structure was further subjected to heat treatment at a temperature of 450.degree. C. in a nitrogen gas atmosphere for 30 minutes, neither cracking in the insulator films nor formation of voids or disconnection in the Al interconnection occurred.

While triethoxyfluorosilane was used as the alkoxyfluorosilane in the preferred embodiment, other materials, for example, ethoxytrifluorosilane, diethoxydifluorosilane, methoxytrifluorosilane, dimethoxydifluorosilane, trimethoxyfluorosilane, butoxytrifluorosilane, dibutoxydifluorosilane and tributoxyfluorosilane can also be used.

The SOG film-forming coating solution may not be limited to the silanol solution as used in the above embodiment, and a solution containing a tetraalkoxysilane, alkylalkoxysilane or a solution containing at least one of these silane compounds may be used.

While aluminum was used as the wiring layer material in the above embodiment, other materials such as aluminum alloy, tungsten, molybdenum, titanium-containing tungsten, polysilicon, gold, platinum and titanium nitride films or their multi-layered films may also be used.

As described heretofore, since formation of the three-layered insulator film and its planarization can be carried out at a low temperature of 200.degree. C. or less according to the invention, cracking in the insulator film and formation of void or disconnection in the wiring layers can be prevented from occurring. Accordingly, the process of the invention has an effect of improving reliability and yield of semiconductor devices having multilevel interconnection structures.

Although one embodiment of the present invention has been described herein, it should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention.