US 5,397,931 AGrant
Voltage Multiplier
Issue Date:1995-03-14
•6 Claims
•16 Drawing Sheets
Abstract
The present invention relates to a voltage multiplier for generating an output voltage which is several times greater than the operating voltage for connection of a load connected to ground to the operating voltage by means of an N-channel power MOS transistor, comprising a plurality of capacitors (C1, C2, C3), a control input (C) for supplying a control signal, an output (V.sub.out), an operating voltage terminal (Vb) and a ground terminal (M). In known voltage multipliers, for rectification and multiplication of the output voltage diodes are used which reduce the maximum output voltage obtainable and restrict the clock frequency of the control signal to a few hundred kHz. In contrast, the voltage multiplier according to the invention has a high efficiency and can also be used at high clock frequencies; it includes a switchover means which comprises a control signal generator (S) having a plurality of inverters (I0, I1, I2, I3) and a first and second group of switch elements which are constructed as MOS field-effect transistors and can be driven with clock frequencies of up to 4 MHz. These MOS field-effect transistors are controlled by means of the control signal generator (S) by control signals in such a manner that the capacitors are periodically switched between a series connection and a parallel connection.
Metadata
Assignee
- Texas Instruments Deutschland GmbH
Inventor
- Erich Bayer
Application Information
Application Number:US 2558416
Filing Date:1994-06-08
Priority Date:1993-03-31
Art Unit:255
Classifications
IPC:
H01L 2706H02M 307H02M 725H03K 17687
Field of Search:
307363261;264;268;296.259
Patent Drawings (16 sheets)
Description
The invention relates to an integrated voltage multiplier for generating an output voltage which is several times greater than the operating voltage for connecting a load connected to ground to the operating voltage by means of an N-channel power MOS transistor, comprising a plurality of capacitors, a control input for supplying a clock signal, an output, an operating voltage terminal and a ground terminal.
Voltage multipliers are widely used in almost all areas of electrical engineering. For example, in motor vehicle systems it is frequently necessary to connect loads which are connected to ground to the operating voltage via an electronic switch without a voltage drop arising at the closed switch in order to ensure that the voltage drop at the load is as far as possible equal to the operating voltage.
In general, N-channel power MOS field-effect transistors are used as electronic switches for connecting the loads to the operating voltage, because P-channel MOS field-effect transistors with a low drain-source resistance are not available on monolithic integrated semiconductor circuits and consequently the voltage drop at the drain-source path of the N-channel MOS field-effect transistor is too high.
The necessary low voltage drop is achieved in the N-channel transistors in that the gate electrode of the power MOS field-effect transistor used as a power switch is connected to a voltage potential which is higher than the operating voltage potential. This means however, in practice that voltages of more than 15 V must be present on monolithic integrated semiconductor circuits on which only an operating voltage of about 5 V is available.
To generate on monolithic integrated semiconductor circuits voltages which are higher than the operating voltage, voltage multipliers are employed which are generally integrated into the semiconductor circuit and include a plurality of lateral bipolar diodes. The circuit configuration of such a voltage multiplier is for example shown in FIG. 1.
The circuit illustrated in FIG. 1 represents a voltage multiplier which comprises a control input C, an output and an operating voltage terminal B and which includes of four diodes D1 to D4, three capacitors C1 to C3 and three inverters I1-I3. The output of the voltage multiplier is connected to the gate electrode of an MOS field-effect transistor which serves as a switch for switching the load R.sub.L to the operating voltage Vb. The three inverters are connected in series and controlled via the control input C.
If the voltage multiplier illustrated in FIG. 1 is connected to the operating voltage and the control input C of the voltage multiplier is in the L state, firstly the capacitor C2 and the gate capacitance of the MOS field-effect transistor acting as a capacitor are charged. If the control input changes to the H state, the outputs of the inverters I1 and I3 change to the L state and the capacitors C1 and C3 are consequently charged. The charge quantities Q1, Q2 and Q3 stored in the respective capacitors C1, C2 and C3 are conveyed when the capacitors are discharged via the diodes D2-D4 to the gate electrode of the MOS field-effect transistor so that a charge quantity Q1+Q2+Q3 is additionally added to the charge quantity Q4 already present in the gate electrode. If this transfer charging process is carried out with high enough clock frequency, on a time average at the gate electrode a charge quantity Q corresponding to the sum of the individual charges Q1 to Q4 is present which generates at the gate electrode of the field-effect transistor a voltage corresponding to a multiple of the operating voltage.
The known voltage multiplier according to FIG. 1 has however the serious disadvantage that lateral bipolar diodes D1 to D4 are necessary for rectifying the voltages at the capacitors C1 to C3. Lateral diodes are used because they have reverse voltages of the order of magnitude of the operating voltage. However, lateral diodes have relatively long switch-through times so that the clock frequency supplied to the control input C for reverse charging of the capacitors C1 to C3 is limited to a 20 few hundred kHz. Furthermore, when using this voltage multiplier in an integrated semiconductor circuit the lateral diodes give rise to parasitic effects which are initiated by vertical substrate PNP transistors which are connected when the lateral diodes are operated in the forward direction. A further disadvantage is to be seen in that the use of silicon diodes reduces the voltage multiplied at the output by each diode by 0.7 V so that the efficiency of the known voltage multiplier is not more than 60 to 80%.
In view of these disadvantages the problem underlying the invention is to provide an integrated voltage multiplier which can be used at high frequencies and has high efficiency.
In a voltage multiplier for generating an output voltage which is several times greater than the operating voltage for connecting a load connected to ground to the operating voltage by means of an N-channel power MOS transistor, comprising a plurality of capacitors, a control input for supplying a clock signal, an output, an operating voltage terminal and a ground terminal this problem is solved, by the features that the output is connected via a unidirectionally conductive circuit element to the operating voltage terminal, that a switchover means is provided which comprises a control signal generator and a first group of switch elements having control terminals which are connected to one or more outputs of the control signal generator so that the first group of switch elements are switchable by means of control signals from the control signal generator between a conductive and a nonconductive state, and a second group of switch elements having control terminals which are connected to a further output of the control signal generator so that the second group of switch elements are switchable by means of a further control signal from the control signal generator between a conductive and a nonconductive state, that in each case two of the switch elements of the first group of switch elements connect the positive and the negative electrode of a capacitor to the operating voltage terminal and the ground terminal respectively, that the switch elements of the second group are connected to the capacitors in such a manner that they form a series circuit between the operating voltage terminal and the output in which a respective switch element and a capacitor lie alternately, and that the two groups of switch elements are driven by the control signal generator in such a manner that they are alternately in the conductive and in the nonconductive state and during the operation have opposite states.
Advantageous further developments of the invention are characterized in detail in the subsidiary claims.
Hereinafter an example of embodiment of the invention will be explained in detail with the aid of the drawings, wherein:
FIG. 1 shows a conventional voltage multiplier,
FIG. 2 shows an embodiment of the voltage multiplier according to the invention,
FIG. 3 shows the embodiment of FIG. 2 in a first state and
FIG. 4 shows the embodiment of FIG. 2 in a second state.
In contrast to the known voltage multiplier shown in FIG. 1, in which the rectification and addition of the capacitor currents is by means of lateral diodes, in the voltage multiplier illustrated in FIG. 2 a switchover means comprising MOS field-effect transistors is provided by which the capacitors C1-C3 are connected together in series so that the capacitor voltages are summated.
As apparent from FIG. 2, the voltage multiplier comprises the capacitors C1, C2 and C3 for generating an output voltage V.sub.out which is several times greater than the operating voltage Vb, an operating voltage terminal B, a ground terminal M, a control input C for supplying a clock signal and an output A to which the gate electrode of an N-channel power transistor N1 is connected.
The voltage multiplier of FIG. 2 further includes for switching over the capacitors C1, C2 and C3 a switchover means which comprises a circuit section S and a plurality of switch elements having control terminals which are controlled by control signals by means of the control signal generator S in such a manner that the capacitors C1, C2 and C3 are periodically switched between a parallel circuit and a series circuit. The control signal generator S includes a plurality of inverters I0, I1, I2 and I3, an input connected to the control input C of the voltage multiplier and a first, second and third output for furnishing control signals, the control input C being the inverter input of an input inverter I0 and the first, second and third outputs being the outputs of a first, second and third inverter I1, I2 and 13.
The switch elements are preferably formed by MOS field-effect transistors N12 to N19 and P13 to P21. Via the N-channel power MOS field-effect transistor N1 serving as electronic switch a load R.sub.L can be connected to the output A of the voltage multiplier. If the voltage multiplier 20 in operation, the output voltage V.sub.out increased compared with the operating voltage Vb is present at the output thereof and consequently the transistor N1 opens and connects the load R.sub.L to the operating voltage Vb.
Each capacitor C1, C2 and C3 of the voltage multiplier is connected to two MOS field-effect transistors N12 and P14, N16 and P17, N19 and P20, used as switch elements, of a first group of switch elements and to the source-drain paths thereof in series, so that the negative electrodes of the capacitors C1, C2 and C3 are each connected via a drain-source path of the N-channel field-effect transistors N12, N16 and N19--which form a first subgroup of the first group of switch elements-to the mass terminal M when the field-effect transistors N12, N16, N19 of said subgroup are in the conductive state. The positive electrodes of the capacitors C1, C2 and C3 are each connected via the drain-source paths of the P-channel field-effect transistors P14, P17 and P20--which form another subgroup of a first group of switch elements--to the operating voltage terminal B when the field-effect transistors of the other subgroup are in the conductive state, i.e. when the P-channel transistors P14, P17 and P20 are in the conductive state.
A second group of switch elements of the voltage multiplier is formed by P-channel MOS field-effect transistors P13, P15, P18 and P21. The drain-source paths of these transistors and the capacitors C1, C2 and C3 are connected alternately in series so that they form a series circuit between the operating voltage terminal B and the output A, in which a respective switch element and a capacitor alternately lie. The MOS field-effect transistors P13 and P21 connect the capacitor C1 and the capacitor C3 to the operating voltage terminal B and to the output A respectively when the transistors P13 and P21 are in the conductive state.
Hereinafter the mode of operation of the voltage multiplier illustrated in FIG. 2 will now be described in detail.
To make an output voltage higher than the operating voltage available at the output of the voltage multiplier, as already mentioned the switching state of the field-effect transistors of the first group and of the second group are periodically changed in such a manner that the capacitors are switched alternately from a parallel connection to a series connection. If the clock signal present at the control input C is in the H state, the field-effect transistors of the first group are conductive and the field-effect transistors of the second group are nonconductive so that the capacitors C1, C2 and C3 are connected in parallel to each other and lie in each case between the operating voltage terminal B and the ground terminal M. Each capacitor is charged thereby to the operating voltage Vb. If the clock signal present at the control input is in the L state, the field-effect transistors of the two groups assume opposite switching states so that the capacitors C1, C2 and C3 are connected in series and the capacitor C1 is connected via the transistor P13 to the operating voltage terminal B and the capacitor C3 via the transistor P21 to the output A. There is then a voltage drop of approximately 4 Vb between the output A and ground M.
The first state of the voltage multiplier (control signal input C: H) will be explained in detail hereinafter with the aid of FIG. 3. When the voltage multiplier is connected to the operating voltage Vb, a charging current flows via the transistor P22 to the gate capacitor (capacitance of the gate electrode of N1) of the transistor N1 serving as switch, which is connected between output and ground terminal. After completion of this charging operation the output voltage at the output A has risen to a voltage value V.sub.out which can be calculated in accordance with the following equation:
In this equation, V.sub.P22 is the voltage drop at the drain-source path of the transistor P22.
Now, when the clock signal at the control input C of the voltage multiplier is in the H state, the outputs of the inverters I3 and I1 are in the L and H state respectively. Consequently, the gate-source voltages of the P-channel transistors of the one subgroup are negative and those of the N-channel transistors of the other subgroup are positive so that the transistors P14, P17 and P20 and the transistors N12, N16 and N19 are rendered conductive and connect the positive electrodes and the negative electrodes of the capacitors C1, C2 and C3 to the operating voltage terminal A and to the ground terminal M respectively.
The capacitors C1, C2 and C3 then connected in parallel are now simultaneously charged up to the operating voltage Vb. The period of the clock signal here must be dimensioned so that the charging time required to charge the capacitors is shorter than the half period of the clock signal. The transistors of the second group of switch elements, i.e. the P-channel transistors P13, P15, P18 and P21, are all nonconductive here so that the electrical connections between the capacitors C1, C2 and C3 are interrupted. This is achieved in that the further output of the inverter 12 connected to the gate electrodes of said transistors is in the H state during the first switching state and this ensures that the gate-source voltages of the P-channel transistors are positive so that the transistors P13, P15, P18 and P21 remain in the nonconductive state.
Hereinafter, with reference to FIG. 4 the second state of the voltage multiplier (control signal input C:L) will be described. When the clock signal at the control input C changes its electrical state and goes into the L state, the outputs of the inverters I1 and I3 are switched to the L state and the H state respectively. The result of this is that the gate voltages of the N-channel transistors N12, N16 and N19 drop to ground potential so that said transistors are changed to the nonconductive state and interrupt the electrical connections between the negative electrodes of the capacitors and the ground terminal. The P-channel transistors P14, P17 and P20 are likewise nonconductive and interrupt the electrical connections between the positive electrodes of the capacitors and the operating voltage terminal B, since the gate-source voltages of said capacitors are positive when the output of the inverter 13 is in the H state.
However, the P-channel transistors P13, P15, P18 and P21 are in the conductive state here because the output of the inverter I2 connected to the gate electrodes of said transistors is in the L state during the second switching state and consequently the gate-source voltages of the P-channel transistors P13, P15, P18 and P21 are negative. The negative electrode of the capacitor C1 is thus connected to the operating voltage terminal B and the capacitors C1, C2 and C3 are connected in series; the positive electrode of the capacitor C3 is connected to the output A of the voltage multiplier. Accordingly, the capacitors fully charged during the first switching state and now connected in series charge the gate capacitor of the transistors N1 to such an extent that the gate voltage of the transistor N1 rises to four times the operating voltage. For the charging voltage at the series-connected 20 capacitors C1, C2 and C3, which are each charged to the operating voltage Vb, is added to said operating voltage. Consequently, at the output A of the voltage multiplier a voltage V.sub.out can be tapped off which corresponds approximately to four times the operating voltage Vb.
If V.sub.out <Vb, during the charging of the capacitors C1, C2 and C3 a current also flows via the transistor P22 to the output A of the voltage multiplier and consequently the output voltage V.sub.out rises during the charging of the capacitors and thus prevents discharging of said capacitors. Consequently, the capacitor voltages after the charging are each equal to Vb so that directly after the switchover to the series connection the charge voltage between the negative electrode of the capacitor C1 and the positive electrode of the capacitor C3 is 3 Vb.
An optimum functioning of the voltage multiplier requires that the MOS field-effect transistors and in particular the P-channel MOS field-effect transistors open and close completely. Consequently, the controlling gate electrodes of the P-channel transistors must be connected to the highest voltage available in the voltage multiplier. In the present example of embodiment the highest available voltage is at the output A which via the 9ate electrode of the transistor P22 connected as diode is always electrically connected to the conductor L1. For the same reason, the gate electrodes of all the P-channel transistors require control voltages which lie above the operating voltage Vb. For this reason the operating voltage terminals of the inverters I1, I2 and I3 are connected to the conductor L1. This is the only way of ensuring that the control voltages at the gate electrodes of the MOS field-effect transistors are higher than the operating voltage Vb in the respective necessary cases.
The voltage multiplier of the type described can be operated with high clock frequencies. The clock frequencies may be up to 4 MHz, since the MOS field-effect transistors used can be switched very rapidly from the conductive to the nonconductive state.
Claims
I claim:
1. An integrated voltage multiplier for generating an output voltage greater in magnitude by a multiple of the operating voltage for connecting a load connected to ground to the operating voltage via an N-channel power MOS transistor, said voltage multiplier comprising: a control input for providing a clock signal; an output; an operating voltage terminal; a ground terminal; a unidirectionally conductive circuit element interposed between the operating voltage terminal and the output and respectively connected thereto; switch over means comprising a control signal generator; a first group of switch elements having control terminals connected to respective outputs of said control signal generator; said first group of switch elements being switchable in response to the generation of respective control signals from said control signal generator and applied to the control terminals of said first group of switch elements so as to switch said first group of switch elements between a conductive and a nonconductive state; a second group of switch elements having control terminals connected to a further output of said control signal generator; said second group of switch elements being switchable between a conductive and a nonconductive state in response to the application of a further control signal from said control signal generator to the control terminals of said second group of switch elements; a plurality of capacitors operably interconnected between said first and second groups of switch elements; respective pairs of switch elements included in said first group of switch elements connecting the positive and the negative electrodes of a capacitor corresponding thereto to said operating voltage terminal and to said ground terminal respectively; said switch elements of said second group of switch elements being connected to said plurality of capacitors to form a series circuit of said plurality of capacitors between said operating voltage terminal and the output having a respective switch element of said second group of switch elements and a capacitor of said plurality of capacitors arranged in an alternating sequence; said first and second groups of switch elements being driven by the respective control signals from said control signal generator in an alternating sequence such that said first and second groups of switch elements are alternately in the conductive and in the nonconductive states wherein said first group of switch elements are in the conductive state when said second group of switch elements are in the nonconductive state and vice-versa.
2. A voltage multiplier as set forth in claim 1, wherein said control signal generator comprises a plurality of inverters and having an input connected to the control input and first, second and third outputs for providing control signals; said plurality of inverters providing inverter outputs as the first, second and third outputs of said control,signal generator, respectively.
3. A voltage multiplier as set forth in claim 1, wherein the first output of said control signal generator is connected to the control terminals of switch elements included in a subgroup of the first group of switch elements; the second output of said control signal generator providing the further control signal of said control signal generator connected to the control terminals of said second group of switch elements; the third output of said control signal generator being connected to the control terminals of another subgroup of said first group of switch elements.
4. A voltage multiplier as set forth in claim 3, wherein the switch elements of said one subgroup of said first group of switch elements are N-channel, MOS field-effect transistors; the switch elements of the other subgroup of said first group of switch elements are P-channel MOS field-effect transistors; the switch elements of said second group of switch elements are P-channel MOS field-effect transistors.
5. A voltage multiplier as set forth in claim 4, wherein said unidirectionally conductive circuit element is a P-channel MOS field-effect transistor.
6. A voltage multiplier as set forth in claim 5, wherein said plurality of inverters comprising said control signal generator are respectively provided with operating voltage terminals; the operating voltage terminals of said plurality of inverters being connected to said output, to the gate electrode of said P-channel MOS field-effect transistor and to ground terminal.