Electrically Programmable Internal Power Voltage Generating Circuit

The present invention relates to semiconductor memory devices, and more particularly, to electrically programmable internal power voltage generating circuits.

As the degree of integration of semiconductor memory devices has increased, the size of elements such as transistors constituting those memory devices has been reduced. Accordingly, if a voltage from an external power source is applied across such reduced size transistors without any conversion, that transistor may be subjected to the occurrence of strong electric fields and stress. This may result in an increase in defects in each of those transistors. Hence, in a highly integrated semiconductor memory device larger than sixteen megabytes, an internal power voltage generating circuit should be used which reduces the amplitude of the voltage from an external power voltage to an internal power voltage of a given amplitude suitable for the memory device. For example, when the external power voltage is approximately five volts, an internal power voltage with an amplitude of approximately four volts is used. The internal power voltage together with the external power voltage have yet to be lowered in currently available memory devices over sixteen megabytes. In order to reduce the amplitude of the external power voltage to the amplitude of the internal power voltage, an internal power voltage generating circuit is required for uniformly providing the internal power voltage within the chip.

In conventional internal power voltage generating circuits, a reference voltage generator will generate a reference voltage so that an internal power voltage of a desired amplitude can be produced. A comparator such as a differential amplifier then compares the amplitude of the internal power voltage with the reference voltage in order to control the amplitude of the internal power voltage provided to devices within the chip. A driver will then convert an external power voltage, into an internal power voltage, in response to the control of the comparator. The internal power voltage, provided at the output terminal of the driver is thus applied to each memory device on the chip connected to one input terminal of the comparator. Therefore, in each memory device, the internal power voltage produced at the output terminal of driver will be sensed by the comparator, and will be applied to each memory device on that chip which is simultaneously corrected to that input terminal of the comparator. Consequently, in each of those memory devices connected to the comparator, the amplitude of the interval voltage as lowered to a given level is then sensed by the comparator, and output voltage of the comparator is adjusted for example, to a lower amplitude in order to again control the voltage of the internal power from the devices within the chip.

So long as a voltage from an external power source is supplied to such a conventional semiconductor memory device, the internal power voltage generating circuit operates and the constant internal power voltage is provided as long as the amplitude of the voltage provided by the external power source is above a constant amplitude. It is often necessary however, to have an internal power voltage supplied to each circuit of the chip at an amplitude equal to that of the external power voltage, as for example, during a reliability test of the chip. When manufacture of the chip is completed, a "burn-in test" is usually performed by the more conscientious semiconductor manufacturers in order to detect any defects within the chip. The "burn-in test" is a test in which a high voltage in excess of a regulated external power voltage of the chip is applied to each device constituting the chip, for a long time at a high temperature in order to detect defective devices within the chips. Since the stress applied to each device constituting a chip is increased, defective chips should theoretically be easily detected. With currently available semiconductor devices however, even though the amplitude of the external voltage is raised, a voltage applied to the chip will not be raised above the internal power voltage. Therefore, an effective and reliable "burn-in test" can not be performed and a defective chip can not be easily detected; the manufacturer will consequently have a lower reliability among the semiconductor memory devices shipped to customers after being subjected to the ineffective "burn-in test."

It is therefore, an object of the present invention to provide an improved semiconductor memory device.

It is another object to provide a semiconductor memory device with an improved internal power voltage generating circuit.

It is yet another object to provide an internal power voltage generating circuit capable of accommodating electrical programming of the amplitude of a voltage provided b y an internal power generating circuit.

It is still another object to provide an electrically programmable internal power voltage generating circuit capable of furnishing an internal voltage having the same amplitude as a given voltage or an external power voltage.

It is still yet another object to provide an internal power voltage generating circuit capable of permitting electrical programming of the amplitude of the voltage provided by the internal power voltage generating circuit to enable the internal voltage to rise to the same amplitude as either a given voltage or the amplitude of the voltage provided by an external power source.

In order to achieve these and other objects, according to one aspect of the present invention a semiconductor memory device may be constructed with a reference voltage generator, a driver circuit with one terminal of a channel connected to an external power source generating a given internal power voltage, and a differential amplifier connected to receive outputs of a reference voltage generator and the internal power voltage, and to transfer the internal power voltage to a control terminal of the driver circuit. The internal power voltage generating circuit may include a voltage sensing circuit and a reference voltage controller. The voltage sensor senses a voltage applied to a given pad and generates a first or second output in dependence upon the sensed voltage level. Moreover, the reference voltage controller generates potential from the reference voltage generator to a first or second potential in dependence upon the first or second output from the voltage sensor, with the first and second outputs, that is logic "high" and "low" levels respectively, or logic "low" and "high" levels respectively, being complementary to each other. The first and second potentials may be the external power voltage and reference voltage respectively, or the reference voltage and external power voltage respectively.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made to the following detailed description, in conjunction with the accompanying diagrammatic drawings, in which:

FIG. 1 is a circuit diagram of a conventional internal power voltage generating circuit;

FIG. 2 is a block diagram of an internal power voltage generating circuit according to one example of a preferred embodiment of the present invention;

FIG. 3 is a circuit diagram of the internal power voltage generating circuit shown in FIG. 2;

FIG. 4 is a partial, more detailed circuit diagram illustrating an example of operation of the circuit of FIG. 3; and

FIG. 5 is a circuit diagram of an internal power voltage generating circuit according to another example of a preferred embodiment of the present invention.

Turning now to the drawings, FIG. 1 is a circuit diagram of a conventional internal power voltage generating circuit. A reference voltage generator 50 generates a reference voltage V.sub.ref so that a desired internal power voltage can be produced. A comparator 30 in the form of a differential amplifier compares the internal power voltage into V.sub.CC with the reference voltage V.sub.ref in order to control output of the internal power voltage. A single transistor driver 20 converts an external power voltage, ext. V.sub.CC, into an internal power voltage, int. V.sub.CC, in response to the control of the comparator 30. The internal power voltage, int. V.sub.CC, provided at the output terminal of driver 20 is applied to each memory device (not shown in FIG. 1) on the chip connected to the gate of transistor 4 serving as one input terminal of the comparator 30. Therefore, in each memory device, the internal power voltage, int. V.sub.CC, produced at the output terminal of driver 20 is sensed by comparator 30, and is applied to each memory device (not shown in FIG. 1) on the chip which are connected in common to comparator 30. Therefore, in each of those memory devices connected to comparator 30, the interval voltage int. V.sub.CC is lowered to a given amplitude is then sensed by comparator 30, and output voltage of the comparator 30 i.e. , the potential level at node G1, goes to a lower amplitude with the result that driver 20 is made more conductive and the amplitude of the internal power voltage int. V.sub.CC is again compensated.

In the semiconductor memory device of FIG. 1, if only a power voltage is supplied, the internal power voltage generating circuit is operated and the constant internal power voltage int. V.sub.CC is produced as long as the amplitude of the external power voltage ext. V.sub.CC is above a constant level. It is often necessary to have an internal power voltage, int. V.sub.CC, supplied to each circuit of the chip at a level of the external power voltage, ext. V.sub.CC, as for example, during a reliability test of the chip. When manufacture of the chip is completed, a "burn in test" is performed to detect the defects of the chip. With currently available semiconductor devices, even though the external power voltage ext. V.sub.CC is raised, a voltage applied to the chip is not raised above the internal power voltage, int. V.sub.CC. Therefore, the effective "burn in test" may not be performed and a defective chip is not easily detected with a resulting lower reliability among semiconductor memory devices shipped to customers after testing.

Referring now to FIG. 2, an internal power voltage generating circuit includes a voltage sensing circuit 100, a latch circuit 200, a reference voltage controller 300 and an internal power voltage generator 400. The voltage sensing circuit 100 is connected to a pad 10 of the chip to which a pin is coupled to sense the voltage applied to pad 10. The latch circuit 200 continuously latches the voltage sensed by the voltage sensing circuit 100. The reference voltage controller 300 transfers or blocks a reference voltage V.sub.ref produced from a reference voltage generator 50, and is connected to the internal power voltage generator 400. The voltage of an external power voltage, ext. V.sub.CC, is applied to the reference voltage controller 300. The internal power voltage generator 400 receives either one of the reference voltage V.sub.ref or the external power voltage and provides an internal power voltage, int. V.sub.CC.

Referring to FIG. 3, the voltage sensing circuit 100 has a serial array of first, second, third and fourth PMOS transistors P1, P2, P3 and P4 for lowering a voltage level applied to the pad 10, resistor R1 connected between one terminal of a channel of the fourth PMOS transistor P4 and a local ground voltage V.sub.SS. First, second and third inverters INV1, INV2 and INV3 are serially connected between a common terminal at the node C.sub.0 formed by the fourth PMOS transistor P4 and resistor R1, and an electrically conductive electrode of the channel switching transistor N1. The gate of transistor N1 is connected between a node C.sub.2 formed between the output terminal of the second inverter INV2 and input terminal of the third inverter INV3. PMOS transistors P1 through P4 may be different in respective channel size and in number, in dependence upon the variation of the internal power voltage. Also the number of the inverters INV1 through INV3 may be varied in dependence upon the logic state or amplifying operation. Moreover, each inverter is preferably constructed using CMOS circuitry.

Latch circuit 200 is shown with a resistor R2 connected to an external power source voltage ext. V.sub.CC, and inverters INV4 and INV5 coupled back-to-back for transferring and latching a potential received through the resistor R2. Thus, the output signal of latch circuit 200 is continuously supplied to the reference voltage controller 300. The reference voltage controller 300 is shown with a transmission gate TH1 having a control terminal connected to receive the output signal of the latch circuit 200, an inverter INV6 and a pull-up transistor T1. The pull-up transistor T1 is turned on only when the transmission gate TH1 is turned off by the output signal of latch circuit 200 to raise the voltage of a node C.sub.7 to the level of the external power voltage ext. V.sub.CC. Node C7 is connected to an input terminal of the internal power voltage generator 400. In order provide protection from either signal noise in the external power voltage ext. V.sub.CC or an undesirably high voltage applied to the pad 10, pull-up transistor T1 is turned on only when a nearly direct voltage is applied to the pad 10. Therefore, pull-up transistor T1 must be considerably smaller in size than other transistors in the circuits. The reference voltage generator 50 and the internal power voltage generator 400 are of generally known construction; accordingly, no further description for these components will be given.

An example of the operation of the circuit shown in FIG. 3 will now be described.

First, a description is given in the situation where either no voltage is applied to pad 10 or the amplitude of the voltage applied to pad 10 does not exceed 5.5 volts in a semiconductor device of less than sixteen megabytes during a normal operation of the device. Node C.sub.0 is set to logic "low" level through the PMOS transistors P1 to P4. Usually, the threshold voltage of one PMOS transistor is about one volt. Therefore, nodes C.sub.1, C.sub.2 and C.sub.3 are set to logic "high", "low" and "high" levels, respectively, and the switching transistor N.sub.1 is turned off. Node C.sub.4 of latch circuit 200 is set to logic "high" level by resistor R.sub.2 and this logic "high" level is latched by inverters INV4 and INV5. Here, at node C.sub.4, a signal of logic "high" level is continuously latched regardless of changes in the output of the voltage sensing circuit 100. Node C.sub.5, therefore, remains at a logic "low" level. The transmission gate TH1 of the reference voltage controller 300 is turned on by the logic "low" level of the latch circuit 200, and provides the reference voltage V.sub.ref produced from the reference voltage generator 50 to the internal power voltage generator 400. Moreover, pull-up transistor T1 is turned off by the "high" level of node C.sub.6. Then, the internal power voltage generator 400 produces a constant internal power voltage int. V.sub.CC corresponding to the reference voltage V.sub.ref.

In the situation in which a high voltage, over 5.5 V, is applied to the pad 10, node C.sub.0 of voltage sensing circuit 100 is set to logic "high" level through PMOS transistors P1 to P4. Hence, nodes C.sub.1, C.sub.2 and C.sub.3 are set to logic "low", "high" and "low" levels, respectively, and switching transistor N1 is turned on by the "high" level of node C.sub.2. Then, as is shown in FIG. 4, node C.sub.4 of latch circuit 200 is grounded through transistor Q32, a driving section of third inverter INV3 serially coupled between ext V.sub.CC, node C.sub.3 and V.sub.SS and a channel (which is in a conducting state) of switching transistor N1. Since node C.sub.4 of latch circuit 200 is at a logic "low" level, node C.sub.5 is set to logic "high" level. As a result, latch circuit 200 generates logic "high" level signals, thereby turning OFF transmission gate TH1. At this time, even if the voltage applied to pad 10 is lowered or disconnected, latch circuit 200 continuously produces a signal of logic "high" level. Thus, since transmission gate TMH of reference voltage controller 300 is turned off, reference voltage V.sub.ref generated by reference voltage generator 50 is not received by the internal power voltage generator 400. Moreover, pull-up transistor T1 is turned on and charges node C.sub.7 to a potential level of the external power voltage ext. V.sub.CC. Therefore, the output of reference voltage controller 300 goes to the amplitude of the external power voltage ext. V.sub.CC. The external power voltage ext. V.sub.CC is transferred to an input terminal of a differential amplifier in internal power voltage generator 400. Then, a driver T10 is turned on by the operation of the differential amplifier and produces the internal power voltage int. V.sub.CC having the amplitude of the external power voltage ext. V.sub.CC. Thereafter, regardless of whether the voltage applied to pad 10 is changed or disconnected, the internal power voltage, int. V.sub.CC, is generated at the amplitude of the external power voltage, ext. V.sub.CC. In other words, if a user supplies to pad 10 of the chip, a high voltage in excess of a regulated value, the internal power voltage int. V.sub.CC is raised to the level of the external power voltage ext. V.sub.CC. Consequently, the user can freely produce either an internal power voltage int. V.sub.CC of four volts during normal operation, or about five volts of external power voltage, ext. V.sub.CC, during testing, under control of the amplitude of the voltage applied to pad 10.

Referring now to FIG. 5, in another embodiment of the present invention the internal power voltage generating circuit does not include latch circuit 200 shown in the embodiment represented by FIG. 3. Therefore, only when a voltage in excess of 5.5 V is applied to pad 10 is the internal power voltage, int. V.sub.CC, raised to the amplitude of the external power voltage, ext. V.sub.CC. In other words, since there is no latch circuit, a voltage in excess of about 5.5 V must be continuously applied to pad 10 in order for internal power voltage generator 400 to raise the internal power voltage int. V.sub.CC to the same amplitude as the external power voltage ext. V.sub.CC. Hence, in the circuit of FIG. 3, once a high voltage in excess of 5.5 V is applied to pad 10, the internal power voltage, int. V.sub.CC, is continuously maintained at the amplitude of the external power voltage, ext. V.sub.CC. In the circuit of FIG. 3 therefore, even if the voltage applied to pad 10 is disconnected, all external power voltages ext V.sub.CC must be completely disconnected from pad 10 in order for the internal power voltage, int. V.sub.CC to be set to the amplitude of reference voltage V.sub.ref. In the circuit of FIG. 5 however, the internal power voltage int. V.sub.CC is controlled by only the voltage applied to pad 10. Furthermore, even if the operating voltage of a highly integrated semiconductor memory device is lowered, by adjusting transistors P1-P4 of the voltage sensing circuit, the amplitude of a voltage applied to the pad and sensed by the voltage sensing circuit, can be controlled.

In the foregoing description of examples of an internal power voltage generating circuit which may be readily integrated into the monolithic structure of each integrated semiconductor device, the amplitude of the internal power voltage is electrically programmed so as to have the same amplitude as either a given reference voltage or external power voltage. Therefore, defective chips can be easily detected by applying the external power voltage to the interior of the chip during a "burn-in test", and the reliability of the semiconductor memory devices subjected to testing will be greatly improved.

While preferred embodiments of the present invention have been particularly shown and described, it will be understood by those skilled in the art that foregoing and other changes in form and details may be made without departing from the spirit and scope of the present invention.