Enabling Data Access of a Unit of Arbitrary Number of Bits of Data in a Semiconductor Memory

1. Field of the Invention

The present invention relates generally to dynamic semiconductor memory devices having a multi-bit configuration as a unit and image data generation device for generating image data of a selected number of bits, and more particularly, to memory devices enabling selective read of a specified smaller number of bits out of a given larger plurality of bits.

2. Description of the Background Art

A conventional dynamic random access memory device (hereinafter referred to as DRAM) generates data by 1 bit, 4 bits or 8 bits. DRAM devices of .times.4 bits and .times.8 bits are generally called memory devices having a multi-bit configuration.

In the field of image processing, data is often used on an basis such as 6 bits or 7 bits. This is because of the following reason. That is, memories are originally used in computers to store 4-bit, 8-bit or 16-bit data. On the other hand, 6-bit or 7-bit data is used for image processing. While a 8-bit memory has a large memory capacity, it incurs more expensive manufacturing costs, and production of special 6-bit or 7-bit memories also costs much.

Such image data of 6-bit or 7-bit is used for forming such special images as those in a search mode and slow reproduction (see "Home VTR Containing Field Memory for Correcting Crossbar and Skew Distortion in Search Mode" NIKKEI ELECTRONICS, Oct. 20, 1986, Vol. 406).

FIG. 12A is a block diagram showing a device for generating 6-bit luminance data shown in the above-described article.

With reference to FIG. 12A the device includes .times.4-bit memory devices M1, M2 and M3 and a selector 50 for selecting 6-bit data. Luminance data is written in each of memory devices M1-M3 by 4 bits. Selector 50 alternately selects either 4-bit data from memory device M1 and 2-bit data from memory device M3 or 2-bit data from memory device M3 and 4-bit data from memory device M2 for each field. 6-bit luminance data is generated at the output terminal of selector 50 in this way.

Selector 50, however, requires 6 switch circuits for selecting 6-bit data, which necessitates an increased number of elements.

The memory device in FIG. 12A is considered to have the structure as shown in FIGS. 12B to 12D.

FIG. 12B is a block diagram of a DRAM having 4-bit configuration. FIG. 12C is a timing chart of the DRAM device of FIG. 12B.

With reference to FIG. 12B, the DRAM device comprises an RAS terminal for receiving a row address strobe signal RAS (hereinafter referred to as an RAS signal), a CAS terminal for receiving a column address strobe signal CAS (hereinafter referred to as a CAS signal), Add terminals for receiving an address signal Add, an OE terminal for receiving an output enable signal OE, data input/output terminals DQ1-DQ4 and a WE terminal for receiving a write control signal WE. Data input/output terminals DQ1-DQ4 receive input/output data.

The DRAM device further includes a memory cell array 1, a row decoder 2, a column decoder 3, an address buffer 4, an RAS buffer 5, a CAS buffer 6, an output buffer 7, an input buffer 8, a OE buffer circuit 90 and a WE buffer circuit 100.

Memory cell array 1 is divided into four memory cell array blocks 1a, 1b, 1c and 1d. A plurality of memory cells MC arranged in a matrix, word lines WL arranged in a row direction and bit lines BL arranged in a column direction are provided in each of memory cell array blocks 1a-1d. Row decoder 2 decodes a row address signal of an address signal applied in a time divisional manner to select one word line WL of each of memory cell array blocks 1a-1d. Column decoder 3 decodes a column address signal of an address signal applied in a time divisional manner to select one (a pair of bit lines) bit line BL of each of memory cell array blocks 1a-1d. As a result, a memory cell at the word line and the bit line selected by row decoder 2 and column decoder 3 is simultaneously designated in each of memory cell array blocks 1a-1d.

Address buffer 4 receives address signal Add to generate an internal address signal. The internal address signal is applied to row decoder 2 and column decoder 3.

RAS buffer 5 receives row address strobe signal RAS to generate an internal RAS signal. The internal RAS signal is applied to row decoder 2 and 0E buffer circuit 90.

CAS buffer 6 receives CAS signal to generate an internal CAS signal. The internal CAS signal is applied to column decoder 3.

OE buffer circuit 90 is coupled to output buffer 7 in a differential manner and connected to OE terminal data. OE buffer circuit 90 activates output buffer 7 in response to OE signal.

WE buffer circuit 100 is coupled to input buffer 8 in a differential manner and connected to WE terminal. WE buffer circuit 100 activates input buffer 8 in response to write enable signal WE.

Output buffer 7 receives data from memory cells of 4 bits and applies the received data to data input/output terminals DQ1-DQ4.

Input buffer 8 receives the 4-bit data from data input/output terminals DQ1-DQ4 and applies the same to designated memory cells of 4 bits.

FIG. 12C is a timing chart illustrating an operation of the DRAM device of FIG. 12B. The hatched portions of the drawing are in an arbitrary state.

A row address signal included in an address signal Add is strobed at a fall of RAS signal and a column address signal is strobed at a fall of CAS signal. A row address and a column address designate a memory cell in the memory cell array. The data from the input/output terminal DQ1-DQ4 is written at the designated memory cells, and the written data is read out from the memory cells.

FIG. 12D is a block diagram showing the output buffer of FIG. 12B. With reference to the figure, output buffer 7 includes data output buffers 71, 72, 73 and 74.

Each of data output buffers 71-74 is connected between the corresponding data input/output terminal DQ1-DQ4 and an I/O terminal of memory cell array 1 and enters a read allowed state or a read inhibited state (high impedance state) in response to the OE signal.

A common DRAM having a multi-bit configuration includes an output enable terminal, to which terminal an output enable signal OE (hereinafter referred to as 0E signal) is applied, thereby simplifying the structure of the image data generation device.

FIG. 13 is a block diagram showing an image data generation device using an OE signal. With reference to FIG. 13, the image data generation device includes data input/output terminals DQ1, DQ2, DQ3 and DQ4, memory devices M1, M2, and M3 of .times.4-bit configuration, a timing generator 51 and a selector 52.

Timing generator 51 generates output enable signals OE1 and OE2 and a selection signal .phi. in response to a clock signal .phi.. OE1 signal and OE2 signal are applied to memory devices M1 and M2, respectively, and .phi. signal is applied to selector 52.

Memory device M1 comprises output ports 1a, 1b, 1c and 1d, memory device M2 comprises output ports 2a, 2b, 2c and 2d and memory device M3 comprises output ports 3a, 3b, 3c and 3d. Output ports 1a-1d and 2a-2d are connected to data output terminals DQ1-DQ4, while output ports 3a-3d are connected to input terminals of selector 52. Selector 52 includes 2-input 1-output switch circuits 52a and 52b. Switch circuit 52a has input terminals connected to output ports 3a and 3b and an output terminal connected to a data input/output terminal DQ5. Switch circuit 52b has input terminals connected to output ports 3c and 3d and an output terminal connected to a data input/output terminal DQ6.

FIG. 14 is a timing chart of the image data generation device of FIG. 13. Memory device M1 outputs data when OE1 signal is at a low level, while memory device M2 outputs data when OE2 signal is at a low level. Memory device M3 outputs data at any time because 0E signal is fixed to a ground level. Selector 52 selects output ports 3a and 3c when .PHI. signal is at a low level and selects output ports 3b and 3d when .PHI. signal is at a high level. Data input/output terminals DQ1-DQ4 alternately receive 4-bit data from memory device M1 and 4-bit data from memory device M2, while data output terminals DQ5 and DQ6 alternately receive 2-bit data (3a-3c) and (3b, 3d) out of 4-bit data generated from memory device M3. Data input/output terminals DQ1-DQ6 obtain 6-bit data in this way.

Extremely high speed data processing is desirable in the field of the image processing.

However, an image data generation device should include selectors provided outside memory devices as shown in FIGS. 12A and 13 such that data read from the memory devices is output through interconnections and the selectors. Data transmission speed is reduced as a result. In addition, four data lines of each memory device are connected to inputs of each selector, making the interconnections complicated.

The present invention is directed to selectively inhibiting the memory device of FIGS. 13 and 14 from outputting a specified bit in order to avoid the necessity of a selector.

Such a memory device has not yet been producted.

An object of the present invention is to selectively inhibit read of a desired bit in a memory device having a multi-bit configuration.

Another object of the present invention is to enable high speed data processing in an image data generation device.

A further object of the present invention is to generate image data of an arbitrary number of bits in an image data generation apparatus, wherein an arbitrary number is different from the number of bits of each of memory devices used.

Briefly stated, according to one aspect of the present invention, a dynamic semiconductor memory device includes a memory cell array having a plurality of memory cells each storing 1-bit data, an operation mode designating signal receiver, a bit designating signal receiver and a read controller.

The operation mode designating signal receiver receives an external signal for designating an operation mode wherein read of a desired bit, out of a plurality of bits, is inhibited.

The bit designating signal receiver receives an external bit designating signal for designating a bit the read of which is to be inhibited, in response to the operation mode designating signal received by the operation mode designating signal receiver.

The read controller selectively inhibits read of desired bit data based on an externally generated read control signal and the bit designating signal received by the bit designating signal receiver.

In accordance with another aspect of the present invention, the dynamic semiconductor memory device further includes a write controller. The write controller selectively inhibits write of specified bit data, from among the data of a plurality of bits, based on externally generated write control signal and bit designating signal.

According to a further aspect of the present invention, an image data generation apparatus includes a plurality of dynamic semiconductor memory devices according to one aspect of the present invention and a signal generation device. The signal generation device generates a signal for setting each dynamic semiconductor memory device to operate in a write state, a signal for enabling the same to operate in a read state, a signal for designating an operation mode for inhibiting read of a specified bit out of the plurality of bits and a signal for designating a bit the read of which is to be inhibited out of the plurality of bits.

According to a still further aspect of the present invention, an image data generation device includes a plurality of dynamic semiconductor memory devices in accordance with another aspect of the present invention and a signal generation device.

In the device in accordance with one aspect of the present invention, the operation mode designating signal receiver receives an external operation mode designating signal. In response to the received operation mode designating signal, the bit designating signal receiver receives an external signal for designating a bit the read of which is to be inhibited out of a plurality of bits. The received bit designating signal is applied to the read controller which selectively inhibits an output of a specified bit in response to the applied bit designating signal. As a result, the number of bits can be reduced, thereby enabling data generation of a desired number of bits among the plurality of bits.

Since in the device according to another aspect of the invention a bit, is designated, and as a result, the write to the designated bit out of input data can be inhibited. As a result, the number of bits of input/output data can be reduced and write to and read from data of a desired number of bits can be performed among the larger plurality of bits of memory storage.

The device according to a still further aspect of the invention wherein read of at least one memory device is inhibited, enables generation of image data of a desired number of bits within the total number of bits of the plurality of dynamic semiconductor memory devices. It is therefore unnecessary to use a selector for selecting data read from a semiconductor memory device as is necessary in conventional art, enabling data reading at a high speed accordingly.

The device according to a still further aspect of the invention wherein a bit write to/read of which is to be inhibited is designated for at least one semiconductor memory device, enables generation of image data of a desired number of bits within the total number of bits of the plurality of semiconductor memory devices. With no selector used, high speed access is possible.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of a DRAM device according to one embodiment of the present invention.

FIG. 2 is a timing chart of the DRAM device of FIG. 1.

FIG. 3 is a block diagram of a read control circuit and an output buffer of FIG. 1.

FIG. 4 is a circuit diagram showing the details equivalent to one bit of FIG. 3.

FIG. 5 is a block diagram of an image data generation device for generating image data of an arbitrary number of bits.

FIG. 6 is a timing chart of the image data generation device of FIG. 5.

FIG. 7 is a block diagram showing a DRAM device according to another embodiment.

FIG. 8 is a timing chart of a write operation of the DRAM device of FIG. 7.

FIG. 9 is a block diagram of a write control circuit and an input buffer of FIG. 7.

FIG. 10 is a block diagram showing an image data generation device using the DRAM device of FIG. 7.

FIG. 11 is a timing chart illustrating a write operation of the image data generation device of FIG. 10.

FIG. 12A is a block diagram of a conventional image data generation device.

FIG. 12B is a block diagram of a DRAM having a 4-bit configuration.

FIG. 12C is a timing chart of the DRAM device of FIG. 12B.

FIG. 12D is a block diagram showing the output buffer of FIG. 12B.

FIG. 13 is a block diagram of a conventional data generation device.

FIG. 14 is a timing chart of the image data generation device of FIG. 13.

FIG. 1 a block diagram of a DRAM device according to one embodiment of the present invention. FIG. 2 is a timing chart of the DRAM device.

With reference to FIG. 1, the DRAM device comprises an RAS terminal for receiving a row address strobe signal RAS (hereinafter referred to as an RAS signal), a CAS terminal for receiving a column address strobe signal CAS (hereinafter referred to as a CAS signal), Add terminals for receiving an address signal Add, an OE terminal for receiving an output enable signal OE, data input/output terminals DQ1-DQ4 and a WE/WB terminal for receiving a write control signal WE and an operation mode designating signal WB in a time divisional manner. Data input/output terminals DQ1-DQ4 receive a bit designating signal for designating a bit the read of which is to be inhibited and input/output data in a time divisional manner. Operation mode designating signal WB inhibits read of a desired bit out of 4-bit data.

The DRAM device further includes a memory cell array 1, a row decoder 2, a column decoder 3, an address buffer 4, an RAS buffer 5, a CAS buffer 6, an output buffer 7, an input buffer 8, a read control circuit 9 and a write control circuit 10.

Memory cell array 1 is divided into four memory cell array blocks 1a, 1b, 1c and 1d. A plurality of memory cells MC arranged in a matrix, word lines WL arranged in a row direction and bit lines BL arranged in a column direction are provided in each of memory cell array blocks 1a-1d. Row decoder 2 decodes a row address signal of an address signal applied in a time divisional manner to select one word line WL of each of memory cell array blocks 1a-1d. Column decoder 3 decodes a column address signal of an address signal applied in a time divisional manner to select one (a pair of bit lines) bit line BL of each of memory cell array blocks 1a-1d. As a result, a memory cell at the word line and the bit line selected by row decoder 2 and column decoder 3 is simultaneously designated in each of memory cell array blocks 1a-1d.

Address buffer 4 receives address signal Add to generate an internal address signal. The internal address signal is applied to row decoder 2 and column decoder 3.

RAS buffer 5 receives row address strobe signal RAS to generate an internal RAS signal. The internal RAS signal is applied to row decoder 2 and read control circuit 9.

CAS buffer 6 receives CAS signal to generate an internal CAS signal. The internal CAS signal is applied to column decoder 3.

Read control circuit 9 is operably coupled to output buffer 7 and connected to WE/WB terminal, OE terminal and data input/output terminals DQ1-DQ4. Read control circuit 9 determines an existence of operation mode designating signal WB at a falling edge of internal RAS signal. When the circuit determines the existence of operation mode designating signal WB, it inhibits read of only the designated bit among 4-bit data in response to a bit designating signal applied to data input/output terminals DQ1-DQ4.

Write control circuit 10 is operably coupled to input buffer 8 and connected to the WE/WB terminal. Write control circuit 10 activates input buffer 8 in response to write enable signal WE.

Output buffer 7 receives data from memory cells of 4 bits and applies the received data to data input/output terminals DQ1-DQ4.

Input buffer 8 receives the 4-bit data from data input/output terminals DQ1-DQ4 and applies the same to designated memory cells of 4 bits.

FIG. 2 is a timing chart illustrating an operation of the DRAM device of FIG. 1. The hatched portions of the drawing are in an arbitrary state.

A row address signal included in an address signal Add is strobed at a fall of RAS signal and a column address signal is strobed at a fall of CAS signal. A row address and a column address designate a memory cell in the memory cell array.

An operation mode designating signal WB is strobed at a fall of RAS signal. The strobed WB signal being at a low level is regarded as the designation of the above-described operation mode. When a bit designating signal to be applied to each of data input/output terminals DQ1-DQ4 at that time is at a low level, read of the bit is allowed, while when the signal is at a high level, read of the bit is inhibited.

FIG. 3 is a block diagram showing the read control circuit 9 and the output buffer 7 of FIG. 1. With reference to FIG. 3, read control circuit 9 includes a mask enable signal generation circuit 9a, mask data registers 9b1, 9b2, 9b3 and 9b4 and OR gates 9c1, 9c2, 9c3 and 9c4. Output buffer 7 includes data output buffers 71, 72, 73 and 74. j is given to a corresponding bit number in the following description.

Mask enable signal generation circuit 9a determines an existence of an operation mode designating signal WB at a fall of an internal RAS signal. When the circuit determines the existence of operation mode designating signal WB, the circuit 9a generates a mask enable signal for activating mask registers 9b1-9b4. Each of mask data registers 9b1-9b4 is connected to the corresponding bit data input/output terminal DQj to hold a bit designating signal applied to the corresponding data input/output terminal DGj in response to the mask enable signal. Each of OR gates 9c1-9c4 has two input terminals and one output terminal, one input terminal being connected to receive 0E signal and the other input terminal being connected to receive a bit designating signal held by the corresponding mask data register 9bj. The respective OR gates 9c1-9c4 generate read control signals RC1, RC2, RC3 and RC4 for controlling read of each bit in response to the bit designating signal held by the corresponding bit mask register 9bj and OE signal. When the read control signal is at a low level, read is allowed, while when the read control signal is at a high level, read is inhibited.

Each of data output buffers 71-74 is connected between the corresponding data input/output terminal DQj and an I/O terminal of memory cell array 1 and enters a read allowed state or a read inhibited state (high impedance state) in response to the read control signal from the corresponding OR gate 9cj.

Operation of read control circuit 9 of FIG. 3 will be described. An operation mode designating signal WB is strobed at a fall of RAS signal. When the strobed WB signal is at a low level, mask enable signal generation circuit 9a generates a mask enable signal which activates all of mask data registers 9b1-9b4. Each of mask data registers 9b1-9b4 holds a bit designating signal applied to the corresponding data input/output terminal DQj. The held bit designating signal is applied to the corresponding OR gate 9cj. Each of OR gates 9c1-9c4 generates a read control signal RCj in response to a bit designating signal held by the corresponding mask data register 9bj. When read control signal RCj is at a low level, data output buffer 7j enters a read allowed state to output the corresponding one bit out of 4 bits. When read control signal RCj is at a high level, data output buffer 7j enters a read inhibited state (high impedance state).

FIG. 4 is a circuit diagram showing the details equivalent to one bit of FIG. 3. With reference to FIG. 4, mask data register 9bj includes an NMOS transistor 9d, an inverter 9e, an inverter 9f and an NMOS transistor 9g. NMOS transistor 9d passes a bit designating signal from data input/output terminal DQj in response to a mask enable signal generated from mask enable signal generating circuit 9a. Inverters 9e and 9f constitute a latch circuit. NMOS transistor 9g activates the latch circuit in response to RAS signal. In an active state, the latch circuit holds a bit designating signal applied through NMOS transistor 9d and applies the same to OR gate 9cj. OR gate 9cj generates a control signal for inhibiting read when the applied bit designating signal is at a high level and generates a control signal for allowing read only when the applied bit designating signal is at a low level and OE signal is at a low level.

A data output buffer 7j includes a preamplifier 7a, an inverter 7b, an NOR gate 7c, an NOR gate 7d, an NMOS transistor 7e and an NMOS transistor 7f. Preamplifier 7a amplifies one-bit data from a memory cell. NOR gates 7c and 7d each has two input terminals and one output terminal. NOR gate 7c has one input terminal connected to the output of OR gate 9cj, the other input terminal connected to receive one-bit data amplified by the preamplifier and an output terminal connected to a gate electrode of NMOS transistor 7e. NOR gate 7d has one input terminal connected to the output of OR gate 9cj, the other input terminal connected to receive one-bit data inverted by inverter 7b and an output terminal connected to the gate electrode of NMOS transistor 7f. Each of NMOS transistors 7e and 7f has a gate electrode, a drain electrode and a source electrode. The drain electrode of NMOS transistor 7e is connected to a power source voltage and the source electrode is connected to the drain electrode of NMOS transistor 7f and data input/output terminal DQj. The source electrode of NMOS transistor 7f is connected to a ground potential.

In data output buffer 7j structured as described above, both of NOR gates 7c and 7d output a low level signal when read control signal RCj is at a high level. NMOS transistors 7e and 7f both turn on as a result (a high impedance state). When read control signal RCj is at a low level, output states of NOR gates 7c and 7d are determined based on the level of one-bit data from preamplifier 7a or inverter 7b.

As described above, since the DRAM device shown in FIGS. 1-4 allows designation of bits the read of which is allowed and bits the read of which is inhibited upon application of a bit designating signal to a data input/output terminal, a combined use of those DRAM devices enables generation of data of a desired number of bits.

FIG. 5 is a block diagram showing an image generation device implemented with those DRAM devices of the invention for generating image data of an arbitrary number of bits. With reference to FIG. 5 and FIG. 13, the image data generation device of FIG. 5 differs from that of FIG. 13 in that memory devices M1-M3 shown in FIGS. 1 to 4 replace ordinary DRAMs and a timing generator 11 replaces the selector 52.

Timing generator 11 generates an RAS signal, a CAS signal, an OE1 signal, OE2 and OE3 signals, and a WE1/WB1 signal, a WE2/WB2 signal and a WE3/WB3 signal which are obtained by processing write control signal and an operation mode designating signal in a time divisional manner. OE1 and WE1/WB1 signals are applied to memory device M1, OE2 signal and WE2/WB2 signal are applied to memory device M2, and OE3 signal and WE3/WB3 signal are applied to memory device M3. The bit designating signal is applied to data input/output terminals DQ3-DQ6.

Memory devices M1-M3 allow data thereof to be read and a bit of a low level to be masked in response to a bit designating signal when operation mode designating signals WB1-WB3 and OE1-OE3 signals are received. The image data generation device designates a bit the read of which is to be inhibited only for memory device M3.

FIG. 6 is a timing chart of image data generation device of FIG. 5. With reference to FIG. 6, with operation mode designating signals WB1 and WB2 being fixed to a high level at all times, memory devices M1 and M2 read 4-bit data when OE1 and OE2 signals are active. Operation mode designating signal WB3 is brought down to a low level at a fall of RAS, while OE3 is set to have the same cycle as that of CAS signal. Data input/output terminals DQ3 and DQ4 and data input/output terminals DQ5 and DQ6 alternately receive a low level bit designating signal.

An operation of the image data generation device shown in FIGS. 5 and 6 will be described. Operation mode designating signals WB1-WB3 and bit designating signals applied to data input/output terminals DQ1-DQ6 are strobed at a fall of RAS signal. When operation mode designating signal WB3 is at a low level, memory device M3 captures the low level bit designating signal applied to data input/output terminals DQ3 and DQ4 in mask data registers 9b1 and 9b2 (see FIG. 3) and captures a high level bit designating signal applied to data input/output terminals DQ5 and DQ6 in mask registers 9b3 and 9b4. As a result, outputs 3a and 3b of memory device M3 are masked. Then CAS signal, OE1 signal and OE3 signal are brought down to a low level, whereby data 1a-1d are read from memory device M1, while data 3c and 3d are read from memory device M3. As a result, 6-bit data including 1a-1d and 3c-3d are obtained at data input/output terminals DQ1-DQ6. Then at a subsequent fall of RAS signal, operation mode designating signal WB3 and bit designating signals applied to data input/output terminals DQ3-DQ6 are strobed. In this cycle, the bit designating signals applied to data input/output terminals DQ3 and DQ4 are at a high level, while the bit designating signals applied to data input/output terminals DQ5 and DQ6 are at a low level, whereby data 3c and 3d of memory device M3 are masked to allow output of 3a and 3b data of memory device M3. As a result, 4-bit data 2a-2b and 2-bit data 3c and 3d are output from memory devices M2 and M3, respectively, in response to subsequent OE2 and OE3 signals.

As described in the foregoing, application of a bit designating signal to data input/output terminals DQ3 to DQ6 inhibits read of a specified bit, out of 4 bits of each of memory devices M1-M3. It is therefore possible to generate image data of an arbitrary number of bits.

FIG. 7 is a block diagram showing another embodiment of a DRAM device. With reference to the FIG. 7 and FIG. 1, the DRAM device of FIG. 7 differs from that of FIG. 1 in that a write control circuit 10' allowing inhibition of write of only a desired bit, out of four bits, replaces the write control circuit for writing 4-bit data and in that a signal for designating such an operation mode is applied to WE/WB terminal.

Write control circuit 10' is operably connected to input buffer 8 and to WE/WB terminal and data input/output terminals DQ1-DQ4. Write control circuit 10' determines whether a WB signal exists or not in response to an internal RAS signal. When determining that WB signal exists, the circuit inhibits write of only a designated bit, out of 4-bit data, in response to a bit designating signal applied to data input/output terminals DQ1-DQ4.

FIG. 8 is a timing chart of a writing operation of the DRAM device of FIG. 7. With reference to FIG. 8 and FIG. 2, the timing chart of FIG. 8 differs from the timing chart of the reading operation shown in FIG. 2 in that a write control signal WE is activated at a fall of a CAS signal, thereby designating a write mode.

A writing operation is described in the following. That is, an operation mode designating signal WB is strobed at a fall of RAS signal. When operation mode designating signal WB is at a low level, write control circuit 10' determines that an operation mode is designated. When a bit designating signal applied to data input/output terminals DQ1-DQ4 at that time is at a low level, the circuit inhibits write of input data applied subsequently to the bit designating signal. When the bit designating signal is at a high level, the circuit allows write of input data applied subsequently to the bit designating signal.

FIG. 9 is a block diagram of the write control circuit and the input buffer of FIG. 7. With reference to FIG. 9, write control circuit 10' includes a mask enable signal generation circuit 10a, mask registers 10b1-10b4 and OR gates 10c1-10c4, similarly to read control circuit 9. Input buffer 8 includes data output buffers 81-84. Mask enable signal generation circuit 10a strobes a WB signal at a fall of a RAS signal and generates a mask enable signal when WB signal is at a low level. Each of mask registers 10b1-10b4 temporarily holds a bit designating signal applied to the corresponding data input/output terminal DQj in response to the mask enable signal. Each of OR gates 10c1-10c4 generates a signal WCj for controlling write of each bit in response to internal write enable signal WE and a bit designating signal held by the corresponding mask register 7ba. When write control signal WCj is at a low level, write to the bit is allowed, while when WCj is at a high level, write to the bit is inhibited.

FIG. 10 is a block diagram showing an image data generation device using the DRAM device shown in FIG. 7. With reference to FIG. 10, the image data generation device differs from that of FIG. 5 in that DRAM devices M1', M2' and M3' are used which allow inhibition of read of/write to a desired bit. The other circuits are similarly structured as those of FIG. 5.

FIG. 11 is a timing chart illustrating a writing operation of the image data generation device of FIG. 10. The timing chart differs from that of FIG. 6 in that OE1, OE2 and OE3 signals are brought to a high level and they are activated after the rises of write enable signals WE1-WE3 signals and CAS signal.

As a result, each memory device is allowed to assume a write state. Each of memory devices M1'-M3' allows data of a desired number of bits to be written in response to operation mode designating signals WB1-WB3 and a bit designating signal. The image data generation device shown in FIG. 12 therefore enables a desired number of bits to be read and to be written.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.