Block Substitution Method in a Cache Memory of a Multiprocessor System

1. Field of the Invention

The present invention relates to a block substitution method of a cache memory in a multiprocessor system including a plurality of processors having cache memories.

2. Related Background Art

In a prior art, when a block-to be substituted in a block substitution of a cache memory (hereinafter referred to as a cache) is to be selected, a block which has a lowest possibility of being referred to in a subsequent program execution is selected in view of the localization of reference which is a common characteristic in the program execution. Specifically, an LRU (least recently used) system in which a block among candidate blocks for substitution which has not been referred to for a longest period is selected, or a FIFO (first-in first-out) system in which a block which has been stored at an oldest time is used.

In addition to the selection system (FIFO, LRU, etc. ) for the block to be selected in the block substitution, a copy back system in which only data in the cache is updated when a CPU write instruction is issued and a main memory is not updated until updating is needed, that is, until a block which contains the data in the cache is selected for the substitution is used rather than a write through system in which the data in the cache and the data in the main memory are simultaneously updated when the CPU write instruction is issued because it is a sole purpose of the cache to promptly execute a service to a main memory access request of the CPU in a single processor system.

It may be said that the cache has been developed and progressed in the single processor system.

However, since the prior art system is a control system based on the localization of reference, the following problem arises in a multiprocessor system (hereinafter referred to as a system) in which a plurality of processors operate in parallel, for example, a plurality of processors and main memories are coupled through a single bus and a cache is provided in each of the processors.

Data integrity among the caches of the respective processors and between the caches and the main memories must be taken into consideration. When the system uses the copy back system to update the main memory when the CPU write instruction is issued, there occurs inconsistency of data content between the cache and the main memory because the written data is not instantly reflected to the main memory. A block which contains such data is called a dirty block. The write back of the dirty block to the main memory (to restore the data integrity between the main memory and the cache) is effected at the following two timings.

(1) When a cache miss to the block in another processor takes place.

(2) When the block is selected as a block to be substituted in the block substitution system.

In those cases, a bus access is required for the write-back to the main memory. The write-back (1) is an effective bus access in that the data is used in the processor which has caused the cache miss, but the write-back (2) is not an effective bus access in the sense of the effective utilization of data.

Further, in a combination of (1) and (2), that is, when a cache miss to a dirty block takes place in a processor immediately after the block has been written back to the main memory by another processor in accordance with a predetermined block substitution system, the bus access takes places twice to the same block at substantially the same time. One of the bus accesses could be avoided if the write-back of the dirty block to the main memory would be delayed for a while. If such a condition frequently occurs, the frequency of bus access increases and a chance of waiting for the bus access rises and a system performance is lowered.

It is an object of the present invention to provide a method for efficiently selecting a block to be substituted in the block substitution of a cache memory in a multiprocessor system.

It is another object of the present invention to provide a method for selecting a block to be substituted in a cache memory, which attains data integrity with a main memory.

It is another object of the present invention to provide a method for selecting a block to be substituted of a cache memory which has a low bus access frequency in order to improve an overall system performance.

According to one aspect, the present invention which achieves these objects relates to a block substitution method of a cache memory comprising the steps of storing data integrity information with a main memory for each block of the cache memory, calculating a non-reference period of each block, selecting a block to be substituted based on the data integrity information of the block and the non-reference period, and loading new information to the selected block.

Other objectives and advantages besides those discussed above shall be apparent to those skilled in the art from the .description of a preferred embodiment of the invention which follows. In the description, reference is made to accompanying drawings, which form a part hereof, and which illustrate an example of the invention. Such example, however, is not exhaustive of the various embodiments of the invention, and therefore reference is made to the claims which follows the description for determinating the scope of the invention.

FIG. 1 shows a configuration of a cache memory in one embodiment,

FIG. 2 shows a configuration of a substitution block selection circuit,

FIGS. 3 (3a-3b) shows a flow chart of a process for selecting a block to be substituted, and

FIG. 4 shows a block diagram of a multiprocessor system in an embodiment.

One embodiment of the present invention is now explained with reference to the drawings.

FIG. 4 shows a configuration of a multiprocessor system in the present embodiment.

Numerals 41, 42, . . . 4n denote processor elements (PE). The PE 41 includes a processor 411 which executes various processings and a cache memory 412 for the processor 411.

The processor 411 accesses to a main memory 40 to copy a portion of information in the main memory 40 to the cache memory 412 for utilization and to update the content as required.

Other PE's are configured and operate in the same manner.

FIG. 1 shows a partial configuration of a 4-way set associative cache memory (hereinafter referred to as a cache) which is a representative embodiment of the present invention. In FIG. 1, numeral 1 denotes a tag array which stores attribute information of a block stored in the cache, numeral 2 denotes a validity bit (V-bit) which indicates whether a valid block is stored in a cache line or not, numeral 3 denotes an address tag which is used in the comparison of address when the cache is accessed, numeral 4 denotes a time stamp which indicate a time when a block stored in the cache line is accessed lastly, and numerals 5 and 6 denote bits which are used to maintain an integrity among the multi-caches and indicate status of the block stored in the cache line. The bit 5 is a dirty bit (D-bit) which indicates whether the integrity between the block and a corresponding block in the main memory is maintained or not, and the bit 6 is a shared bit (S-bit) which indicates whether the same block may have been stored in the cache of another processor or not, Numeral 7 denotes a logic circuit which determines a cache line in which a new block is to be stored when it is loaded in the cache. If a valid block is in the cache line, the V-bit is "1", and if the valid block is not in the cache line, the V-bit is off. If there is integrity between the block of the cache and the corresponding block in the main memory, the D-bit is "0", and if there is no integrity, the D-bit is "1".

FIG. 2 shows a block diagram of a configuration of a substitution block selection circuit 7. Numeral 8 denotes a way number and way time difference output circuit which receives a time stamp from each way and outputs way members LRUWi (i=0.about.3) in the order of LRU (that is, in a descending order of non-reference period) and differences of time stamps between LRUWo and LRUWi+1 (i=0.about.2) (dif0-1, dif0-2 and dif0-3), and numeral 9 denotes a substitution way selection circuit which receives the output of the circuit 8 and the D-bits of the respective ways to select the way to be substituted.

A method for selecting the way to be substituted is now explained with reference to a flow chart shown in FIG. 3.

In a step S10, when a cache miss in any processor of the system is detected, the V-bits, the time stamps and the D-bits of all lines of the corresponding set are read from the tag array 1 to the substitution block selection logic circuit 7 in a step S15. In a step S20, the substitution block selection logic circuit 7 examines the presence or absence of an invalid block. In the present embodiment, the V-bits are checked in the order of the way 0, way 1, way 2 and way 3 (steps S25.about.S40), and if invalid way which has "0" in the V-bit is detected, a new block is loaded to that way (steps S45.about.S60).

If all ways store valid blocks, the process proceeds to a step S65 to activate the way number and way time difference output circuit 8. In a step S70, the way member and way time difference output circuit 8 outputs way numbers (LRUW0.about.3) and way time differences (dif0-1, dif0-2 and dif0-3 ). In a step S75, the substitution way selection circuit 9 is activated to read in the way numbers (LRUW0.about.3), the way time differences (dif0-1, dif0-2 and dif0-3) and the D-bits of the ways.

The substitution way selection circuit 9 then selects the block to be substituted in the following manner.

In a step S80, it checks .whether the D-bit of LRUW0 is "1" or not. If it is "0", that is when there is no need of write-back of data to the main memory because of the data integrity between the cache and the main memory if the way is selected as the block to be substituted, the process proceeds to a step S115 to select the way as the block to be substituted. On the other hand, when the D-bit is "1", that is, when there is need to write back the data to be main memory due to the inconsistency of data between the cache and the main memory if the way is selected as the block to be substituted, the process proceeds to a step S85 to check LRUW1. If the D-bit of LRUW1 is "0", the process further proceeds to a step S90 to examine dif0-1. If dif0-1 is smaller than a prodetermined value, that is, if there is no such difference between LRU0 and LRU1, the process proceeds to a step S120 to select LRUW1 as the block to be substituted. On the other hand, if dif0-1 is larger than the predetermined value, that is, if there is a substantial time difference between LRU0 and LRU1, the process proceeds to a step S115 to select LRUW0 as the block to be substituted.

In a similar manner, when the D-bit of LRUW1 is "1", the D -bit o f LRUW2 i s "1", or the D-bit of LRUW3 is "1", steps S95.about.S110 are executed, one of steps S115.about.S130 is selected and one way of LRUW0.about.LRUW3 is selected as the block to be substituted. Finally, the block to be substituted is loaded in steps S135.about.S150 in accordance with the steps S115.about.S130.

In accordance with the present embodiment, the block having the longest non-reference period for data is not automatically selected as the block to be substituted but any block having substantially equal non-reference period for data and the data integrity between the cache and the main memory (which has no need for writing back the data) is selected as the block to be substituted. If there is no block having the data integrity between the cache and the main memory among the blocks having no such difference between the non-reference periods thereof and the longest non-difference period, the block having the longest non-reference period for data is selected as the block to be substituted.

In accordance with the present invention, the block to be substituted is selected not only by the data non-reference period but also with consideration of the data integrity between the cache and the main memory so that the frequency of access between the main memory and the processor is reduced. Accordingly, the overall system performance of the multiprocessor system is enhanced.