Fast and Efficient Circuit for Identifying Errors Introduced in Reed-Solomon Codewords

This invention relates to information storage and retrieval or transmission systems, and more particularly to means for encoding and decoding codewords for use in error detection, identification and correction in such information systems.

Digital information storage devices, such as magnetic disk, magnetic tape or optical disk, store information in the form of binary bits. Also, information transmitted between two digital devices, such as computers, is transmitted in the form of binary bits. During transfer of data between devices, or during transfer between the storage media and the control portions of a device, errors are sometimes introduced so that the information received is a corrupted version of the information sent. Errors can also be introduced by defects in a magnetic or optical storage medium. These errors must almost always be corrected if the storage or transmission device is to be useful.

Correction of the received information is accomplished by (1) deriving additional bits, called redundancy, by processing the original information mathematically; (2) appending the redundancy to the original information during the storage or transmission process; and (3) processing the received information and redundancy mathematically to detect, identify and correct erroneous bits at the time the information is retrieved. The process of deriving the redundancy is called encoding. The process of processing the received information and redundancy is called decoding. One class of codes often used in these processes is Reed-Solomon codes.

Encoding of information is accomplished by processing a sequence of information bits, called an information polynomial or information word, to devise a sequence of redundancy bits, called a redundancy polynomial or word, in accord with an encoding rule such as Reed-Solomon codes. An encoder processes the information polynomial with the encoding rule to create the redundancy polynomial and then appends it to the information polynomial to form a codeword polynomial which is transmitted over the signal channel or stored in an information storage device. When a codeword polynomial is received from the signal channel or read from the storage device, a decoder processes the received codeword polynomial to detect the presence of error(s), to attempt to identify any error(s) present and to flag the information polynomial as erroneous or to correct it before transferring the information polynomial for further processing.

The decoding process typically comprises three steps: (1) computing frequency-domain syndromes from the received codeword; (2) computing an error locator polynomial, whose roots indicate the locations of erroneous symbols, from the frequency-domain syndromes; and (3) finding the roots of the error locator polynomial and computing the corresponding error values.

The length n of codewords of Reed-Solomon codes utilizing b-bit symbols is restricted to n<2.sup.b. A symbol size commonly used is the "byte" comprising eight bits, giving n<2.sup.8 =256. When it is desired to store in and retrieve from a data storage system, or send and receive over a signal channel, a group of more than 255 bytes together, more than one codeword is required. When errors tend to occur in bursts affecting more than one symbol, it is advantageous to interleave the codewords so that a single error burst is spread across more than one codeword.

Optical disks conforming to ANSI/ISO standards for 90 mm and 130 mm media store data in a sector comprising an identifying mark; a triply-redundant header containing physical location information; 512 or 1024 user-data bytes plus vendor-unique/pointer bytes, all protected by an overlay CRC code with four redundant bytes, in five or ten interleaved ECC codewords, respectively, each with sixteen redundant bytes; and other necessary special marks. See 90 mm Rewritable/Read Only Optical Disk Cartridges for Information Interchange, Second Edition, Second Draft, JTC 1/SC 23/WG 2 N213, December 1990, pages 38-42 and 84-86. Also see Information Technology--130 MM Rewritable Optical Disk Cartridges for Information Exchange, ISO/IEC JTC 1/SC 23N, pages 53-57. FIG. 1 shows the organization of a 512-user-date-byte sector for the ANSI 90 mm rewritable optical disk standard. FIG. 2 shows the interleaved codeword organization of the data area within each 512-data byte sector for the ANSI 90 mm CCS rewritable optical disk standard. The "SB" and "RS" bytes are not included in ECC/CRC computations.

A Reed-Solomon code with distance d over b-bit symbols from GF(2.sup.b) has code generator polynomial G(x) of degree d-1: ##EQU1## where m is the offset of the code generator polynomial. .sym. represents finite-field addition and the product is formed using finite-field multiplication. The time-domain remainder polynomial R(x) has coefficients R.sub.j for j from 0 to d-2 defined by ##EQU2## where C'(x) is the received codeword polynomial and the summation is performed using finite-field addition. Frequency-domain syndromes S.sub.m+i for i from 0 to d-2 are related to coefficients R.sub.j according to: ##EQU3##

Rearranging equation (3) yields: ##EQU4##

Methods for performing the computations of equation (4) when m is zero are known in the art; see Lim, "A Decoding Procedure for the Reed-Solomon Codes, "NASA Technical Paper 1286, 1978 pp. 12-15. FIG. 3 depicts prior-art circuitry implementing equation (4), comprising d-1 registers 113 denoted D(0) through D(d-2); d-1 constant finite-field multipliers 110 implementing multiplication by .alpha..sup.j for j from 0 to d-2; d-1 three-input multiplexers 111; and a (d-1)-input EXCLUSIVE-OR circuit 112. All registers, multiplexers, multipliers and data paths are symbol wide.

In the operation of FIG. 3, first the following process is repeated d-1 times for j from 0 to d-2: present coefficient R.sub.j and assert control signal LD.sub.-- D(j) to store R.sub.j in D(j). Then control signal EN is asserted and the following process is repeated d-1 times for i from 0 to d-2: syndrome S.sub.i is produced on OUT and stored elsewhere and the outputs of multipliers .alpha..sup.j 110 are stored in respective registers D(j) 113 for j from 0 to d-2.

The circuit of FIG. 3 is undesirable because it requires an excessive number of registers and constant finite-field multipliers and a very large EXCLUSIVE-OR circuit. Thus it is clear that improved methods for computing frequency-domain syndromes are needed.

Iterative algorithms for generating the error locator polynomial for Reed-Solomon and related codes are known in the art; see Clark and Cain, Error Correction Coding for Digital Communications, 1981, pp. 204-208. Iterative algorithms which require no inversion are also known in the art; see Burton, "Inversionless Decoding of Binary BCH Codes," IEEE Transactions on Information Theory, IT-17, 1971, pp. 464-466. FIG. 4 shows the steps of a prior-art inversionless iterative algorithm. In step 1, counters n, k and L, parameter d.sub.k and polynomials .sigma..sup.(n) and .sigma..sup.(k) are initialized. In step 2, the nth discrepancy d.sub.n is calculated. If d.sub.n is zero, control passes to step 6. Otherwise, step 3 calculates the updated error locator polynomial .sigma..sup.(p). Then if counter L is greater than or equal to the difference n-k, control is passed to step 5. Otherwise step 4 updates counters k and L, copies d.sub.n to d.sub.k and copies .sigma..sup.(n) to .sigma..sup.(k). Step 4 copies .sigma..sup.(p) to .sigma..sup.(n). Step 6 multiplies .sigma..sup.(k) by x and increments counter n. Then if counter n is less than 2.multidot.t, control is passed to step 2. Otherwise, the iterative algorithm has been completed and .sigma..sup.(n) is the desired error locator polynomial. The prior-art iterative algorithm of FIG. 4 is undesirable because it requires storage elements for three polynomials and repeated copying of polynomial coefficients from one storage area to another.

Hardware capable of performing the computations required for decoding Reed-Solomon and related codes are known in the art; see Glover and Dudley, Practical Error Correction Design for Engineers, 1988, page 353. FIG. 5 shows the major blocks of a prior-art decoding circuit comprising syndrome generator 180; syndrome buffer 181; work buffer 182; sequencer 183; registers 195 A, B, C, D, E, F, G and H; read-only-memory tables 184; EXCLUSIVE-OR circuit 185; zero-detection circuits 186 and 187; finite-field logarithm read-only-memories 188 and 189; NOR circuit 190; ones-complementing circuit 191; modulo-255 adder 192; finite-field antilogarithm table 193; and gating circuit 194. Unless otherwise noted, all paths are eight bits wide.

In operation of FIG. 5, syndrome generator 180 generates frequency-domain syndromes for all interleaved codewords simultaneously and stores them in syndrome buffer 181. Sequencer 183 controls the operation of the decoder, using work buffer 182 to store intermediate results produced using the other circuitry. Finite-field sums are produced using EXCLUSIVE-OR circuit 185. Finite-field variable products are produced using logarithm tables 188 and 189, adder 192, antilogarithm table 192, zero-detection circuits 186 and 187, NOR circuit 190 and gating circuit 194. Finite-field inversion is performed using read-only memory tables 184.

The circuitry of FIG. 5 is undesirable because it requires an excessive amount of complex and relatively slow circuitry. Syndrome generator 180 contains separate syndrome computation circuits for each interleaved codeword. The finite-field computation circuit contains a large number of registers. The read-only-memory circuits of 184, 188, 189 and 192 are both complex and slow, limiting the maximum rate of operation. It is clear that less expensive, faster circuitry is needed.

The ANSI/ISO standards for 90 mm and 130 mm optical disk media provide for a CRC code covering all interleaves of the user data and the vendor-unique/pointer information bytes. This distance-five, Reed-Solomon code has information symbols comprising the EXCLUSIVE-OR sum of bytes across interleaves. The CRC code generator polynomial GC(x) is of degree four: ##EQU5## where dc is the degree and c is the offset of the CRC code generator polynomial. The time-domain CRC residue polynomial RC(x) has coefficients RC.sub.j defined by ##EQU6## where CC'(x) is the received CRC codeword polynomial. The residue of this code must be adjusted to remove the contribution of each identified error. After all errors have been identified, the adjusted CRC residue must be zero; if not, a miscorrection of an uncorrectable error by the error correction code has been detected.

One method for adjusting the CRC residue is to re-encode the sector after the error detection, identification and correction process has been completed and check that the re-encoded CRC redundancy symbols match the corrected CRC redundancy symbols. This method is undesirable because it requires additional hardware to provide access to the corrected data and additional time to perform the re-encoding process.

Another method for adjusting the CRC residue is to compute CRC syndromes SC.sub.c+i from CRC residue coefficients RC.sub.j according to: ##EQU7## and then adjust the CRC syndromes according to: ##EQU8## where N is the total number of errors in symbols covered by the CRC code, E.sub.j are the error values and L.sub.j are the locations of the errors relative to the CRC code. This method is undesirable because it requires additional time to compute the CRC syndromes and to perform the adjustment. It is clear that faster and less expensive methods for adjusting the CRC residue are needed.

Apparatus and methods are disclosed for providing an improved system for identifying the location and value of errors introduced in binary data encoded using Reed-Solomon and related codes and to detect miscorrections of such codes with an auxiliary code. The invention employs an architecture based on a microcode engine that is specialized for error identification and that supports interleaved codewords. This architecture can be efficiently fabricated as an integrated circuit, yet is capable of identifying multiple introduced errors "on the fly" i.e. with performance sufficient to not significantly slow the process of reading from data storage or transmission subsystems such as, but not limited to, optical disks. In the preferred embodiment, a new two-step method of error syndrome computation is employed to reduce circuit cost and complexity. An improved iterative algorithm is provided which reduces circuit cost and complexity and decreases the time required to generate the error locator polynomial. Cyclic redundancy check (CRC) information is adjusted as introduced errors are identified during the Chien search, thus reducing the time required to protect against ECC miscorrection. Externally-specified error thresholds allow detection of excessive numbers of errors.

In accordance with the foregoing, an object of the present invention is, in the typical case, to identify a plurality of errors introduced within a particular sector during the time period in which the next adjacent sector is being read or received from the storage or transmission medium. In the atypical case where the time required to identify the number of introduced errors exceeds the time required to read the next adjacent sector, or where the number of introduced errors exceeds either an externally specified threshold or the correction power of the specific Reed-Solomon code used, the present invention detects this case, signals an external microcontroller and signals the ENDEC section of the CL-SM330 to cease reading the medium.

Another object of the present invention is to reduce the implementation cost and complexity of error identification circuitry by performing error syndrome computation in two steps, where each step processes half of the required bits through a finite-field computation circuit of approximately half the size required by the prior-art one-step method.

Another object of the present invention is to provide an enhancement of the prior-art iterative algorithm to allow computing the coefficients of the error locator polynomial in a manner that is quicker and requires less circuitry than prior-art implementations by using two polynomials and by interchanging the values of two pointers to two tables containing the coefficients of these polynomials and interchanging their associated parameters.

Another object of the present invention is to reduce the time required by the error identification computation by performing, during the Chien search for introduced errors, the required adjustment of the CRC information whenever an error is identified. Data paths and computation circuits are provided specifically to support this objective.

Another object is to provide an architecture particularly suitable for error identification computations which includes both a specialized data-path design and a set of specialized microengine instructions and which is suitable for implementation in an integrated circuit.

Another object is to provide elements of the set of microengine instructions which efficiently control the execution of finite-field variable multiply-and-sum operations.

Another object of the present invention is to accept time-domain error syndromes so as to support a high performance, cost-efficient implementation for Reed-Solomon codes that allows the same LFSR to be used for both encoding and decoding of Reed-Solomon codewords.

Another object is to support the ANSI/ISO standard formats for both 512-byte and 1024-byte sector sizes and both 90 mm and 130 mm optical-disk medium sizes.

Another object is to allow the code symbols of the information polynomial to be interleaved, as is known in the art, among a plurality of codeword polynomials, each containing its own independent redundancy polynomial while using the same error identification circuitry for each interleave.

Another object is to allow the EXCLUSIVE-OR sum across interleaves of the code symbols of the information polynomial to form the information symbols of a codeword of an overlay CRC code.

Another object is to adjust this CRC information as errors are detected during the Chien search, thus reducing the time required to protect against ECC miscorrrection.

Another object is to detect when the number of errors identified within a sector exceeds externally specified thresholds.

These and other objects of the invention will become apparent from the detailed disclosures following herein.

FIG. 1 illustrates the ANSI standard layout of a sector containing 512 user data bytes on 90 mm Continuous Composite Servo (CCS) optical-disk media.

FIG. 2 illustrates the ANSI standard layout of the data area within a sector containing 512 user data bytes on 90 mm CCS optical-disk media.

FIG. 3 is a logic diagram of a prior-art syndrome computation circuit that outputs one syndrome per clock cycle.

FIG. 4 is a flow chart of a prior-art iterative algorithm for computing the coefficients of the error locator polynomial.

FIG. 5 is a block diagram of a prior-art circuit for performing finite-field computations.

FIG. 6 is a block diagram of an optical-disk data-storage system containing the present invention.

FIG. 7 is a block diagram of the CL-SM330 portion of the optical-disk data-storage system.

FIG. 8 is a block diagram of the CL-SM331 portion of the optical-disk data-storage system.

FIG. 9 is a logic diagram of a new two-step syndrome computation circuit.

FIG. 10 is a logic diagram of a two-step syndrome computation circuit equivalent to that of FIG. 9 except for the constant finite-field multipliers implemented.

FIG. 11 is a logic diagram of circuit which can be shared for two-step syndrome computation and for finding the roots of the error locator polynomial.

FIG. 12 is a logic diagram of another circuit which can be shared for two-step syndrome computation and for finding the roots of the error locator polynomial.

FIG. 13 is a flow chart of a new iterative algorithm for computing the coefficients of the error locator polynomial.

FIG. 14 is a high-level block diagram of the CL-SM330's ECC/CRC block containing the error identification circuit of the present invention and showing its interfaces with the other blocks of the CL-SM330.

FIG. 15 is a register address and bit assignment map of the interface between the error identifier circuit and the external microcontroller.

FIG, 16 is block diagram of the error identification circuit of the present invention showing its major functional blocks.

FIG. 17 is a block diagram of the Address Pointer Circuit (APC) block of the present invention.

FIG. 18 is a block diagram of the CRC Residue Adjuster (CRA) block of the present invention.

FIG. 19 is a block diagram of the Error Vector Control (EVC) block of the present invention.

FIG. 20 is a block diagram of the Frequency Domain Circuit (FDC) block of the present invention.

FIG. 21 is a block diagram of the Finite Field Processor (FFP) block of the present invention.

FIG. 22 is a logic diagram of the finite-field Variable Multiply-and-Sum (VMS) circuit of the present invention.

FIG. 23 is a block diagram of the Instruction Processing Circuit (IPC) block of the present invention.

FIG. 24 is a block diagram of the Interleave & Sector Counters (ISC) block the present invention.

FIG. 25 is a flow chart of the overall read sector operation.

FIG. 26 is a flow chart of the identify errors operation.

FIG. 27 is a flow chart of the initialize RAM and CRA operation.

FIG. 28 is a flow chart of the compute frequency-domain syndromes operation.

FIG. 29 is a flow chart of the compute error locator polynomial coefficients operation.

FIG. 30 is a flow chart of the find errors and adjust CRC residue operation.

FIG. 6 is a block diagram of an optical disk system for data storage that embodies the present invention within the CL-SM330 integrated circuit. The CL-SM330 and CL-SM331 are a set of two high-integration, integrated circuits for optical disk controllers for embedded controller applications. They fully support the ANSI/ISO industry standard optical disk formats using the CCS (Continuous Composite Servo) standard for both 90 mm (3.5") and 130 mm (5.25") optical disk drives. The rewritable, partial ROM and WORM (Write Once Read Many) standards are supported. The high integration and optimized pin-out of the CL-SM330/331 make them suitable for embedded controller applications, particularly for 90 mm drives where only limited board space is available. The CL-SM330 Optical Disk ENDEC/ECC implements the encoder/decoder/formatter and the error detection, identification and correction logic required by the CCS standard. The CL-SM331 SCSI Optical Disk Controller implements a Small Computer System Interface (SCSI), Buffer Manager and Sector formatter. The CL-SM330 and CL-SM331, along with buffer memory, a data separator and a local microcontroller with system Read-Only-Memory and Random-Access-Memory, complete a high-performance, low-cost optical disk controller subsystem.

A local microcontroller provides both the CL-SM330 and the CL-SM331 with initial operating parameters, such as disk sector format, type and size of buffer memory and SCSI host controller. During data transfer operations, the CL-SM330/331 require only minimal intervention from the local microcontroller. Features such as auto-incrementing ID registers and fully-automated error correction (in typical cases) minimize the microcontroller's real-time interaction with disk activity.

FIG. 7 is a block diagram of the CL-SM330 integrated circuit showing its interfaces to the CL-SM331, the microcontroller, and the optical drive, as well as its ENDEC and ECC/CRC circuits. The present invention is part of the ECC/CRC block shown. The microcontroller-to-CL-SM330 communication path is a multiplexed address and data path similar to that provided by Intel 80188 and Motorola 68HC11 classes of microcontrollers. A configuration pin is available to allow selection of the microcontroller-bus control-signal method of either class. Virtually all controller functions are programmable by the microcontroller via read/write registers. This provides substantial firmware control over drive operation to allow for various retry methods and other unique requirements. The CL-SM330 has centralized status registers with interrupt capability. These features allow firmware designers flexibility in writing polled loops or interrupt handlers to provide real-time process control critical in embedded controller drive applications.

The data interface between the CL-SM330 and CL-SM331 is a serial NRZ interface. NRZ data is transmitted between the two devices with the Read-Reference Clock (RRCLK). Disk interface control signals, such as "Sector Mark Found" "ID Found" etc., are used for synchronization of the data transfer between the CL-SM330 and CL-SM331. A dedicated serial Error Vector Interface transfers error correction vectors with the System Clock (SYSCLK) to the CL-SM331 for actual correction of erroneous bytes in the buffer. To protect against errors in the information transmission between the two devices, eight-bit checksums cover all information transferred over the NRZ Interface and the Error Vector Interface. An Interrupt line allows optional connection of the CL-SM331 and CL-SM330 interrupt mechanisms, resulting in a single interrupt line to be handled by the local microcontroller.

The CL-SM330 supports standard 512-user-data-byte sectors with five ECC interleaves or 1024-user-data-byte sectors with ten ECC interleaves. Correction of erroneous data in the buffer is performed by the CL-SM330/331 controller independent of the microcontroller. All but worst-case errors are corrected "on-the-fly", without loss of disk revolutions. "On-the-fly" operation is achieved by identifying the introduced errors using the present invention and generating error correction vectors for each sector while the next adjacent sector is being read by the controller. Error correction vectors are transmitted to the CL-SM331 through the dedicated serial Error Vector Interface. An independent Corrector Clock input (CORRCLK) is provided for the ECC/CRC block to allow optimum error identifier performance, independent of the System Clock frequency. Overlay CRC verification is performed in hardware during the error identification process, resulting in very low miscorrection probability without significant performance penalty.

The CL-SM330 ENDEC section includes the RLL (2,7) encoder/decoder and circuitry for the generation and detection of the special marks required by the optical disk format. Full ANSI/ISO format support provides for programmable Sector Mark, ID Field, Data Sync Mark and Resync Mark thresholds, as well as automatic hardware PLL synchronization and re-synchronization capability, compensation for Sector Mark asymmetry, Flag generation and written Flag detection. Output signals are provided to indicate the position of the Pre-Formatted data area, the Track Offset Flag area and the Automatic Laser Power Control area.

The data connection from the CL-SM330 to the optical drive is a serial RLL (2,7) encoded interface. Output signals are also provided for data synchronizer (PLL) control; during either normal phase lock or, if phase lock is lost while reading, these signals can be used to control the synchronization or resynchronization of the phase-locked loop to the incoming data stream. A general-purpose eight-bit output port and a general-purpose eight-bit input port, as well as two general purpose interrupt inputs, are available on the CL-SM330 to allow customization of the drive interface and minimize external component requirements.

FIG. 8 is a block diagram of the CL-SM331 integrated circuit including its interfaces with the SCSI bus and the microcontroller, Buffer Manager and Differential Control circuits, as well as its Format Sequencer and associated Writable Control Store (WCS) and Sector Formatter Data Path. The CL-SM331 Microcontroller Interface is similar to that of the CL-SM330 Microcontroller Interface, with the addition of a Ready signal which enables the CL-SM331 to force wait states on the microcontroller address/data bus.

The CL-SM331 SCSI is designed for compliance with the SCSI-II specification; see Small Computer Standard Interface-2 Draft Proposed American National Standard, XT9.2/86-109 Rev. 10c, X3.131-199x, Mar. 9, 1990. The SCSI logic includes integrated 48 mA drivers for the single-ended option as well as signals for control of the external logic necessary to implement the differential transceiver option. Both the asynchronous and synchronous transfer protocols are supported in either Initiator or Target mode. Routine bus control operations such as arbitration, selection and reselection are automatically sequenced in hardware. This method of implementing the SCSI Interface makes the SCSI protocol firmware extremely flexible and very efficient.

The CL-SM331 Buffer Manager controls the flow of data between the SCSI and disk interface. These interfaces store and retrieve data from the buffer memory using interleaved access cycles. The actual buffer memory may be implemented with static or dynamic RAM devices. The CL-SM331 Buffer Manager is programmable to provide all of the necessary address and control signals for RAM devices of varying access times. Up to 256 KBytes of SRAM can be directly addressed by the CL-SM331. As much as 4 MBytes of DRAM is directly supported by the CL-SM331 with specific control for 64 Kbit, 256 Kbit, 1 Mbit and 4 Mbit devices. In DRAM mode, refresh cycles are generated automatically through a third channel to the buffer memory in addition to the concurrent disk and SCSI accesses. The CL-SM331 Buffer Manager accepts error correction vectors from the CL-SM330 chip and automatically corrects errors in the buffer RAM with no interruption of the current data transfer.

The CL-SM331 Format Sequencer, WCS and Sector Formatter Data Path blocks provide for interface between the CL-SM331 and CL-SM330, as described above. The Data Path logic performs the serial-to-parallel and parallel-to-serial conversion for NRZ data transfer between the buffer and the CL-SM330. The Format Sequencer controls the low-level sector format control, as defined by the pattern loaded in the WCS.

Define x as the largest integer not greater than x and define t= (d-1)/2 .

Equation (3) can be written as ##EQU9##

From equation (9) it is clear that the computation of frequency-domain syndromes S.sub.m+i can be performed in two steps wherein one step produces values A.sub.m+i, the other step produces values B.sub.m+i, and syndromes S.sub.m+i are formed as the EXCLUSIVE-OR sums of respective values A.sub.m+i and B.sub.m+i.

The circuitry of FIG. 9 implements equation (9) for codes with odd d; it comprises t registers 127 denoted D(0) through D(t-1); t constant finite-field multipliers 120 implementing multiplication by .alpha..sup.j for j from 0 to t-1; t three-input multiplexers 121; register 128 DM; a constant finite-field multiplier 122 implementing multiplication by .alpha..sup.m ; a t-input EXCLUSIVE-OR circuit 123; register 129 DT; a constant finite-field multiplier 126 implementing multiplication by .alpha..sup.t ; and two variable finite-field multipliers 124 and 125. Multipliers 124 and 125 may be implemented as one multiplier with appropriate multiplexing of inputs and output, which is preferred due to the circuitry cost of variable multiplexers. All registers, multiplexers, multipliers and data paths are symbol wide. Values A.sub.m+i are produced on OUT1 and values B.sub.m+i are produced on OUT2.

In the first step of operation of FIG. 9, DM is initialized to .alpha..sup.0, then the following process is repeated t times for j from 0 to t-1: present coefficient R.sub.j and assert control signal LD.sub.-- D(j) to store in D(j) the product of R.sub.j and the output of DM, and store the output of multiplier 122 in DM. Then control signal EN is asserted and the following process is repeated d-1 times for i from 0 to d-2: save elsewhere value A.sub.m+i on OUT1 and store the outputs of multipliers * .alpha..sup.j 120 in respective registers D(j) for j from 0 to t-1.

In the second step of operation of FIG. 9, DM is initialized to .alpha..sup.t.multidot.m and the following process is repeated t times for j from 0 to t-1: present coefficient R.sub.j+t and assert control signal LD.sub.-- D(j) to store in D(j) the product of R.sub.j+t and the output of DM, and store the output of multiplier 122 in DM. Then DT is initialized to .alpha..sup.0, control signal EN is asserted and the following process is repeated d-1 times for i from 0 to d-2: save as S.sub.m+i the EXCLUSIVE-OR sum of value B.sub.m+i on OUT2 and value A.sub.m+i from the first step, store the outputs of multipliers * .alpha..sup.j 120 in respective registers D(j) for j from 0 to t-1, and store the output of multiplier * .alpha..sup.t 126 in DT.

Using the circuit of FIG. 9, it is possible to reverse the order of the two steps, first processing R.sub.t through R.sub.d-2 and then processing R.sub.0 through R.sub.t-1. In the first step of operation, initialize DM to .alpha..sup.t.multidot.m load registers D(j) while presenting R.sub.t through R.sub.d-2, then initialize DT to .alpha..sup.0 and save elsewhere values B.sub.m+i from OUT2. In the second step of operation, initialize DM to .alpha..sup.0, load registers D(j) while presenting R.sub.0 through R.sub.t-1, then save as S.sub.m+i the EXCLUSIVE-OR sum of values A.sub.m+i from OUT1 and respective values B.sub.m+i from the first step.

With a slight modification to the circuit of FIG. 9, it is possible to reverse the order in which the remainder coefficients R.sub.j are processed within each step, in one step processing R.sub.d-2 through R.sub.t and in the other step processing R.sub.t-1 through R.sub.0. Replace multiplier 122 with a multiplier implementing multiplication by .alpha..sup.-m. In the first step of operation, initialize DM to .alpha..sup.(d-2).multidot.m, load registers D(j) while presenting R.sub.d-2 through R.sub.t, then initialize DT to .alpha..sup.0 and save elsewhere values B.sub.m+i from OUT2. Then in the second step of operation, initialize DM to .alpha..sup.(t-1).multidot.m, load registers D(j) while presenting R.sub.t-1 through R.sub.0, then save as syndromes S.sub.m+i the EXCLUSIVE-OR sums of values A.sub.m+i from OUT1 and respective values B.sub.m+i from the first step. Alternatively, in the first step of operation, initialize DM to .alpha..sup.(t-1).multidot.m and load registers D(j) while presenting R.sub.t-1 through R.sub.0, then initialize DT to .alpha..sup.0 and save elsewhere values B.sub.m+i from OUT2. Then in the second step of operation, initialize DM to .alpha..sup.(d-2).multidot.m, load registers D(j) while presenting R.sub.d-2 through R.sub.t, then save as syndromes S.sub.m+i the EXCLUSIVE-OR sums of values A.sub.m+i from OUT1 and respective values B.sub.m+i from the first step.

When d is even, the equation for values B.sub.m+i becomes ##EQU10## and the circuit of FIG. 9 is modified to include a register D(t) and another constant finite-field multiplier 120 implementing multiplication by .alpha..sup.t and another three-input multiplexer 121, all connected as for existing registers D(j), multipliers 120 and multiplexers 121. EXCLUSIVE-OR circuit 123 becomes a (t+1)-input EXCLUSIVE-OR circuit. Operation is modified to load register D(t) with zero before producing values A.sub.m+i and with R.sub.2.multidot.t before producing values B.sub.m+i. Remainder coefficients may be processed in reverse order by performing the same modification described above.

When d is even, it is possible to compute the syndromes in two steps wherein one step processes remainder coefficients R.sub.j for j from 0 to t and the other step processes coefficients R.sub.j for j from t+1 to d-2. To do so requires only replacing multiplier 126 with a multiplier implementing multiplication by .alpha..sup.t+1. D(t) is loaded with R.sub.t before producing values A.sub.m+i and with zero before producing values B.sub.m+i.

Equation (3) can also be written as ##EQU11##

From equation (10) it is clear that the computation of frequency-domain syndromes S.sub.m+i can be performed in two steps wherein one step produces values A.sub.m+i, the other step produces values B.sub.m+i, and syndromes S.sub.m+i are formed as the EXCLUSIVE-OR sums of respective values A.sub.m+i and B.sub.m+i.

The circuitry of FIG. 10 implements equation (10) for codes with odd d; it comprises t registers 137 denoted D(t) through D(2.multidot.t-1); t constant finite-field multipliers 130 implementing multiplication by .alpha..sup.j for j from t to 2.multidot.t-1; t three-input multiplexers 131; register 138 denoted DM; a constant finite-field multiplier 132 implementing multiplication by .alpha..sup.m ; a t-input EXCLUSIVE-OR circuit 133; register 139 denoted DT; a constant finite-field multiplier 136 implementing multiplication by .alpha..sup.-t ; and two variable finite-field multipliers 134 and 135. Multipliers 134 and 135 may best be implemented as one multiplier with appropriate multiplexing of inputs and output. Values A.sub.m+i are produced on OUT2 and values B.sub.m+i are produced on OUT1.

In the first step of the operation of FIG. 10, DM is initialized to .alpha..sup.0 and the following process is repeated t times for j from t to 2.multidot.t-1: present coefficient R.sub.j-t and assert control signal LD.sub.-- D(j) to store the product of R.sub.j-t and the output of DM in D(j), and store the output of multiplier * .alpha..sup.m 132 in DM. Then DT is initialized to .alpha..sup.0 control signal EN is asserted and the following process is repeated d-1 times for i from 0 to d-2: save elsewhere value A.sub.m+i from OUT2, store the outputs of multipliers * .alpha..sup.j 130 in respective registers D(j) for j from t to d-2, and store the output of multiplier * .alpha..sup.-t 136 in DT.

In the second step of operation of FIG. 10, DM is initialized to .alpha..sup.t.multidot.m and the following process is repeated t times for j from t to 2.multidot.t-1: present coefficient R.sub.j and assert control signal LD.sub.-- D(j) to store the product of R.sub.j and the output of DM in D(j), and store the output of multiplier 132 .alpha..sup.m in DM. Then control signal EN is asserted and the following process is repeated d-1 times for i from 0 to d-2: save as S.sub.m+1 the EXCLUSIVE-OR sum of value B.sub.m+i from OUT2 and value A.sub.m+i from the first step and store the outputs of multipliers .alpha..sup.j 130 in respective registers D(j) for j from t to d-2.

Using the circuit of FIG. 10, it is possible to reverse the order of the two steps, first processing R.sub.t through R.sub.d-2 and then processing R.sub.0 through R.sub.t-1. In the first step of operation, initialize DM to .alpha..sup.t.multidot.m, load registers D(j) while presenting R.sub.t through R.sub.d-2, then save elsewhere values B.sub.m+i from OUT1. In the second step of operation, initialize DM to .alpha..sup.0 load registers D(j) while presenting R.sub.0 through R.sub.t-1, then initialize DT to .alpha..sup.0 and save as S.sub.m+i the EXCLUSIVE-OR sum of values A.sub.m+i from OUT2 and respective values B.sub.m+i from the first step.

With a slight modification to the circuit of FIG. 10, it is possible to reverse the order in which the remainder coefficients R.sub.j are processed within each step, in one step processing R.sub.d-2 through R.sub.t and in the other step processing R.sub.t-1 through R.sub.0. Replace multiplier 132 with a multiplier implementing multiplication by .alpha..sup.-m. In the first step of operation, initialize DM to .alpha..sup.(d-2).multidot.m, load registers D(j) while presenting R.sub.d-2 through R.sub.t, then save elsewhere values B.sub.m+i from OUT1. In the second step of operation, initialize DM to .alpha..sup.(t-1).multidot.m load registers D(j) while presenting R.sub.t-1 through R.sub.0, then initialize DT to .alpha..sup.0 and save as syndromes S.sub.m+i the EXCLUSIVE-OR sums values A.sub.m+i from OUT2 and respective values B.sub.m+i from the first step. Alternatively, in the first step of operation, initialize DM to .alpha..sup.t.multidot.m, load registers D(j) while presenting R.sub.t-1 through R.sub. 0, then initialize DT to .alpha..sup.0 and save elsewhere values A.sub.m+i from OUT2. In the second step of operation, initialize DM to .alpha..sup.(d-2).multidot.m load registers D(j) while presenting R.sub.d-2 through R.sub.t, then save as syndromes S.sub.m+i the EXCLUSIVE-OR sums of values B.sub.m+i from OUT1 and respective values A.sub.m+i from the first step.

When d is even, the equation for values B.sub.m+i becomes ##EQU12## and the circuit of FIG. 12 is used. Operation is similar to that for FIG. 10 except that register D(2.multidot.t) is loaded with zero before producing values A.sub.m+i and with R.sub.2.multidot.t before producing values B.sub.m+i. Remainder coefficients may be processed in reverse order by modifying FIG. 12 in a fashion similar to that described for FIG. 10.

When d is even, it is possible to modify the circuit of FIG. 12 to compute the syndromes in two steps wherein one step processes remainder coefficients R.sub.j for j from 0 to t and the other step processes coefficients R.sub.j for j from t+1 to d-2. To do so requires only replacing multiplier 156 with a multiplier implementing multiplication by .alpha..sup.t+1. D(2.multidot.t) is loaded with R.sub.t before producing values A.sub.m+i and with zero before producing values B.sub.m+i.

In the preferred embodiment of the invention, the CL-SM330's Encode/Decode LFSR block presents interleaved remainder coefficients R.sub.j sequentially from R.sub.d-2 of the first interleaved codeword to R.sub.0 of the last interleaved codeword, and these coefficients are stored in the error identifier RAM in that order beginning at a fixed address. Further, the number of interleaved codewords can be either five or ten, so the address in the identifier RAM of coefficient R.sub.0 of a codeword is not fixed. Therefore it is desirable to use a syndrome computation which accepts the remainder coefficients in order from R.sub.d-2 to R.sub.0 ; where the order of the two steps of syndrome computation is reversed and the order in which the coefficients R.sub.j are processed within each steps is reversed, i.e. in the first step, R.sub.d-2 through R.sub.t are processed to produce values B.sub.m+i and in the second step, R.sub.t-1 through R.sub.0 are processed to produce syndromes S.sub.m+i as the EXCLUSIVE-OR sums of respective values A.sub.m+i and B.sub. m+i.

Errors can be located by finding the inverse roots of the error locator polynomial ##EQU13## where e is the number of errors, 1.ltoreq.e.ltoreq.t. Observe that at a root .alpha..sup.i of .sigma.(x), ##EQU14##

The roots of .sigma.(x) can be found by successively evaluating .sigma.(x) at all x=.alpha..sup.i for i from 0 to n-1, where n<2.sup.b is the codeword length. A value of .alpha..sup.i for which .sigma.(.alpha..sup.i) evaluates to zero is a root of .sigma.(x), and (-i) is the corresponding error location. This method is known as a Chien search.

The circuit of FIG. 11 can be shared for computing frequency-domain syndromes according to equation (9) and for finding the roots of the error locator polynomial .sigma.(x) according to equation (12) for codes with odd d. FIG. 11 comprises t+1 registers denoted D(0) through D(t); t+1 constant finite-field multipliers 140 implementing multiplication by .alpha..sup.j for j from 0 to t, t+1 three-input multiplexers 141; a symbol-wide gating circuit 146; register DM; a constant finite-field multiplier 142 implementing multiplication by .alpha..sup.m ; a (t+1)-input EXCLUSIVE-OR circuit 143; and two variable finite-field multipliers 144 and 145. Multipliers 144 and 145 may best be implemented as one multiplier with appropriate multiplexing of inputs and output. All registers, multipliers, multiplexers and data paths are symbol wide. FIG. 11 implements a reduction in circuitry which is possible when d is odd; when d is even the circuit of FIG. 9, modified for even d as described above, is used.

The computation of frequency-domain syndromes with the circuit of FIG. 11 is performed in a fashion similar to that used for the circuit of FIG. 9. Control signal GT is deasserted so that the output of gating circuit 146 is zero.

The search for the roots of .sigma.(x) using the circuit of FIG. 11 is accomplished by first loading coefficients .sigma..sub.j into the e+1 registers D(e-j) for j from 0 to e and loading zero into registers the t-e registers D(j) for j from e+1 to t. Control signal GT is asserted so that the input of gating circuit 146 is passed to its output. The following process is repeated n times for i from 0 to n-1: if OUT1 is zero, a root has been found and the error location is i; to search for another root, store the outputs of multipliers * .alpha..sup.j 140 in respective registers D(j) for j from 0 to t.

Multiplying equation (12) by .alpha..sup.i.multidot.t and transforming j, we obtain ##EQU15##

The circuit of FIG. 12 can be shared for computing syndromes according to equation (10) and for finding the roots of the error locator polynomial .sigma.(x) according to equation (13). FIG. 12 comprises t+1 registers 157 denoted D (t) through D(2.multidot.t); t+1 constant finite-field multipliers 150 implementing multiplication by .alpha..sup.j for j from t to 2.multidot.t; register 158 denoted DT; a constant finite-field multiplier 156 implementing multiplication by .alpha..sup.-t ; t+1 three-input multiplexers 151; register 159 denoted DM; a constant finite-field multiplier 152 implementing multiplication by .alpha..sup.m, a (t+1)-input EXCLUSIVE-0R circuit 153; and two variable finite-field multipliers 154 and 155. Multipliers 154 and 155 may best be implemented as one multiplier with appropriate multiplexing of inputs and output. All registers, multipliers, multiplexers and data paths are symbol wide.

The computation of frequency-domain syndromes with the circuit of FIG. 12 is performed in a fashion similar to that used for the circuit of FIG. 10.

The search for the roots of .sigma.(x) using the circuit of FIG. 12 is accomplished by first loading the coefficients .sigma..sub.j-t into the e+1 registers D(e-(j-t)) for j from t to t+e and loading zero into the t-e registers D(j) for j from t+e+1 to 2.multidot.t. The following process is repeated n times for i from 0 to n-1: if OUT1 is zero, a root has been found and the error location is i; to search for another root, store the outputs of multipliers * .alpha..sup.j 150 in respective registers D(j) for j from t to 2.multidot.t.

Circuitry for computing syndromes in two steps and performing the Chien search is implemented in the preferred embodiment as shown in FIG. 16, FIG. 20, and FIG. 21. The IDC block fetches instructions from the ROM and decodes them to generate control signals for the RAM and the other blocks. Remainder coefficients R.sub.j ; values B.sub.m+i and syndromes S.sub.m+i ; and error locator polynomial coefficients o.sub.j are stored in the RAM, with values B.sub.m+i and syndromes S.sub.m+i sharing the same storage elements. Registers 192 denoted D(0) through D(8); multiplexers 191 denoted M(0) through M(8); multipliers 193 denoted A(8) through A(16); and EXCLUSIVE-OR circuit 194 denoted FX of FIG. 20 correspond to registers D(t) through D(2.multidot.t); multiplexers 151; multipliers * .alpha..sup.j 150 for j from t to 2.multidot.t; and EXCLUSIVE-OR circuit 153 of FIG. 12. Registers 202 denoted A135L, multiplier 201 denoted A135, register 206 denoted D0, and multiplier 204 denoted A247 of FIG. 21 correspond to register DM, multiplier * .alpha..sup.m 152; register DT, and multiplier * .alpha..sup.-t 156 of FIG. 12. Finite-field variable multiply-and-sum circuit 208 denoted VMS of FIG. 21 corresponds to finite-field variable multipliers 154 and 155 of FIG. 12 implemented as a single multiplier with multiplexed inputs and outputs and the circuit which produces the syndromes S.sub.m+i as the EXCLUSIVE-OR sums of corresponding values A.sub.m+i and B.sub.m+i.

FIG. 13 is a flow chart of the improved iterative algorithm of the present invention. In FIG. 13, the "++" operator exchanges the values of two variables and v.sub.d, v.sub.n and v.sub.k are arbitrary non-zero constants. In step 11, counters n, l.sub.k and l.sub.n ; parameter d.sub.k ; and polynomials .sigma..sup.(k) and .sigma..sup.(n) are initialized. In step 12, .sigma..sup.(k) is multiplied by x and the nth discrepancy d.sub.n is calculated. If d.sub.n is zero, control passes to step 15. Otherwise, if counter l.sub.k is less than or equal to the counter l.sub.n, control is passed to step 14. Otherwise step 13 exchanges the values of counters l.sub.k and l.sub.n ; exchanges the values of parameters d.sub.k and d.sub.n ; and exchanges the values of .sigma..sup.(k) and .sigma..sup.(n) by exchanging the addresses of .sigma..sup.(k) and .sigma..sup.(n). Step 14 updates error locator polynomial .sigma..sup.(n). Step 15 increments counter n. Then if counter n is less than t+l.sub.n, control is passed to step 12. Otherwise, the iterative algorithm has been completed and .sigma..sup.(n) is the desired error locator polynomial.

The improved iterative algorithm reduces implementation complexity and cost by requiring only two polynomial coefficient storage areas, instead of three, and decreases the time needed to compute the error locator polynomial by eliminating the need to copy polynomial coefficients from one storage element to another. The improved iterative algorithm is particularly suited for implementation in hardware, where exchanging the values of two variables is simply accomplished by cross-connecting the outputs and inputs of two registers which contain the values, or, as in the case of variables stored in a random-access memory, of two registers which contain the addresses of the memory elements which contain the values.

In the preferred embodiment of the invention, implementation complexity is reduced and speed of operation is increased by storing the coefficients of each polynomial .sigma..sup.(n) and .sigma..sup.(k) in a number of memory elements equal to 2.multidot.t+1 wherein the first t and last t elements are initially cleared to zero and the middle element is initialized to an arbitrary non-zero constant. The coefficients of polynomials .sigma..sup.(n) and .sigma..sup.(k) are stored in order of increasing degree of x. The operation of multiplying .sigma..sup.(k) by x is implemented by decrementing a register containing the address of the low-order coefficient of .sigma..sup.(k). The operation of exchanging the coefficients of .sigma..sup.(n) and .sigma..sup.(k) is implemented by exchanging the contents of two registers containing the addresses of the low-order coefficients of .sigma..sup.(n) and .sigma..sup.(k). The operation of computing .sigma..sup.(n) = d.sub.k *.sigma..sup.(n) .sym.d.sub.n *.sigma..sup.(k) where l.sub.k <l.sub.n is performed in a loop repeated l.sub.n times for i from 0 to l.sub.n -1. This operation does not require any special treatment for those coefficients of .sigma..sup.(k) where i>l.sub.k.

Circuitry for performing the new iterative algorithm of the present invention as implemented in the preferred embodiment is shown in FIG. 16, FIG. 17, FIG. 21 and FIG. 23. Referring to FIG. 16, the IPC (Instruction Processing Circuit) block FIG. 23 fetches instructions from the ROM and controls the circuitry of the RAM, the APC (Address Pointer Circuit) block FIG. 17 and the FFP (Finite Field Processor) block FIG. 21. The RAM holds the value of counter n at location N; the syndromes, beginning at location S; and the coefficients of polynomials .sigma..sup.(k) and .sigma..sup.(n), low-order first beginning at the locations contained in registers 175 denoted SK and 171 denoted SN of FIG. 17, respectively. Registers 277 denoted LK and 278 denoted LN of FIG. 23 contain the values of counters l.sub.k and l.sub.n, respectively. Registers 203 denoted DK and 206 denoted D0 of FIG. 21 hold the values of parameters d.sub.k and d.sub.n, respectively.

For step 1, LK and LN are cleared to zero, SK and SN are initialized, the locations in the RAM used for the coefficients of polynomials .sigma..sup.(k) and .sigma..sup.(n) are initialized, DK is initialized to a non-zero value, and D1 is initialized to -(t-2). For step 2, location N in the RAM is written from D1, LK is incremented, .sigma..sup.(k) is multiplied by x by decrementing SK, D0 is cleared, and the nth discrepancy d.sub.n is calculated by using the VMS Variable Multiply-and-Sum block of FIG. 21 to sum into DO the products of the contents of the RAM elements pointed to by SN and the syndromes in the area in the RAM beginning at location S. The block 274 denoted M40 of FIG. 23 is used to determine if parameter d.sub.n is zero; if so, control passes to step 5. Otherwise, block 212 denoted ADD (Integer Addition Circuit) (FIG. 21) and block 270 denoted AGZ (Greater-than-Zero) Detection Circuit) (FIG. 23) are used to determine if the contents of LK are less than or equal to the contents of LN; if so, control is passed to step 14. Otherwise for step 13, the contents of LK and LN are exchanged; the contents of DK and D0 are exchanged; and the contents of SK and SN exchanged. For step 14, the coefficients of polynomial .sigma..sup.(n) are updated by using the VMS block of FIG. 21 to sum the products of the contents of DK and the contents of the RAM elements pointed to by SK with the products of the contents of D0 and the contents of the RAM elements pointed to by SK using the VMS block of FIG. 21 and then storing the results into the RAM elements pointed to by SN. For step 15, the ADD block of FIG. 21 and the AGZ block of FIG. 23 are used to determine if the sum of the contents of D1 and the contents of LN is less than or equal to zero; if so, the ADD block of FIG. 21 is used to form in D1 the sum of one and the contents of the RAM at location N, and control is passed to step 2. Otherwise, the iterative algorithm has been completed; LN holds the degree and SN holds the address in the RAM of the coefficients of the error locator polynomial .sigma..sup.(x).

In the preferred embodiment of the invention, the adjustment of the CRC information required whenever an error is identified is performed during the Chien search. Circuitry for performing the CRC residue adjustment as implemented in the preferred embodiment is shown in FIG. 18, FIG. 21, and FIG. 23.

The CRC residue is adjusted in a dedicated CRC Residue Adjuster (CRA) comprising a Linear Feedback Shift Register (LFSR) implementing the reciprocal of the CRC code generator polynomial. The registers in the CRA are initially loaded with the CRC residue symbols. Referring to FIG. 18, loading the CRA registers is performed by asserting control signal EN and deasserting control signals SH and FB while presenting the CRC residue symbols on RAM.sub.-- OUT, most-significant symbol first.

The search for roots .alpha..sup.i of the error locator polynomial is performed sequentially for all i from 0 to n. For each interleave in error, before the search for roots reaches i equal to d-1, zero is clocked into the CRA x times, where x is the non-inclusive number of CRC redundancy symbols between the last non-ECC-redundancy symbol of the interleave in error and the first ECC redundancy symbol of the first interleave. For example, referring to FIG. 2, x is equal to 4, 3, 2, 1 and 0 for the interleaved codewords containing the symbols labeled "VU4" "CRC1" "CRC2" "CRC3" and "CRC4" respectively. Referring to FIG. 18, clocking a value into the CRA is performed by asserting control signals EN, SH and FB and presenting the value on CRA.sub.-- IN.

If a root is found for i equal to d-1, the error value is clocked into the CRA; otherwise zero is clocked into the CRA. Then if the symbol corresponding to i equal to d-1 is a CRC redundancy symbol, zero is clocked into the CRA y times where y is the non-inclusive number of CRC redundancy symbols between the symbol corresponding to i equal to d-1 and the last non-CRC-redundancy symbol of the sector. For example, referring to FIG. 2, y is equal to 0, 0, 1, 2 and 3 for the interleaved codewords containing the symbols labeled "VU4" "CRC1" "CRC2" "CRC3" and "CRC4" respectively. For all i greater than d-1, either zero or the value of the error in the symbol corresponding to i is clocked into the CRA.

After all n locations of an interleave in error have been processed, the contents of the dc-1 CRA registers are shifted out of the CRA and EXCLUSIVE-OR-ed into dc-1 storage elements elsewhere, and the dc-1 CRA registers are cleared to zero. Referring to FIG. 18, the contents of the CRA are shifted out and the CRA registers are cleared to zero by asserting control signals EN and SH and deasserting control signal FB. In the preferred embodiment, referring to FIG. 21, the contents of each CRA register are presented in turn on CRA.sub.-- OUT and, using the VMS block, multiplied by AL.sub.-- OUT and EXCLUSIVE-OR-ed with the contents of the corresponding RAM storage element presented on RAM.sub.-- OUT, the result being stored in D1 and then D1.sub.-- OUT being back into the RAM storage element. This procedure works because AL.sub.-- OUT is always the same, .alpha..sub.n-1, after each interleave has been processed, and the fact that the adjusted CRC residue bytes for each interleave have all been multiplied by a common non-zero factor is immaterial if the sum of all the adjusted CRC residue bytes is zero. Implementation complexity is reduced because no unique instruction or instruction exception condition need be implemented.

After all interleaved codewords have been processed, the dc-1 storage elements are checked for zero. This is performed adding zero to each accumulated adjusted CRC residue byte using the ADD circuit of the FFP FIG. 21 and using the M40 OR circuit in the IPC FIG. 23 to detect any non-zero value.

FIG. 14 shows the CL-SM330's ECC/CRC block, including the interfaces between the error identifier, the Encode/Decode LFSR block, and the other blocks of the CL-SM330. The CORRCLK (Correction Clock) signal clocks the synchronous logic of the error identifier. The five configuration signals SIZE, FORM, SUPP, DIAG and VU.sub.-- PTR and the START, STOP, CONT and DISABLE signals are the outputs of registers in the CL-SM330's Microcontroller Interface block which are programmed by the external microcontroller. The BUSY, DONE, ECC.sub.-- ERR, CRC.sub.-- ERR, THR.sub.-- ERR and OVERRUN signals are applied to the CL-SM330's Microcontroller Interface block. MPU.sub.-- BUS provides an address bus, a data bus, and read/write control signals for external microcontroller access to the error identifier RAM and register AO. The RRCLK, CG.sub.-- RG, RMNDR and T7 signals are provided to the error identifier from the Encode/Decode LFSR block. The VREADY signal is fed from the CL-SM331 Buffer Manager through the CL-SM330's SM331 Interface block to the error identifier. The SEND.sub.-- VEC signal and the FWD.sub.-- OUT and D1.sub.-- OUT buses are applied to the CL-SM330's SM331 Interface block.

SIZE and FORM determine the number of interleaves (hereafter abbreviated as NUM.sub.-- ILVS) and the total number of bytes in the sector (hereafter abbreviated as NUM.sub.-- BYTS):

SIZE, FORM, SUPP, DIAG and VU.sub.-- PTR control assertion of SEND.sub.-- VEC as described below. Assertion of START forces the error identifier to begin identifying errors using the current contents of RAM. If the error identifier is identifying errors, assertion of STOP forces the error identifier to cease identifying errors and to assert DONE. Assertion of DISABLE prevents the error identifier from beginning to identify errors at the trailing edge of CG.sub.-- RG as described below.

FIG. 15 shows the register address and bit assignments for the signals accessible to the external microcontroller through the CL-SM330's Microcontroller Interface block. A number in hexadecimal notation is denoted by appending h to it. Because the overall CL-SM330 busy status is read from bit 6 at register 10h, BUSY is advantageously implemented to be read from bit 4 at address 10h. Because START is best implemented as an edge-triggered control signal and the "write" function of bit 4 of register 10h would otherwise be wasted, START is advantageously implemented to be asserted by writing one to bit 4 at address 10h. Because the CL-SM330 is configured for Read Sector operations by writing bits 3-0 of register 10h, SUPP is advantageously implemented to be simultaneously (de)asserted by writing (zero)one to bit 3 at address 10h. Placing the form factor, sector size and vendor-unique/pointer control signals in the same register allows all three to be controlled with one microcontroller access; therefore VU.sub.-- PTR is (de)asserted by writing (zero)one to bit 5 at address 11h, FORM is (de) asserted by writing (zero) one to bit 1 at address 11h, and SIZE is (de)asserted by writing (zero)one to bit 0 at address 11h. Disabling the error identifier and enabling continuous sector read operation are seldom-used functions, so it is preferred that they be placed in register 12h along with other relatively static CL-SM330 configuration signals; DISABLE is (de)asserted by writing (zero)one to bit 3 at address 12h and CONT is (de)asserted by writing (zero)one to bit 0 at address 12h. Because it is desirable to control related functions by accessing a single address and other medium-related CL-SM330 microcontroller interrupts are enabled and disabled through register 21h, it is implemented so that when one is written to bit 0 at address 21h, the CL-SM330's Microcontroller Interface block will assert an interrupt signal to the external microcontroller when the error identifier asserts DONE. For ease of microcontroller firmware implementation it is advantageous that interrupt status signals be read from the corresponding bits at another address, so DONE is read from bit 0 at address 23h. Placing the error signals for the error identifier in the same register with other CL-SM330 error signals allows all to be read with one microcontroller access; therefore ECC.sub.-- ERR, CRC.sub.-- ERR, THR.sub.-- ERR and OVERRUN are read from bits 7, 6, 5 and 4, respectively, at address 30h. Grouping the error identifier RAM address and data access address with the error identifier error access register yields a more logical organization of the CL-SM330 microcontroller address space, so A0 is written at address 31h and the RAM element at the address in A0 is read or written by reading or writing address 32h. Because A0 is incremented each time the microcontroller accesses the error identifier RAM, the microcontroller firmware is always certain of the value of A0, implementation cost is reduced by providing no path for the microcontroller to read the contents of A0. There is normally no need to transfer error correction vectors for errors in the ECC redundancy bytes, so DIAG is advantageously implemented to be (de)asserted by writing (zero)one to bit 4 at address 3Fh, wherein other bits control other test modes of the CL-SM330.

FIG. 16 is a block diagram of the error identifier. The major blocks comprising the error identifier are the Address Pointer Circuit 165 (APC), CRC Residue Adjuster 164 (CRA), Error Vector Control 166 (EVC), Frequency Domain Circuit 167 (FDC), Finite Field Processor 169, (FFP), Instruction Processing Circuit 162 (IPC), Interleave & Sector Counters 163 (ISC), Random Access Memory 168 (RAM) and Read-Only Memory 161 (ROM).

The output of a register or circuit is denoted by appending ".sub.-- OUT" to its name. The input to a register or circuit is denoted by appending ".sub.-- IN" to its name. A number in hexadecimal notation is denoted by appending `h` to it. Where not otherwise indicated, control signal inputs to registers, multiplexers, etc. are driven from the appropriate "xxx.sub.-- CTU" bus from the IPC block 162, FIG. 23.

In the preferred embodiment of the invention, each instruction is fetched from the ROM and stored in the seventeen-bit instruction register (IR), then decoded from IR.sub.-- OUT and executed during the next clock cycle. By pipelining the instruction in this manner, it is immediately available at the beginning of each cycle with no ROM-access delay. Also, the decoding of instruction bits required to select the proper address to be applied to the RAM address bus is performed using ROM.sub.-- OUT rather than IR.sub.-- OUT, and the selected address is stored in the eight-bit RAM address register (RA) and applied during the next cycle. By pipelining the RAM address in this manner, it is immediately available at the beginning of each cycle with no instruction-decoding delay.

FIG. 17 is a block diagram of the Address Pointer Circuit (APC), which controls the address and data input buses of the RAM and the loading of FDC registers D(i). APC includes A0, A1, AM, D49, RA, RMX, SK and SN.

A0 is an eight-bit register 172 which can supply an address for indirect access to the RAM. A0 can be loaded from SN.sub.-- OUT, from RAM.sub.-- OUT, or from the external microcontroller data bus. Bits 7-5 of A0.sub.-- IN are forced to zero when SN is the source. A0 can be incremented. NUM.sub.-- ILVS can be added to A0.

A1 is a seven-bit register 176 which can supply an address for indirect access to the RAM or to the FDC registers D(i). A1 can be loaded from SK.sub.-- OUT or from ADD.sub.-- OUT. Bits 7-5 of A1.sub.-- IN are forced to zero when SK.sub.-- OUT is the source. A1 can be incremented or decremented.

AM is a three-input, eight-bit-wide multiplexer 173 which supplies input to RA. Its inputs are A0.sub.-- OUT, A1.sub.-- OUT and bits 6-0 of ROM.sub.-- OUT. Bit 7 of AM.sub.-- OUT is forced to zero when A1.sub.-- OUT or ROM.sub.-- OUT is the selected source.

D49 is a four-to-nine decoder 177 with enable. A1.sub.-- OUT is applied to D49.sub.-- IN. D49.sub.-- OUT is applied to the LD.sub.-- D(i) inputs of FDC multiplexers M(i).

RA is an eight-bit register 174 which holds the address applied to the RAM address bus during the execution of an instruction. RA is loaded from AM.sub.-- OUT.

RMX is a four-input, eight-bit wide multiplexer 178 which supplies input to the RAM data bus. Its inputs are FDC.sub.-- OUT, M3.sub.-- OUT, CER.sub.-- BUS and the external microcontroller data bus.

SK is a five-bit register 175 which holds the address of the low-order coefficient of the .sigma..sup.(k) polynomial in the RAM. SK can be preset to 0Eh or loaded from SN.sub.-- OUT. SK can be decremented.

SN is a five-bit register 171 which holds the address of the low-order coefficient of the .sigma..sup.(n) polynomial in the RAM. SN can be preset to 1Fh or loaded from SK.sub.-- OUT.

FIG. 18 is a block diagram of the CRC Residue Adjuster (CRA), which is a LFSR implementing H(x), the reciprocal of the Reed-Solomon generator polynomial GC(x) for the ANSI/ISO standard CRC code. CRA comprises four eight-bit registers (185-188) denoted C0, C1, C2 and C3; the CM computation circuit 183, described below; a two input, eight-bit-wide multiplexer 184 deonted MX; a two input, eight-bit-wide EXCLUSIVE-OR circuit 181 denoted EO; and an eight-bit gating circuit 182 denoted CG. The output of C3 is CRA.sub.-- OUT. CRA.sub.-- IN and CRA.sub.-- OUT are applied to the inputs of EO. EO.sub.-- OUT is applied to CG.sub.-- IN. CG.sub.-- OUT, C2.sub.-- OUT, C1.sub.-- OUT and C0.sub.-- OUT are applied to inputs A, B, C and D of CM, respectively. Outputs W, X and Y of CM are applied to C3.sub.-- IN, C2.sub.-- IN and Cl.sub.-- IN, respectively. Output Z of CM and RAM.sub.-- OUT are applied to the inputs of MX. MX.sub.-- OUT is applied to CO.sub.-- IN.

To "clock the CRA" means to perform the combination of actions specified by bits 4-1 of IR-OUT:

CM is a four-input, four-output, eight-bit-wide constant finite-field computation circuit with inputs A, B, C and D, and outputs W, X, Y and Z, which implements:

W=H.sub.3 *A.sym.B

X=H.sub.2 *A.sym.C

Y=H.sub.1 *A.sym.D

Z=H.sub.0 *A

where H.sub.i are the coefficients of H(x).

FIG. 19 shows Error Vector Control (EVC), which controls the assertion of SEND.sub.-- VEC, the signal which initiates transfer of an error correction vector to the CL-CSM331. Each time the error identifier has located and identified an introduced error, EVC examines the configuration signals and applies the selected condition to FWD.sub.-- OUT. If FWD.sub.-- OUT satisfies the condition, ECV asserts SEND.sub.-- VEC, causing the CL-SM331 Interface block to execute an error correction vector transfer using the current values of FWD.sub.-- OUT and D1.sub.-- OUT.

FIG. 20 is a block diagram of the Frequency Domain Circuit (FDC), which is used to compute syndromes from the time-domain remainders and to search for the roots of the error locator polynomial. The FDC in the preferred embodiment is a variation on the circuit shown in FIG. 12. The FDC comprises nine eight-bit registers 192 denoted D(i) for i from 0 to 8, each associated with a constant finite-field multiplier 193 denoted A(8+i) and a two-input, eight-bit-wide multiplexer 191 denoted M(i); plus a nine-input, eight-bit-wide EXCLUSIVE-OR circuit 194 denoted FX; and an eight-bit-input OR circuit FDO. The output of FX is FDC.sub.-- OUT and is applied to FDO.sub.-- IN. The output of each register D(i) is applied to the input of A(8+i) and to one of the inputs of FX. The output of each multiplier A(8+i) is applied to one of the inputs of M(i). FDC.sub.-- IN is applied to the other input of each multiplexer M(i). The output of each multiplexer M(i) is applied to the input of respective register D(i). When FDC register D(i) is to be loaded from FDC.sub.-- IN, signal LD.sub.-- D(i) from D49.sub.-- OUT is asserted. To "clock the FDC" means to record FDO.sub.-- OUT in the FZD latch within the IAC; to load each register D(i) from the output of its associated finite-field multiplier A(i); to store ALPHA1.sub.-- OUT in the AL register within the FFP; to store A135.sub.-- OUT in the A135L register within the FFP; and to load the FWD register within the ISC from SUB.sub.-- OUT within the ISC.

FIG. 21 is a block diagram of the Finite-Field Processor (FFP), which performs integer addition and variable finite-field multiply-and-sum operations. It includes A135, A135L, A247, ADD, AL, ALPHA1, D0, D1, DK, M1, M2, M3, M4, M5 and VMS. Except as noted, all data paths are 8-bits wide.

A135 is a constant finite-field multiplier 201 implementing multiplication by .alpha..sup.135. A135L.sub.-- OUT is applied to A135L.

A135L is an eight-bit multiplexed register 202 which holds X*.alpha..sup.135.multidot.L, where L is the number of times A135L has been clocked since it was loaded with X from IR.sub.-- OUT. The value loaded into A135L is multiplexed between A135.sub.-- OUT and bits 7-0 of IR.sub.-- OUT. A135L.sub.-- OUT is applied to A135.sub.-- IN and M1.

A247 is a constant finite-field multiplier 204 implementing multiplication by .alpha..sup.247. D0.sub.-- OUT is applied to A247.sub.-- IN. A247.sub.-- OUT is applied to M5.

ADD is a two-input, eight-bit-wide integer addition circuit 212 with a one-bit carry-in signal CI implementing S=A+B+CI. M1.sub.-- OUT is applied to input A. M2.sub.-- OUT is applied to input B. Bit C of IR.sub.-- OUT is applied to input CI.

AL is an eight-bit register 210 which holds .alpha..sup.L-1, where L is the number of times AL has been clocked since it was initialized to .alpha..sup.-1 by assertion of control input I. AL.sub.-- OUT is applied to ALPHA1.sub.-- IN and M2. AL can be initialized to .alpha..sup.-1 or loaded from ALPHA1.sub.-- OUT.

ALPHA1 is a constant finite-field multiplier 209 implementing multiplication by .alpha..sup.1. ALPHA1.sub.-- OUT is applied to AL.sub.-- IN.

D0 is an eight-bit register 206 which is used for many purposes. D0 can be loaded from M5.sub.-- OUT. D0.sub.-- OUT is applied to M1, M2 and A247.sub.-- IN.

D1 is an eight-bit register 214 which is used for many purposes. D1 can be loaded from M4.sub.-- OUT. D1.sub.-- OUT is applied to M2, M3 and the SM331 interface block.

DK is an eight-bit register 203 which is used to hold d .sub.k and for other purposes. DK can be loaded from D0 .sub.-- OUT. DK .sub.-- OUT is applied to M1.

M1 is a six-input, eight-bit-wide invertible multiplexer 207 which supplies input to VMS and ADD. Its inputs are D0.sub.-- OUT, DK.sub.-- OUT, LN.sub.-- OUT, CRA.sub.-- OUT, A135L.sub.-- OUT and zero. Bits 7-4 of the LN.sub.-- OUT input are forced to zero. If bits P and 7 of IR.sub.-- OUT are set, each bit of M1.sub.-- OUT is inverted.

M2 is a seven-input, eight-bit-wide multiplexer 211 which supplies input to VMS and ADD. Its inputs are D0.sub.-- OUT, D1.sub.-- OUT, LK.sub.-- OUT, AL.sub.-- OUT, RAM.sub.-- OUT, FDC.sub.-- OUT and bits 7-0 of IR.sub.-- OUT. Bits 7-4 of the LK.sub.-- OUT input are forced to zero. Bit 7 of the IR.sub.-- OUT input is replaced with bit 6 of IR.sub.-- OUT.

M3 is a three-input, eight-bit-wide multiplexer 215 which supplies input to VMS, CRA and RMX. Its inputs are D1.sub.-- OUT, RAM.sub.-- OUT and zero. M3.sub.-- OUT is CRA.sub.-- IN.

M4 is a three-input, eight-bit-wide multiplexer 213 which supplies input to M5, D1 and the nine FDC registers D(i). Its inputs are VMS.sub.-- OUT, ADD.sub.-- OUT and zero. M4.sub.-- OUT is FDC.sub.-- IN.

M5 is a two-input, eight-bit-wide multiplexer 205 which supplies input to D0. Its inputs are M4.sub.-- OUT and A247.sub.-- OUT.

FIG. 22 is a block diagram of the finite-field Variable Multiply-and-Sum circuit (VMS), which implements Z=(A*B).sym.C, which is computed according to: ##EQU16## VMS comprises a single-input, eight-output constant finite-field multiplier circuit 221 denoted B07; eight eight-bit-wide gating circuits 222 denoted VG(i); and a nine-input, eight-bit-wide EXCLUSIVE.sub.-- OR circuit 223 denoted VX. B07 implements

for i from 0 to 7. Mi.sub.-- OUT is applied to input A of VMS, which is input A of B07. M2.sub.-- OUT is applied to input B of VMS; each bit i of B is applied to the control input G of respective gating circuit VG(i). The eight outputs Z(i) of B07 are applied to the inputs of VG(i), whose outputs are applied to the first eight inputs of VX. M3.sub.-- OUT is applied to input C of VMS, which is the remaining input of VX.

Note that propagation delay from input B of VMS to VMS.sub.-- OUT is less than that from input A of VMS to VMS.sub.-- OUT. RAM access time can be significantly longer than other circuit delays. In the preferred embodiment, the propagation delay from RAM.sub.-- OUT to M2.sub.-- OUT is minimized in preference to the propagation delays from the other inputs of M2 to M2.sub.-- OUT, and M2.sub.-- OUT is applied to input B of VMS rather than to input A of VMS. This minimizes the total propagation delay when a RAM element is applied to VMS and increases the maximum CORRCLK rate which may be applied to the error identifier.

FIG. 23 is a block diagram of the Instruction Processing Circuit (IPC), which controls the operation of other portions of the error identifier. IPC contains AGZ, FZD, GTZ, IA, ID, IM, IR, LA, LC, LK, LN, M40, NZR, XI and ZRO.

AGZ is an eight-bit greater-than-zero detection circuit block 270. Greater than zero means the most-significant bit is zero and at least one other bit is non-zero. ADD.sub.-- OUT is applied to AGZ.sub.-- IN.

FDO is an eight-bit-input circuit (block 272). FDC.sub.-- OUT is applied to FD0.sub.-- IN.

FZD is a one-bit register (block 273) which records FDO.sub.-- OUT whenever the FDC is clocked.

GTZ is a one-bit register (block 271) which records AGZ.sub.-- OUT when each instruction is executed.

IA is an eight-bit register (block 203), which holds the address applied to the ROM address bus. IA can be cleared to zero, incremented, and loaded from IM.sub.-- OUT.

ID is the Instruction-bit Decoding network (block 291), which generates control signals for the error identifier hardware, including but not limited to multiplexer selection signals; register increment-enable, decrement-enable and write-enable signals; and RAM write-enable signals. ID decodes instruction bits from ROM.sub.-- OUT and IR.sub.-- OUT and control signals from the other blocks of IPC to produce control signals applied to the other blocks of the error identifier on the buses labeled APC.sub.-- CTL, CRA.sub.-- CTL, etc.

IM is a two-input, eight-bit-wide multiplexer (block 282) which supplies input to IA. Its inputs are LA.sub.-- OUT and bits 7-0 of IR.sub.-- OUT.

IR is a seventeen-bit register (block 280) which holds the instruction being executed. IR is loaded from ROM.sub.-- OUT. Bits 16-13 of IR.sub.-- IN can be forced to zero to prevent execution of the next instruction by transforming it into a NOP.

LA is an eight-bit register (block 281) which holds the address of the first instruction of a DO loop. LA can be loaded from bits 7-0 of IR.sub.-- OUT.

LC is a four-bit register (block 279) which holds the loop count during execution of a DO loop. It can be loaded from LN.sub.-- OUT or from bits 12-9 of IR.sub.-- OUT.

LK is a four-bit register (block 277) which holds the degree of the .sigma..sup.(k) polynomial. LK can be incremented, cleared to zero, or loaded from LN.sub.-- OUT.

LN is a four-bit register (block 288) which holds the degree of the .sigma.(n) polynomial. LN can be cleared to zero or loaded from LK.sub.-- OUT or from bits 3-0 of ADD.sub.-- OUT.

M40 is an eight-bit-input OR circuit (block 274). M4.sub.-- OUT is applied to M40.sub.-- IN.

NZR is a one-bit latch (block 276) which is set if M40.sub.-- OUT is one when a Load.sub.-- FDC.sub.-- Rem instruction is executed. NZR can be cleared.

XI is the external interface module (block 290). XI controls APC when the external microcontroller is accessing RAM and when CRC residue/ECC remainder bits are being stored in RAM. The XI block of the IPC manages the interfaces to the external microcontroller and the rest of the CL-SM330.

The microcontroller can write register A0 and read or write RAM at the address contained in A0. Each time the microcontroller accesses RAM, XI increments A0.

If at the leading edge of CG.sub.-- RG, either CONT is asserted or BUSY is not asserted, XI presets A0 to the value 3Eh and begins deserializing bits from RMNDR onto the eight-bit-wide CER.sub.-- BUS. When T7 is asserted during the last bit of each byte, XI stores the deserialized byte on CER.sub.-- BUS into RAM at the address contained in A0 and then increments A0. In addition, if at the leading edge of CG.sub.-- RG both CONT and BUSY are asserted, then XI asserts OVERRUN, stops and does not complete the current error identification process.

If at the leading edge of CG.sub.-- RG, CONT is not asserted and BUSY is asserted, then XI asserts OVERRUN, does not store the deserialized CRC residue or ECC remainder bits in RAM, and does not stop the current error identification process.

If at the trailing edge of CG.sub.-- RG, no non-zero bit was detected on RMNDR while CG.sub.-- RG was asserted and either CONT is asserted or OVERRUN is not asserted, then XI asserts DONE.

If at the trailing edge of CG.sub.-- RG, any non-zero bit was detected on RMNDR while CG.sub.-- RG was asserted and DISABLE is not asserted and either CONT is asserted or OVERRUN is not asserted, then XI asserts BUSY and the error identifier begins identifying introduced errors.

When a Stop instruction is executed, XI asserts DONE and stops the error identifier by deasserting BUSY, which forces IA to zero. If an uncorrectable ECC error, uncorrectable CRC error, or error exceeding threshold has been detected, a Stop instruction will be executed which causes XI to assert ECC.sub.-- ERR, CRC.sub.-- ERR, or THR.sub.-- ERR, respectively.

ZRO is a one-bit register (block 275) which records NOT(M40.sub.-- OUT) when each instruction is executed.

FIG. 24 is a block diagram of the Interleave and Sector Counters (ISC) block, which maintains forward displacement and ECC error location counters for the error identifier. IPC comprises CMP, FWD, LOC and SUB. The forward displacement of an error is the non-inclusive number of bytes between the first data byte of the sector and the byte in error.

CMP is a comparator circuit (block 234) with inputs FWD.sub.-- OUT and LOC.sub.-- OUT and outputs FWD.sub.-- LT0, FWD.sub.-- LTNI, LOC.sub.-- EQ16, LOC.sub.-- GT16, LOC.sub.-- EQ17 and LOC.sub.-- GT17, where

FWD.sub.-- LT0=(FWD.sub.-- OUT<NUM.sub.-- ILVS)

FWD.sub.-- LTNI=(FWD.sub.-- OUT<2*NUM.sub.-- ILVS)

LOC.sub.-- EQ16=(LOC.sub.-- OUT==16)

LOC.sub.-- GT16=(LOC.sub.-- OUT>16)

LOC.sub.-- EQ17=(LOC.sub.-- OUT==17)

LOC.sub.-- GT17=(LOC.sub.-- OUT>17)

FWD is an eleven-bit register (block 231) which holds the forward displacements of errors. Bits 6-0 of FWD can be loaded from RAM.sub.-- OUT; when bits 6-0 are so loaded, bits 10-7 of FWD IN are forced to 1001 if SIZE is one or forced to 0100 if SIZE is zero. For each interleave i in error (where 0.ltoreq.i<NUM.sub.-- ILVS), FWD is initialized to NUM.sub.-- BYTS+i before the search for roots is begun. Each time the FDC is clocked, FWD is loaded from SUB.sub.-- OUT. If FDO.sub.-- OUT is zero before the FDC is clocked, then after the FDC is clocked, FWD holds the forward displacement of the error just located.

LOC is a five-bit counter (block 233) which holds the number of times the FDC has been clocked, up to eighteen. LOC can be cleared to zero. If LOC.sub.-- GT17 is zero when the FDC is clocked, LOC is incremented.

SUB is an eleven-bit minus four-bit unsigned subtraction circuit (block 232) implementing

NUM-ILVS is determined by the SIZE signal as described herein.

RAM is a 226-by-eight-bit random-access memory which holds the time-domain CRC residue and ECC remainder bytes, frequency-domain ECC syndromes, polynomial coefficients and other data used by the error identifier. Usage of RAM is as shown in TABLE I. On power up or other initialization, the external microcontroller must write desired error threshold values to locations ILV.sub.-- THR and SCT.sub.-- THR, and must write zero to locations SIG.sub.-- K+9 through SIG.sub.-- K+16 and SIG.sub.-- N+9 through SIG.sub.-- N+16.

The error identifier has no need to access individual CRC residue or ECC remainder bytes using immediate addresses. In the preferred embodiment of the invention, implementation cost is reduced by storing these bytes beginning at RES.sub.-- REM equal to 3Eh, above all other variables stored in the RAM, so that all immediate addresses used to access other variables need be only six bits wide. At the beginning of the error identification procedure, the four CRC residue bytes must be fetched from the RAM in reverse order and stored in the CRA registers and six bytes in the RAM must be cleared to zero. These six bytes are the four locations used for accumulating the adjusted CRC residue beginning at ADJ.sub.-- CRC, the location used for the total error count (TOT.sub.-- ERR), and the location used for the maximum interleave error count (MAX.sub.-- ERR). It is advantageous to place ADJ.sub.-- CRC at 3Ah, TOT.sub.-- ERR at 39h and MAX-ERR at 38h, so that the address register used to access the four CRC residue bytes at consecutive decreasing addresses need not be reloaded before beginning a loop which clears the next six bytes at consecutive decreasing addresses. By placing SIG.sub.-- K at 06h and SIG.sub.-- N at 17h, the registers implemented for SK and SN need be only five bits wide, and this leaves room at 28h for storing the syndromes. The interleave error threshold (ILV.sub.-- THR) and sector error threshold (SCT.sub.-- THR) are placed adjacent to each other at the beginning of the RAM at 00h and 01h, respectively, to simplify microcontroller access. The remaining variables including the number of interleaves left to be processed (ILV.sub.-- LFT), the address or R.sub.15 of the interleave being processed (R15.sub.-- ADR), the seven least-significant bits of the initial forward displacement value for the interleave being processed (MAX.sub.-- FWD) and counter n of the iterative algorithm (N) are placed at the remaining RAM locations 02h, 03h, 04h and 05h respectively.

ROM is a 157-by-seventeen-bit read-only memory which contains the sequence of instructions required to identify errors. TABLE II shows the contents of ROM in binary and hexadecimal form.

Each instruction comprises seventeen bits. The instruction bits are labeled as follows:

The Opcode of an instruction comprises bits Q, P and R. `x` represents a bit whose value may be either one or zero. `a` represents a bit which is part of an immediate ROM or RAM address; it may be either one or zero. `v` represents a bit which is part of an immediate value; it may be either one or zero.

Conventions used for immediate values, immediate addresses and indirect addresses are as follows:

When any instruction with bit L equal to one (except a Conditional.sub.-- Branch or Search.sub.-- For.sub.-- Root instruction) is executed, LC.sub.-- OUT is examined. If LC.sub.-- OUT is zero, IA is incremented; otherwise, LC is decremented and IA is loaded from LA.sub.-- OUT.

When a Search.sub.-- For.sub.-- Root instruction with bit L equal to one is executed, FDC.sub.-- OUT, FWD.sub.-- OUT and LOC.sub.-- OUT are examined. If FDC.sub.-- OUT is zero, FWD.sub.-- LTNI is one, or LOC.sub.-- EQ16 is one, IA is incremented and bits L, Q, P and R of IR.sub.-- IN are forced to zero to prevent execution of the next instruction by transforming it into a NOP instruction; otherwise, IA is loaded from LA.sub.-- OUT.

Perform an eight-bit addition operation with carry-in:

Mi.sub.-- OUT is specified by bits T and F of the instruction. If bit 7 of the instruction is one, each bit of M1.sub.-- OUT is inverted. M2.sub.-- OUT is specified by bits R, 6 and 5 of the instruction. CARRY is bit C of the instruction. ADD.sub.-- OUT is stored in the destination (s) specified by bits D and S of the instruction. The operation

is selected by bits 7 and C of the instruction both equal to one. The operation

is selected by bits T, F and 7 of the instruction all equal to zero and bit C of the instruction equal to one. The operation

is selected by bits T, F and C of the instruction all equal to zero and bit 7 of the instruction equal to one.

The following combinations are exceptions to the foregoing or cause additional functions to be performed:

Perform a finite-field variable multiply-and-sum operation:

MI.sub.-- OUT is specified by bits T and F of the instruction. M2.sub.-- OUT is specified by bits R, 6 and 5 of the instruction. M3.sub.-- OUT is specified by bits C and 7 of the instruction. VMS.sub.-- OUT is stored in the destination(s) specified by bits D and S of the instruction. Note that when bits D and S of the instruction are both zero, the initial value of DO.sub.-- OUT is stored in DK. If bits T and F are both one, the CRA is clocked.

The following combinations are exceptions to the foregoing or cause additional functions to be performed:

If bit F of any instruction with Opcode 111 is one, the FDC is clocked. If both bits S and T of any instruction with Opcode 111 are one, the CRA is clocked.

The sequence of instructions used in the preferred embodiment to implement the error identification procedure is shown in TABLE III. This sequence is implemented in the contents of ROM shown in TABLE II. A variable stored in RAM at a label shown in TABLE I is denoted by the parenthesized label preceded by "*"; the value of a label is denoted by the label itself.

FIG. 25 illustrates the read-sector process for the typical case where DISABLE is zero, CONT is zero and BUSY is zero at the leading edge of CG.sub.-- RG; other cases are described above. First, circuitry in the Encode/Decode LFSR block of the CL-SM330 computes CRC and ECC redundancy over user-data and vendor-unique/pointer bytes read from the optical disk. While CRC and ECC redundancy bits are read CG.sub.-- RG is asserted and CRC residue/ECC remainder bits (which are the EXCLUSIVE-OR sum of the computed and read redundancy bits) are presented on RMNDR. T7 is asserted while every eighth such bit is presented. CG.sub.-- RG, RMNDR and T7 are synchronized with RRCLK. The error identifier deserializes the CRC residue/ECC remainder bits from RMNDR and stores the CRC residue/ECC remainder bytes in RAM. At the trailing edge of CG.sub.-- RG if no non-zero bit was detected on RMNDR while CG.sub.-- RG was asserted, then the error identifier immediately asserts DONE; otherwise, the error identifier asserts BUSY and begins identifying introduced errors.

FIG. 26 illustrates the major steps of the error identification process. In step 1020, the RAM and the CRA are initialized. Then for each interleave, the following process is repeated: In step 1030, compute frequency-domain syndromes from the remainder. If all remainder coefficients are zero, the control is transferred to step 1080. Otherwise in step 1040, compute coefficients of the error locator polynomial from the syndromes, and in step 1050, perform the Chien search to locate each errors, adjusting the CRC residue whenever an error is found.

In step 1060, the RAM elements at MAX.sub.-- FWD and R15.sub.-- ADR are incremented and the RAM element at ILV.sub.-- LFT is decremented. If the RAM element at ILV.sub.-- LFT is not zero, control is transferred to step 1030. Otherwise, in step 1080, if any uncorrectable ECC error was detected, the error identifier asserts ECC.sub.-- ERR and stops; if any of the four RAM elements at ADJ.sub.-- CRC is non-zero, an uncorrectable CRC error has been detected and the error identifier asserts CRC.sub.-- ERR and stops; if the value stored in the RAM element at MAX.sub.-- ERR exceeds that stored in the RAM element at ILV.sub.-- THR or if the value stored in the RAM element at TOT.sub.-- ERR exceeds that stored in the RAM element at SCT.sub.-- THR, a threshold error has been detected and the error identifier asserts THR.sub.-- ERR and stop; otherwise the error identifier stops without asserting any error signal. When the error identifier stops, it deasserts BUSY and asserts DONE.

FIG. 27 shows the process of initializing the RAM and the CRA each time a sector containing errors is detected. First the four CRC residue bytes stored in RAM at RES.sub.-- REM are loaded into the CRA registers. Then the four RAM elements at ADJ.sub.-- CRA, used for accumulating the adjusted CRC residue, the RAM element at MAX.sub.-- ERR, used for the maximum error count and the RAM element at TOT.sub.-- ERR, used for the total error count, are cleared to zero. The RAM element at R15.sub.-- ADR, used to record the address in RAM of R.sub.15 of the current interleave, is initialized to RES.sub.-- REM+4. The RAM element at MAX.sub.-- FWD, used to record the seven least-significant bits of the sum of NUM.sub.-- ILVS and the forward displacement of the last byte of the current interleave, is initialized to NUM.sub.-- BYTS. The RAM element at ILV.sub.-- LFT, used to record the number of interleaves remaining to be processed, is initialized to NUM.sub.-- ILVS.

FIG. 28 is a flow chart of the compute frequency-domain syndromes operation. In step 251, A0, A1, A135L and the FDC are initialized for the first step. Then in step 252, coefficients R.sub.15 through R.sub.8 are read from RAM, multiplied by A135L.sub.-- OUT and stored in D(7) through D(0). As each coefficient specified by A0 is processed, VMS.sub.-- OUT is stored in the FDC register specified by A1, NUM.sub.-- ILVS is added to A0, A1 is decremented and A135.sub.-- OUT is stored in A135L and NZR is set if M40.sub.-- OUT is one; all these functions are performed by the microcengine Load.sub.-- FDC.sub.-- Rem instruction. Then in step 253, the FDC is clocked sixteen times, with the partial syndrome on FDC.sub.-- OUT being stored each time in RAM. Then in step 254, A1, A135L and D0 are initialized for the second step. Then in step 255, coefficients R.sub.7 through R.sub.0 are read from RAM, multiplied by A135L.sub.-- OUT and stored in D(7) through D(0), with A0, A1, A135L and NZR treated as in the first step, again by using the microengine Load.sub.-- FDC.sub.-- Rem instruction. Then in step 256, if none of R.sub.15 through R.sub.0 were non-zero, NZR will be zero and the ECC code detected no errors in the current interleave, the error identification process for the current interleave is complete so control is passed to step 1060 of FIG. 26. Otherwise, the error identification process for the current interleave continues with step 257, in which the FDC is clocked sixteen times, with the EXCLUSIVE-OR sum of the product of FDC.sub.-- OUT and D0.sub.-- OUT and the corresponding partial syndrome from the first step being stored in RAM and A247.sub.-- OUT being stored in D0. This is performed by executing a microengine Compute.sub.-- Syndrome instruction in which the normal function of bits D and S is disregarded and instead, VMS.sub.-- OUT is stored in D1 at the same time that the FDC is clocked and A247.sub.-- OUT is stored in D0. Then in step 258, zero is clocked into the CRA is clocked as necessary to account for any CRC remainder bytes between the last non-ECC remainder byte of the current interleave and the first ECC remainder byte of the sector. Note that this clocking of the CRA could be performed later, e.g. just before the loop in FIG. 30 is begun or immediately after the loop of FIG. 30 is interrupted when the FDC has been clocked d-1 times, but that to do so would increase the required ROM size and time required to perform the error identification procedure.

FIG. 29 is a flow chart of the compute error locator polynomial coefficients operation. This implements the new iterative algorithm of FIG. 13, as detailed in TABLE III. In the preferred embodiment of the invention, the swapping of the contents of LK and LN; DK and D0; and SK and SN are performed using a single microengine Swap.sub.-- K.sub.-- N.sub.-- Regs instruction after one has been stored into D1 using a microengine ADD instruction. When the Swap.sub.-- K.sub.-- N.sub.-- Regs instruction is executed, the product of D1.sub.-- OUT and DK is stored in D0 and D1 at the same time that D0.sub.-- OUT is stored in DK, LK.sub.-- OUT is stored in LN, LN.sub.-- OUT is stored in LK, SK.sub.-- OUT is stored in SN and SN.sub.-- OUT is stored in SK.

FIG. 30 is a flow chart of the find errors and adjust CRC operation. In step 261, A135L, AL, LOC, FWD, A0, A12, D0, D1 and the FDC are initialized. The RAM element at TOT.sub.-- ERR is updated by adding LN. If necessary, the RAM element at MAX.sub.-- ERR is updated with LN. The error locator polynomial coefficients in RAM at the address contained in SN are loaded into the FDC registers D(i). LN is stored in the RAM location at N, then LN is decremented. Then in step 262, the FDC is clocked and L is incremented. Then if none of the conditions for terminating the search for roots was met before the FDC was clocked, the loop of step 263 is begun, in which zero is clocked into the CRA, the FDC is clocked and L is incremented until one of the terminating conditions is met. When one of the terminating conditions is met, the pipelined nature of instruction execution requires that execution of the next instruction be blocked. As disclosed herein, this is accomplished by transforming it into a No-Operation. Then in step 264, D1 is cleared. Then if condition (a) was met, step 265 is performed. In step 265, the RAM element at N is decremented and the error value is computed and stored in D1. Computing the error value requires performing a finite-field variable division. Hardware for performing this operation directly is complex and expensive. In the preferred embodiment, of the invention, implementation cost is reduced by using the following identity to perform finite-field division as a series of finite-field multiplications: ##EQU17##

Proceeding according to equation (14), finite-field division of x by y is performed by first loading x into D1 and y into D0, then repeating the following two-step process b-1 times: store the product of D0.sub.-- OUT and D0.sub.-- OUT in D0, then store the product of D0.sub.-- OUT and D1.sub.-- OUT in D1. The value x/y is produced in D1 and if either x or y was zero, D1.sub.-- OUT is zero.

If the computed error value is zero, an uncorrectable ECC error has been detected, so this fact is recorded and control is transferred to step 1060 of FIG. 26; otherwise, if correction of the identified error is allowed by its forward displacement and the configuration bits, then the forward displacement and value of the identified error are presented to the CL-SM331 Interface block on FWD.sub.-- OUT and D1.sub.-- OUT respectively. The CL-SM331 deasserts VREADY when it is not able to accept an error correction vector. When the error identifier is ready to send an error correction vector, it waits until VREADY is asserted before asserting SEND.sub.-- VEC. Then in step 266, D1.sub.-- OUT is clocked into the CRA if LOC.sub.-- GT16 is one. Then if condition (b) was met, step 267 is performed. In step 267, zero is clocked into the CRA as necessary to account for any CRC remainder bytes between the last non-CRC remainder byte of the sector and the last non-ECC remainder byte of the current interleave. Then if condition (c) was not met, control is transferred to step 262, otherwise step 268 is performed. In step 268, if the RAM element at N is not zero, an uncorrectable ECC error has been detected so this fact is recorded and control is transferred to step 1060 of FIG. 26; otherwise, the EXCLUSIVE-OR sums of the four RAM elements at ADJ.sub.-- CRC and the products of the contents of the CRA registers and AL.sub.-- OUT are stored in RAM at ADJ.sub.-- CRC and then control is transferred to step 1060 of FIG. 26.

There has been disclosed and described in detail herein the preferred embodiment of the invention and its method of operation. From the disclosure it will be obvious to those skilled in the art that various changes in form and detail may be made to the invention and its method of operation without departing from the spirit and scope thereof.