Integrated Circuit Driver Having Current Limiter for Brushless Motor

The invention relates to brushless motors having electric commutation means.

Brushless motors are well known. Conventionally, these motors comprise a housing rotatably supporting a rotor carrying a plurality of permanent magnets arranged in pole pairs. These magnets supply the field flux. A plurality of stators are are arranged about the rotor. Each stator has stator windings such that the interaction of current passing through the winding with the flux of the rotor magnets produces torque if the current through each stator winding is timed correctly with respect to rotor position.

Typically, brushless motors provide the necessary commutation position feedback information to a motor controller through the use of either an optical encoder mounted on the end of the motor or through Hall effect sensors placed in close proximity to a disc having a magnetic pattern thereon which rotates with the rotor.

U.S. Pat. No. 4,931,712 to DiGiulio et al. entitled Multiple Channel Servo Configuration discloses an arrangement for driving brushless motors in a mailing machine environment.

U.S. Pat. No. 5,010,282 to Moberg suggests the use of an integrated circuit device which eliminates a sense resistor for the motor current by detecting the drain-to-source voltage of a power FET and generating a feedback current that is proportional to it.

U.S. Pat. No. 4,814,674 also teaches the use of a monolithic integrated circuit which includes a pulse shaping circuit for shaping the slope of the driving pulse edges.

U.S. Pat. No. 4,544,868 teaches a pulse-width modulation circuit to monitor the current supplied to the motor and to interrupt motor energization whenever the current rises above a reference level. The circuit is also used to provide regenerative braking whenever the direction of motor rotation is to be reversed.

It is therefore an object of the invention to provide an integrated circuit driver for commutating a brushless motor and more particularly a device which includes all low-power driver functions which may be placed on the end of the brushless motor.

It is a further object of the invention to provide an integrated circuit driver having an analog current limiter that dynamically switches back and forth between a high current limit and low current limit mode to allow maximum torque available for acceleration without damaging the power-switching FET's and motor windings or demagnetizing the motor.

The aforementioned and other objects are accomplished by providing an integrated circuit driver for a brushless motor having encoder means comprising a plurality of Hall-effect sensors operative for providing commutation information to a motor controller, the integrated circuit comprising means for decoding the commutation information from the Hall-effect sensors, output means connected to said decoding means, said output means being operative for providing switching signals in accordance with the decoded commutation information and an analog current limiter, said current limiter including means for dynamically switching the current limit values for current in the motor between a high current limit value and a low current limit value.

FIG. 1 is a block diagram of an integrated circuit motor driver chip in accordance with the invention.

FIG. 2 is a block diagram of a current limiter circuit on the chip.

FIG. 3 is a schematic diagram of the differential amplifier sub-block.

FIG. 4 is a schematic diagram of the sample and hold circuit sub-block.

FIG. 5 is a schematic diagram of the window comparator sub-block.

FIG. 6 is a schematic diagram of the pulse by pulse comparator sub-block.

FIG. 7 is an overall schematic diagram of the current limiter section of the chip in accordance with the invention.

FIG. 8 is a schematic diagram of the sample clock generator.

FIG. 9 is a schematic of a suitable RC oscillator.

FIG. 10 is a timing diagram of the CL.sub.-- TRIP.sub.-- B signal.

FIG. 11 is a timing diagram of the sample clock generator.

FIG. 12 is a timing diagram of the sample clock generator with the CL.sub.-- TRIP.sub.-- B signal.

FIG. 13 is an overall schematic diagram of the chip in accordance with the invention.

FIGS. 14A, 14B and 14C comprise a schematic diagram of the phase generator sub-block.

FIG. 15 is a schematic diagram of the commutation decoder.

FIG. 16 is a timing diagram of the dead time generator.

FIG. 1 shows at 10 an overall block diagram of an integrated motor driver chip in accordance with the invention. The chip 10 comprises a digital commutator and controller functional block shown at 12, an analog current limiter block at 14, and a quadrature encoder block at 16.

The commutator and controller 12 receives a direction and PWM signal indicated at 18 from a central controller (not shown) along with miscellaneous control information at 20 to provide commutated sink and source outputs at 22 for controlling power FET's (not shown) in correspondence with position information provided by Hall sensors fed in at 24.

The Hall sensors also feed quadrature encoder 16. Conventional optical encoder information may also be fed to the encoder as seen at line 26. The quadrature output signals developed from this information are provided on output channels as shown at 28.

The analog current limiter 14 receives sense voltage information at 30 which corresponds to the motor current and develops in accordance with a current limit value provided at 32 control information to the controller 12 along lines 34. Information also passes to the limiter 14 as indicated at 36.

A block diagram of the current limiter 12 is shown in FIG. 2. The purpose of the current limiter section is to provide protection for both the FET's and the motor windings. A high current is allowed to flow during start-up and then the limit is switched to a lower current limit mode to prevent excessive power dissipation in the drive FET's and motor windings. Differential amplifier 50 receives input signals Vsense and Vsense.sub.--. The output of differential amplifier 50 is fed to sample and hold circuit 52 and to pulse-by-pulse comparator 54. The other input to comparator 54 is provided by window comparator 56. The switch over from a high current limit to a low current limit is preferably controlled by an external RC time constant and the window comparator 56. The high and low current limit values are established by way of off-chip voltage sources.

FIG. 3 is a schematic diagram of the differential amplifier section. As mentioned previously, the input to the differential amplifier is at the Vsense and Vsense.sub.-- pins of the chip. Preferably the voltage is developed across an external sense resistor (not shown) which is proportional to the current of the motor winding. In the embodiment discussed here, the voltage across the sense resistor is a signal with a duty cycle between 0% and 100% and an amplitude that varies between 0 and 1.2 volts.

The differential amplifier section 50 comprises an operational amplifier 60, matching resistors indicated at 62 with nominally a DC gain of 2 and a minimum closed-loop bandwidth of 300 kHz. Capacitors 64 suppress unwanted oscillation. Level shift circuitry indicated at 66 is provided to shift the sense voltage by approximately 500 mV to minimize any gain error of the amplifier.

FIG. 4 is a schematic diagram of the sample and hold circuit 52. It will be appreciated that the output of the differential amplifier segment 50 represents an instantaneous current in a motor winding only during the FET on-time. In the preferred embodiment, it is sampled during each of the PWM cycles and only when a source output is active in order to generate the peak envelope of the instantaneous motor current. As will be discussed below, the sample clock is generated as long as a source output is on except for the blanking period. The sampled output is fed from block 70 to operational amplifier 72. Preferably, the 3 time constant of the input sample and hold circuit is set to be less than the minimum sample clock period (here 400 ns).

FIG. 5 is a schematic diagram of the window comparator 56. As seen in FIG. 5, a signal COMP.sub.-- IN is applied to the respective inputs of two op-amps 80 and 82. In the present embodiment this signal is the average voltage of the sampled motor current. Two off-chip voltages are applied to the other inputs of the comparators; the CL.sub.-- AVG.sub.-- H to comparators 80 and CL.sub.-- AVG.sub.-- L to comparator 82. The difference between CL.sub.-- AVG.sub.-- L and CL.sub.-- AVG.sub.-- H provides hysteresis. The outputs of the comparators are fed as shown to flip-flop 84 which applies either CL.sub.-- LOW or CL.sub.-- HIGH to the pulse by pulse comparator 54 via 2 analog switches.

It will be appreciated that the window comparator 56 dynamically determines the mode of high or low current limit operation, based on the input voltage applied to the COMP.sub.-- IN pin and the off-chip voltages. After power-up, the window comparator output is high and the high-current limit mode is activated since the COMP.sub.-- IN voltage is lower than the CL.sub.-- AVG.sub.-- L voltage. If the COMP.sub.-- IN voltage increases and eventually becomes higher than the CL.sub.-- AVG.sub.-- H voltage level, the output of the comparator becomes low and the current limiter folds back to a low-current limit mode. The low-current limit mode is kept activated until the COMP.sub.-- IN voltage decreases below the CL.sub.-- AVG.sub.-- L level at which point the high current mode is switched back again.

FIG. 6 is a schematic of the pulse by pulse comparator circuit 54. The purpose of the pulse by pulse comparator 54 is to compare the output of the differential amplifier 50 with either one of the off-chip reference voltages selected by the the window comparator 56. The output of the differential amplifier is fed to one input of comparator 90 while the other input receives the selected input based on the output of the window comparator. If the signal RSFFQ is high, then the output of the differential amplifier is compared against the off-chip high current limit reference value CL.sub.-- HIGH. If the output of the window comparator is low, then the output of the differential amplifier is compared against the off-chip low-current reference value, CL.sub.-- LOW.

It will be appreciated that the output of the comparator 54, CL.sub.-- TRIP.sub.-- B, is an active low signal which indicates that the output of the differential amplifier representing the instantaneous motor current exceeded the limit value, either CL.sub.-- HIGH or CL.sub.-- LOW. The overall schematic diagram of the current limiter functional block is shown in FIG. 7 and will not be discussed further in view of the foregoing explanation of its various parts.

FIG. 8 illustrates at 100 a schematic diagram of the logic of the sample clock generator circuit. The clock generates a sample pulse with each rising edge of the PWM signal. The first three clock periods after the rising edge of the PWM signal are blanked by the blanking input shown at block 102. The purpose of the blanking period is to avoid sampling the motor current when the power FET starts to turn on. The blanking period is suitably set at a default of three clock periods to exceed the settling time of the motor current. It will be appreciated that the blanking period may be changed to two clock periods by wire bonding the BLNK.sub.-- SEL pin which inputs to block 102 to GND.

FIG. 9 is a schematic diagram of the RC oscillator 120 which provides a clock reference for the chip. The illustrated circuit may be used either as a crystal/resonator controlled oscillator or as an RC controlled oscillator. For the RC oscillator mode illustrated, external resistor 122 is connected between the OSCOUT and OSCIN pins and a capacitor 124 is connected externally between the OSCIN pin and ground. It will be understood that in the RC oscillator mode, the amplifier design becomes a comparator-oscillator type with both positive and negative feedback. The positive feedback is accomplished through the internal hysteresis network indicated at 126 and the negative feedback is accomplished through the external resistor 122. Capacitor 124 is charged or discharged through the external resistor and thus determines with the external resistor 122 the time constant. Thus the time constant and the hysteresis voltage is the basis for oscillation.

FIG. 10 is a timing diagram of the CL.sub.-- TRIP.sub.-- B signal. It will be understood from the foregoing that typically the CL.sub.-- TRIP.sub.-- B signal is active for a short period of time (less than the PWM period). Thus the CL.sub.-- TRIP.sub.-- B signal is latched to stop the motor current for the remainder of the PWM period. In FIG. 10 this latched signal is called LIMIT.sub.-- B. The latch is released at the next rising edge of the PWM signal and the motor current may start to flow again.

It will however be appreciated that if the PWM is greater than 99% duty cycle so that the next rising edge of the PWM is not detected by circuit, the latch will not be released until more than 132 clock periods, that is approximately 1.5 PWM period, are exhausted counting from the last rising edge. It should be noted also that if the CL.sub.-- TRIP.sub.-- B is activated during a blanking period, it is not recognized until the blanking period is completed.

FIG. 11 is a timing diagram of the sample clock generator. It will be recalled from the previous discussion of the sample clock generator circuit that the first three clock periods after the rising edge of the PWM signal are blanked. In FIG. 11 the sample clock output is labelled as SCLK. At the first rising edge of the PWM signal no sample is generated since the PWM width is less than the blanking period. The second case shows the sample clock with 2 clock period blanking and the last illustrated case shows that the sample clock is generated after the 3 clock period blanking period.

The sample clock is active high as long as the PWM signal is high. The sample clock is disabled if the current limit is activated, but the sample clock is re-generated after the 132 clock periods from the last rising edge as long as the PWM is high. It will be understood that even if the PWM signal is either below 1% duty cycle or even 0% duty cycle, the sample clock is generated for the purpose of refreshing the sample and hold circuit capacitor. In this case the sample clock is only one clock period wide and is activated every 132 clock periods so long as the PWM is below 1% duty cycle.

FIG. 12 is a timing diagram of the sample clock generator with the CL.sub.-- TRIP.sub.-- B signal. As seen in this Figure, the sample clock is turned off when the CL.sub.-- TRIP.sub.-- B signal is active. This serves to ensure that the sample clock is only valid when the SOURCE.sub.-- B signal is active. The sample clock is active high again on the next rising edge of the PWM signal.

FIG. 13 is an overall schematic diagram of the integrated circuit chip 10. The various pins are shown along with a description in Table 1. The various input and output signals are buffered in conventional manner and the various components correspond in general to the block diagram of FIG. 1 so that it is not believed necessary to detail the various logic gates and flip-flops connecting the various parts of the circuit. It will be necessary to describe in more detail the block 200 labelled PHASE and the commutation decoder circuit 300 labelled CD.

FIGS. 14A, 14B and 14C comprise the schematic diagram of the phase sub-block. In FIG. 14A the inputs from the Hall-effect sensors on the motor are received and clocked into shift registers so as to provide both new and old values for the transitions of the sensors. As seen in FIG. 14B these new and old sensor states are applied to logic arrays shown at 208 and 210 for the purpose of generating CNT.sub.-- DN and CNT.sub.-- UP signals respectively. In FIG. 14C these signals are in turn applied to logic array to generate quadrature output signals CHB and CHA as the output of flip-flops 214 and 216 respectively. These outputs are selectively applied to output pins 6 and 7 of the chip as shown in FIG. 13 whenever the SEL input is high. Further details of a quadrature signal generator as shown here may be obtained from U.S. patent application Ser. No. 08/018,599 entitled METHOD AND APPARATUS FOR GENERATING A QUADRATURE SIGNAL USING COMMUTATION SENSORS (Atty. Docket No. C-959) filed on even date herewith and assigned to the assignee of the present invention now abandoned. When the SEL multiplexer input is low, the quadrature encoder signals are driven directly from the external optical encoder.

FIG. 15 is a schematic diagram of the commutation decoder circuit. The sensor outputs from the phase circuit 200 are also sent to the commutation decoder circuit 300 along with the DIR and CLK and PWM signals and applied to the logic arrays as illustrated in order to provide appropriate commutation signals to the motor. For a discussion of the commutation approach see U.S. patent application Ser. No. 08/018,600 entitled A BRUSHLESS MOTOR HAVING A PROGRAMMABLE LOGIC DEVICE FOR COMMUTATION (Atty. Docket No. C-960) filed on even date herewith and assigned to the assignee of the present invention now U.S. Pat. No. 5,319,291.

The commutation decoder receives the Hall-effect sensor inputs and decodes them to a switching sequence for the motor driver FET's. The Hall-effect sensor inputs and switching sequence outputs are grey-coded. Table 2 shows a decoding truth table for the direction control (DIR) input low. For a reverse rotation (DIR input high), states of the switching sequences become exchanged (not reversed) as shown in Table 3. The logic state (0 or 1) in the tables represents the SINK or SOURCE.sub.-- B output of the integrated circuit chip with external pull-up resistors.

The SINK or SOURCE.sub.-- B outputs are open drain pins in this embodiment. The SOURCE.sub.-- B output may be connected to a 50 V power supply through pull-up resistors and bias the gate input of a P-channel power FET. The SINK output pins may be connected to an 12 V power supply through a pull-up resistor and connected to the gate input of an N-channel power FET. Accordingly for this embodiment it is defined that the SOURCE.sub.-- B outputs should be active low (logic 0) to turn on P-channel power FET's and the SINK outputs should be active high (logic 1) in order to turn on N-channel power FET's.

At every state of the Hall-effect sensor, only one output is turned on for each of the SINK and SOURCE.sub.-- B group. For example, at state 3 in Table 2, SINK 2 is on (logic 1) and SOURCE1.sub.-- B is on (logic 0), but all other outputs are off. As the state of the Hall-effect sensor progresses from the top to the bottom of the Table, it is observed that only two outputs are changing their on/off states in one group, either from SINK group or SOURCE.sub.-- B group, but not both. For example, if the state 3 progresses to state 2 in Table 3, then the two outputs of the SOURCE.sub.-- B group are changing, but all the SINK outputs do not change their states.

The SOURCE.sub.-- B outputs are always gated with the PWM input. Therefore if the PWM is low, the SOURCE outputs are always off (logic 1). On the other hand, the SINK outputs are independent of the PWM input. All SOURCE.sub.-- B and SINK outputs are synchronous with the rising edge of the OSCOUT clock signal. However, if the current limit condition is detected, the SOURCE.sub.-- B outputs are turned off asynchronously, but the SINK outputs are not affected.

FIG. 16 is a timing diagram of the dead time generator circuit of the commutation decode circuit 300. The purpose of the dead time generator is to eliminate the heavy current spike when the motor changes its direction and all output driver polarities reverse. The undesired current spiking occurs because the motor driver FET is not completely turned off when its complementary device is turned on. As can be seen from the schematic of FIG. 15, during the direction reversal, any SOURCE.sub.-- B outputs are turned off temporarily for six cycles as seen in FIG. 16. After the first 3 clock cycles, the SINK outputs change their on/off state according to Tables 2 and 3. Therefore at least 3 clock cycles have passed between SOURCE.sub.-- B turn-off and SINK turn-on or visa versa. At the end of the sixth cycle, the SOURCE.sub.-- B output is turned back on. It will be understood that the 3 clock-cycle delay is calculated to exceed the worst case turn-off time of the motor driver FET's (maximum 1200 ns).