Solid State Imaging Devices for Producing Normal and Mirror Image Signals With the Use of a Reversible Shift Register

The present invention relates to solid state imaging devices and methods for selectively producing normal and mirror image signals.

Video telephones serve to reproduce images of another with whom one is speaking by telephone, and in some cases, provide the ability to produce an image of oneself on the receiving monitor.

The image signal to be transmitted to the distant party is produced as a normal image signal by a television camera of the video telephone. The image of oneself, however, would appropriately be produced as a mirror image, and a normal image signal is not easily employed for this purpose.

Consequently, solid state image pickup devices have been provided with the capability of producing either a normal image signal or a mirror image signal. That is, with the use of such a device, a normal image signal can be transmitted to the other party at a distance, while the mirror image signal may be reproduced by a monitor to provide an image of oneself.

Solid state imaging devices include charge coupled devices (CCD's) having a plurality of picture elements each of which accumulates an electric charge representing an image. The accumulated charge is transmitted as is horizontally and vertically with respect to the device and ultimately converted into an electric image signal which is output by the device. Amplification-type solid state imaging devices, such as MOS-type and JFET-type devices, accumulate charge to develop an image which is read from each of a plurality of picture elements via a respective vertical signal line to a horizontal signal line to be output as an electric image signal.

A conventional amplification-type solid state image pickup device capable of producing either a normal image signal or a mirror image signal is illustrated in FIG. 1 hereof. With respect to FIG. 1, the device includes an image sensor portion 61 coupled with output switches 65 both at an upper horizontal side thereof as well as at a lower horizontal side thereof. The gates of the switches 65 at the upper horizontal side are each coupled with a respective output of an upper horizontal shift register 62 which serves, for example, to control output of a mirror image signal from the device by scanning the upper switches 65 in a first horizontal direction. The .gates of the switches 65 at the lower horizontal side are each coupled with a respective output of a horizontal shift register 63 which serves to control output of a normal image signal from the device by scanning the lower switches 65 in a second horizontal direction opposite the first direction.

The device of FIG. 1 suffers the disadvantage that two horizontal shift registers and two sets of output switches are required, thereby adding a complexity to the device which is not present in imaging devices which produce only a normal image signal and, thus, require only a single horizontal shift register and associated switches. Where both the image sensor portion as well as the shift registers and switches are fabricated on a single substrate, substrate space occupied by the second shift register and associated switches reduces the space available for the image portion, thus reducing the achievable image resolution.

It is an object of the present invention to alleviate the shortcomings and disadvantages of prior art imaging devices.

It is another object of the present invention to provide solid state imaging devices having the ability to produce both normal and mirror image signals while minimizing circuit complexity.

It is a further object of the present invention to provide such solid state imaging devices having improved image resolution.

It is still another object of the present invention to provide such solid state imaging devices which maximize the space available on the substrate for an image sensor portion.

In accordance with an aspect of the present invention, a solid state imaging device comprises an image sensor including a two-dimensional matrix of picture elements arranged horizontally and vertically therein to form a plurality of vertically spaced horizontal lines thereof, the image sensor further including a plurality of vertical lines each coupling vertically disposed ones of the picture elements; a vertical scanning means for selecting the horizontal lines in a predetermined order for reading the picture elements thereof; and a horizontal scanning means coupled with the plurality of vertical lines on one horizontal side of the two-dimensional matrix for selecting picture elements in the selected horizontal lines to output image signals therefrom; the horizontal scanning means being operative to scan the picture elements of the selected horizontal lines through said one horizontal side of the two-dimensional matrix in a first horizontal direction to output a normal image signal, and being operative to scan the picture elements of the selected horizontal lines through said one horizontal side of the two-dimensional matrix in a second horizontal direction opposite the first horizontal direction to output a mirror image signal. Since the horizontal scanning means is operative to scan in the first and second directions, although coupled with the vertical lines on one horizontal side of the two-dimensional matrix, it is possible to employ a single device, such as a reversible shift register, to implement such a horizontal scanning means. This affords the ability to reduce the complexity of the device. In addition, when the device including both the image sensor as well as the vertical and horizontal scanning means, is fabricated on a common substrate, it is possible to dedicate a larger portion of the substrate to the image sensor, thus providing the ability to achieve greater image resolution by maximizing the number of picture elements employed.

In accordance with another aspect of the present invention, a solid state imaging device comprises an image sensor including a two-dimensional matrix of picture elements arrayed horizontally and vertically therein to form a plurality of vertically spaced horizontal lines thereof, the image sensor further including a plurality of vertical lines each coupling vertically disposed ones of the picture elements; a vertical scanning circuit operative to supply a vertical scanning signal to a selected one of the horizontal lines to enable reading of the picture elements therein; a plurality of switching circuits each having an ON state and an OFF state, each of the switching circuits having an input coupled with a respective one of the plurality of vertical lines, an output for providing an image signal from the respective vertical line during the ON state of the switching circuit and a control input for receiving a switching control signal to control the state of the switching circuit; and a reversible shift register having a plurality of shift register stages each having a respective output terminal coupled with a respective control input of at least one Corresponding switching circuit to supply a horizontal scanning signal thereto to turn the at least one corresponding switching circuit ON such that the image signal from the respective vertical line is provided at the output of the at least one corresponding switching circuit, the reversible shift register being operative in a first selectable mode to shift the horizontal scanning signal in a first direction from stage to stage of the reversible shift register to scan the vertical signal lines from a first side of the two-dimensional matrix to a second side thereof, the reversible shift register being operative in a second selectable mode to shift the horizontal scanning signal in a second direction from stage to stage of the reversible shift register to scan the vertical signal lines from the second side of the two-dimensional matrix to the first side thereof. The use of a reversible shift register minimizes the circuit complexity required to carry out either normal or mirror image signal production with the use of a solid state imaging device. The device in accordance with this aspect of the present invention also minimizes the substrate area required for horizontal scanning circuitry when such a device is fabricated on a common substrate, thus permitting a greater number of picture elements to be included on the substrate and greater resolution than heretofore has been possible.

In accordance with a further aspect of the present invention, a method of scanning a solid state imaging device for reading normal and mirror image signals therefrom is provided. The solid state imaging device comprises an image sensor including a two-dimensional matrix of picture elements arranged horizontally and vertically therein to form a plurality of vertically spaced horizontal lines thereof, the two-dimensional matrix having a first horizontal side, a second horizontal side, a first vertical side and a second vertical side, the image sensor further including a plurality of vertical lines each coupling vertically disposed ones of the picture elements. The method comprises the steps of selecting the horizontal lines in a predetermined order for reading the picture elements thereof; reading the picture elements of a selected horizontal line to form a normal image by scanning the plurality of vertical lines at the first horizontal side in a first direction from the first vertical side of the two-dimensional matrix of picture elements toward the second vertical side thereof; and reading the picture elements of a selected horizontal line to form a mirror image signal by scanning the plurality of vertical lines at said first horizontal side in a second direction from the second vertical side of the two-dimensional matrix of picture elements toward the first vertical side thereof.

The above, and other objects, features and advantages of the invention, will be apparent in the following detailed description of certain illustrative embodiments thereof which is to be read in connection with the accompanying drawings forming a part hereof, and wherein corresponding parts and components are identified by the same reference numerals in the several views of the drawings.

As used herein, expressions such as "downwardly", "upwardly", "upper", "lower", "above", "below", "horizontal", "vertical", "left" and "right" when referring to elements of the devices and methods disclosed and/or claimed herein are used in this application to express relative positions and directions, rather than positions and directions with respect to a fixed reference. It is intended that these terms should be broadly construed. Their use herein is for convenience and to promote a clear understanding of the present invention.

The following detailed description, given by way of example, and not intended to limit the present invention solely thereto, will best be understood in conjunction with the accompanying drawings in which:

FIG. 1 is block diagram of a conventional solid state image pickup device providing both normal and mirror image readout capabilities;

FIG. 2 is a partially block and partially schematic diagram of a solid state imaging device in accordance with the first embodiment of the present invention;

FIG. 3 is a schematic diagram of a horizontal shift register adapted for use in the embodiment of FIG. 2;

FIG. 4 is a timing chart for use in explaining the operation of a reversible shift register included in the embodiment of FIG. 2;

FIG. 5 is a partially block and partially schematic diagram of a reversible shift register for use in a second embodiment of the present invention; and

FIG. 6 is a partially block and partially schematic diagram of yet another reversible shift register for use in a further embodiment of the present invention.

With reference to the drawings, and initially to FIG. 2 thereof, a first embodiment of a solid state imaging device in accordance with the present invention is illustrated therein. The solid state imaging device of FIG. 2 includes an image sensor portion 2 in which a plurality of picture elements 1, symbolized by circles in FIG. 2 for purposes of simplicity and clarity, are disposed in vertical lines or columns and horizontal lines or rows to form a two-dimensional matrix extending in vertical and horizontal directions as depicted. The picture elements 1 may be, for example, amplification-type devices, such as MOS or JFET devices. The picture elements of each horizontal line are joined with a respective output of a vertical shift register 3 which serves as a vertical scanning circuit to select each of the lines in succession by applying an appropriate scanning pulse thereto in order to read image signals accumulated in each of the picture elements 1 to a respective vertical line 4. That is, during each horizontal scanning period of an image signal produced with the use of the device of FIG. 2, a single output of the vertical shift register 3 is at a "one" state, while all remaining outputs are at a "zero" state, such that the single output at the "one" state selects the corresponding horizontal line of picture elements 1 to read during that horizontal scanning period. After each period, the "one" state is shifted vertically to the next stage of the shift register in order to read a corresponding, further horizontal line of the image sensor portion 2.

The embodiment of FIG. 2 also includes image signal read circuitry for reading the image signals accumulated in the picture elements 1 by correlation double sampling. Each of the vertical signal lines 4 is connected through a lower horizontal side of the image portion 2 to a node N1 of a respective one of a plurality of read circuits, a representative one of which is described hereinafter.

The node N1 of the representative read circuit is connected to a first terminal of the source-drain circuit of an n-channel transistor Q1, the second terminal of the source-drain circuit of transistor Q1 being coupled with a power source voltage V.sub.DD. Node N1 is also connected with a first terminal of the source-drain circuit of a p-channel transistor Q2, the second terminal of its source-drain circuit being coupled to ground. Transistor Q1 serves as a gate for the output of the respective vertical signal line 4 under the control of a signal .phi.S supplied to its gate. Transistor Q2 serves as a load for the respective signal line 4 and receives an appropriate biasing voltage V.sub.GG at its gate.

A noise removal capacitor C.sub.c has a first terminal connected to node N1 and a second terminal connected to a node N2 and serves to accumulate a signal output from the respective signal line 4 under the control of gate transistor Q1. The first terminal of the source-drain circuit of an MOS transistor Q3 is connected to node N2, the second terminal of the source-drain circuit being coupled to receive a clamp voltage V.sub.clp. The gate of transistor Q3 is provided with a clamp pulse .phi..sub.clp which turns on transistor Q3 to clamp the node N2 to V.sub.clp such that noise, such as reset noise, is suppressed in the image signal read through correlation double sampling.

Node N2 is also connected with the input of a buffer 5 which serves to couple the image signal selectively to the first terminal of one of a pair of capacitors C1 and C2 through the source-drain circuit of a respective one of a pair of MOS switching transistors Q4 and Q5. The second terminal of each of capacitors C1 and C2 is coupled with ground. Each of the capacitors C1 and C2 together with its respective switching transistor Q4 and Q5 forms a sample and hold circuit for an image signal read from the corresponding picture element of a selected horizontal line. Control of each of switching transistors Q4 and Q5 is exercised by a respective one of a pair of sample and hold signals SH1 and SH2 supplied to the gate thereof. During successive horizontal periods, an alternate one of the transistors Q4 and Q5 is turned on during the horizontal blanking interval by a respective signal SH1 and SH2, so that capacitor Cl serves to accumulate and hold image signals of even numbered ones of the horizontal lines while capacitor C2 serves to accumulate and hold image signals of odd numbered ones of the horizontal lines.

The first terminal of capacitor C2 is coupled with a first terminal of the source-drain circuit of an MOS switching transistor Q7, while the first terminal of capacitor C1 is connected with the first terminal of the source-drain circuit of another MOS switching transistor Q6. The second terminal of the source-drain circuit of each of transistors Q6 and Q7 is connected in common to the gate of a further MOS transistor Q9. A first terminal of the source-drain circuit of transistor Q9 is coupled with voltage source V.sub.DD while the second terminal thereof is coupled with one of a pair of horizontal signal lines 6.sub.-1 and 6.sub.-2. Each of the horizontal signal lines 6.sub.-1 and 6.sub.-2 is coupled with alternate ones of the plurality of read circuits through the source-drain circuits of respective transistors Q9. Each of the plurality of read circuits also includes an MOS reset transistor Q8 having a first terminal of its source-drain circuit connected with the gate of transistor Q9 and a second terminal thereof coupled to ground.

A horizontal shift register 7 has a plurality of outputs . . . , 20.sub.n, 20.sub.n+1, . . . (where n is an integer), each of which is coupled with the gates of the transistors Q6 and Q7 of each of a first respective pair of adjacent ones of the plurality of read circuits to control the switching states thereof, as well as to the gates of transistors Q8 of each of an adjacent, second respective pair of the plurality of read circuits. For purposes of simplicity and clarity only two successive ones of the outputs 20.sub.n and 20.sub.n+1 of the horizontal shift register 7 are illustrated in FIG. 2.

The horizontal shift register 7 includes a plurality of successively arranged inverters . . . , 8.sub.-1, 8.sub.-2, 8.sub.-3, 8.sub.-4, . . . each having an input terminal i and an output terminal o. A first group of MOS switch transistors . . . Q11.sub.-1, Q11.sub.-2, Q11.sub.-3, Q11.sub.-4, . . . is provided, each having a source-drain circuit coupled between the output terminal o of a first respective one of the inverters 8.sub.-n (where n is an integer) and the input terminal of a second respective one of the inverters 8.sub.-(n+l.sub.). That is, each of the transistors . . . , Q11.sub.-1, Q11.sub.-2, Q11.sub.-3, Q11.sub.-4, . . . , when the same is turned on, serves to couple the output terminal of the first respective one of the inverters 8.sub.-(n) to the input terminal of the second respective one of the inverters 8.sub.-(n+1). As depicted in FIG. 2, voltage Vin.sub.1 supplied to transistor Q11.sub.-1 represents an output of an inverter to the left of inverter 8.sub.-1. Alternatively, Vin.sub.1 represents a start pulse applied to the left-most one of the inverters . . . , 8.sub.-1, 8.sub.-2, 8.sub.-3, 8.sub.-4, . . .

A second group of switch transistors . . . , Q12.sub.-1, Q12.sub.-2, Q12.sub.-3, Q12.sub.-4, . . . is also provided, each having a source-drain circuit coupled between the input terminal i of a first respective one of the inverters 8.sub.-n and the output terminal of the second respective one of the inverters 8.sub.-(n+1). That is, each of the transistors . . . , Q12.sub.-1, Q12.sub.-2, Q12.sub.-3, Q12.sub.-4, . . . , when the same is turned on, serves to couple the input terminal of the first respective one of the inverters 8.sub.-n to the output terminal of the second respective one of the inverters 8.sub.-(n+1). As depicted in FIG. 2, voltage Vin.sub.2 supplied to transistor Q12.sub.-4 represents an output of an inverter to the right of inverter 8.sub.-4. Alternatively, Vin.sub.2 represents a start pulse applied to the right-most one of the inverters . . . , 8.sub.-1, 8.sub. -2, 8.sub.3, 8.sub.-4, . . . . The first and second groups of the MOS switch transistors may, for example, comprise N-MOS, P-MOS or C-MOS types.

The gates of the first group of MOS switch transistors are connected in common by a first control line to receive a control voltage V.sub.F, while the gates of the second group of MOS switch transistors are connected in common by a second control line to receive the inverse of the control voltage V.sub.F. Accordingly, when the control voltage V.sub.F is at a first level such that the first group of switch transistors . . . Q11.sub.-1, Q11.sub.-2, Q11.sub.-3, Q11.sub.-4, . . . is turned on, the second group of switch transistors . . . , Q12.sub.-1, Q12.sub.-2, Q12.sub.-3, Q12.sub.-4, . . . is simultaneously turned off. Consequently, in the presence of the first level of the control voltage V.sub.F, the output of each of the inverters . . . 8.sub.-1, 8.sub.-2, 8.sub.-3, 8.sub.-4, . . . is provided as an input to the inverter immediately to the right thereof as depicted in FIG. 2, thus to permit shifting of a horizontal scanning signal from left to right within the horizontal shift register 7. As a result, the picture elements 1 of each horizontal line selected to be read are scanned in this process from left to right to produce a normal image signal.

Conversely, when the control voltage V.sub.F is at a second level such that the first group of switch transistors is turned off, the second group of switch transistors . . . , Q12.sub.-1, Q12.sub.-2, Q12.sub.-3, Q12.sub.-4, . . . is simultaneously turned on. Consequently, the output of each of the inverters . . . , 8.sub.-1, 8.sub.-2, 8.sub.-3, 8.sub.-4, . . . is provided as an input to the inverter immediately to the left thereof as depicted in FIG. 2, thus to permit shifting of the horizontal scanning signal from right to left within the horizontal shift register 7. As result, the picture elements 1 are read from right to left as shown in FIG. 2 to produce a mirror image signal.

With reference now to FIG. 3, a schematic diagram of the inverter stages . . . , 8.sub.-1, 8.sub.-2, 8.sub.-3, 8.sub.-4, . . . is provided thereby. As seen in FIG. 3, inverter 8.sub.-1 includes a first p-channel MOS transistor P.sub.1 whose source-drain circuit is coupled between an electric power source voltage V.sub.DD and the drain of a second p-channel MOS transistor P.sub.2. The source of transistor P.sub.2 is coupled with the source of a first n-channel MOS transistor n.sub.1. The drain of transistor n.sub.1 is coupled with a first terminal of the source-drain circuit of a second n-channel MOS transistor n.sub.2, the other terminal of which is coupled to ground. The gates of transistors P.sub.1 and n.sub.2 are commonly coupled with an input terminal of the inverter 8.sub.-1 to receive the input signal Vin.sub.1. The output terminal of inverter 8.sub.-1 is coupled with the sources of the transistors P.sub.2 and n.sub.1.

Inverter 8.sub.-2 is constructed in the same fashion as inverter 8.sub.-1 such that p-channel MOS transistors P.sub.3 and P.sub.4 and n-channel MOS transistors n.sub.3 and n.sub.4 of inverter 8.sub.-2 are coupled in the same manner as transistors P.sub.1, P.sub.2, n.sub.1 and n.sub.2, respectively, of inverter 8.sub.-1. The output of inverter 8.sub.-2, indicated as V.sub.1 is coupled with output 20.sub.n of the shift register 7, as illustrated in FIG. 2.

Inverter 8.sub.-3 likewise is constructed in the same fashion as inverter 8.sub.-1 such that inverter 8.sub.-3 includes p-channel MOS transistors P.sub.5 and P.sub.6 and n-channel MOS transistors n.sub.5 and n.sub.6 coupled in the same manner as transistors P.sub.1, P.sub.2, n.sub.1 and n.sub.2, respectively, of inverter 8.sub.-1.

The fourth inverter 8.sub.-4, as illustrated in FIG. 3, is constructed in the same fashion as inverter 8.sub.-1 such that inverter 8.sub.-4 includes p-channel MOS transistors p.sub.7 and p.sub.8 and n-channel MOS transistors n.sub.7 and n.sub.8 coupled in the same fashion as transistors p.sub.1 , p.sub.2, n.sub.1 and n.sub.2 of inverter 8.sub.-1. The output of inverter 8.sub.-4 is indicated as V.sub.2 which is coupled with output 20.sub.n+1 of the horizontal shift register 7, as illustrated in FIG. 2.

When the inverters . . . , 8.sub.-1, 8.sub.-2, 8.sub.-3, 8.sub.-4 are connected in the fashion illustrated in FIG. 2 and with the first group of switch transistors . . . , Q11.sub.-2, Q11.sub.-3. Q11.sub.-4, . . . turned on, it will be seen that inverters 8.sub.-1 and 8.sub.-2 together form a first flip-flop corresponding with a respective pair of vertical signal lines which are read in response to the output thereof. In addition, it will be seen that inverters 8.sub.-3 and 8.sub.-4 together constitute another flip-flop adjacently coupled with the flip-flop formed by inverters 8.sub.-1 and 8.sub.-2, the output of the flip-flop formed by inverters 8.sub.-3 and 8.sub.-4 corresponding with a further pair of vertical signal lines read thereby. While the flip-flop stages of the shift register circuit 7 are formed with the use of dynamic circuitry, static circuits may instead be employed. Moreover, other types of flip-flop circuits suitable for use as the stages of a shift register may likewise be employed in place of the inverters 8.sub.-1 through 8.sub.-4.

A pair of clock pulses, .phi. and its inverse, are applied to each of the flip-flops thus constituted, such that in the flip-flop formed by inverters 8.sub.-1 and 8.sub.-2 the clock pulse .phi. is applied to the gates of transistors n.sub.1 and p.sub.4, while its inverse is applied to the transistors p.sub.2 and n.sub.3. In the case of the flip-flop formed by the inverters 8.sub.-3 and 8.sub.-4, the clock pulse .phi. is applied to the gates of transistors n.sub.5 and p.sub.8, while its inverse is applied to transistors p.sub.6 and n.sub.7.

FIG. 4 provides a timing chart for use in explaining the manner in which the horizontal scanning signal is shifted through the various stages of the horizontal shift register 7 when the control voltage V.sub.F is at a level which turns on switch transistors . . . , Q11.sub.-1, Q11.sub.-2, Q11.sub.-3, Q11.sub.-4, . . . As shown in FIG. 4, at a first rising edge 40 of the clock pulse .phi., the concurrently high level of the input voltage Vin.sub.1 results in a low level of the output A1 of the inverter 8.sub.-1. Upon the occurrence of the trailing edge 42 of a first clock pulse .phi., the level of the output V.sub.1 of the inverter 8.sub.-2 is brought high in response to the simultaneously low level of the output of the A1 of inverter 8.sub.-1.

Subsequently, at the rising edge 44 of a second clock pulse .phi. the high level of the output V.sub.1 of inverter 8.sub.-2 brings the output A.sub.2 of the inverter 8.sub.-3 low, as indicated in FIG. 4. Thereafter, at the trailing edge 46 of the second clock pulse .phi. the output V.sub.2 of the inverter 8.sub.-4 is brought high. At the same time, the output V.sub.1 returns to a low state. In like manner, at the trailing edge 48 of a third clock pulse .phi., the level of the output V.sub.2 returns to a low level.

It will be appreciated that, when the levels of the control signal V.sub.F and its inverse are selected such that the switching transistors Q12.sub.-1 through Q12.sub.-4 are turned on while the transistors Q11.sub.-1 through Q11.sub.-4 are turned off, the operation of the inverters illustrated in FIG. 3 will be reversed. That is, a high level of Vin.sub.2 at the input of inverter 8.sub.-4 occurring at the leading edge of the first clock pulse .phi. will be clocked in by the inverter 8.sub.-4 to produce a low level on its output V.sub.2. Further transitions of the clock pulse .phi. and its inverse will result in clocking of the pulse received originally at inverter 8.sub.-4 to the outputs of the inverters 8.sub.-4, 8.sub.-3, 8.sub.-2, 8.sub.-1, . . . . In this manner, a horizontal scanning pulse is shifted sequentially from right to left of the shift register stages formed by the inverters 8.sub.-1 through 8.sub.-4 as illustrated in FIGS. 2 and 3, thus to scan the picture elements of a selected horizontal line to form a mirror image signal.

It will be seen, therefore, that with the use of a single reversible shift register, such as that illustrated in FIGS. 2 and 3, it is possible to produce either a normal image signal or a mirror image signal with the use of a solid state imaging device. The embodiment of FIG. 2, including the image sensor portion 2, the vertical shift register 3, the image signal read circuitry, the shift register 7, the first and second groups of switch transistors, and associated circuitry, advantageously are fabricated on a single substrate. It will be appreciated that, by dispensing with the need for a second shift register, the embodiment of FIG. 2 provides an advantageously simplified horizontal scanning circuit arrangement permitting the use of a greater portion of the substrate by the image sensor portion. It will also be appreciated that one or more of the elements of the FIG. 2 embodiment may be fabricated on separate substrates while still realizing the advantage of a simplified circuit configuration.

FIG. 5 illustrates a further embodiment of a reversible shift register which may be employed in place of the shift register 7 of FIG. 2. The shift register of FIG. 5 is fabricated on the same substrate as the remainder of the device as depicted in FIG. 2. In the embodiment of FIG. 5 each of the inverters 8.sub.-1 through 8.sub.-4 is replaced by a respective one of inverters 50.sub.-1, 50.sub.-2, 50.sub.-3 and 50.sub.-4. Inverters 50.sub.-1 through 50.sub.-4 differ from inverters 8.sub.-1 through 8.sub.-4 in that each of the inverters 50.sub.-1 through 50.sub.-4 is provided with a pair of electrically common output terminals o.sub.1 and o.sub.2. It will be seen from FIG. 5 that the output terminal o.sub.1 of each of inverters 50.sub.-1 through 50.sub.-4 is positioned on the substrate to a first side of the input of the respective inverter and that the other common output terminal o.sub.2 is positioned on the substrate to a second side of the input terminal opposite the first side. As seen in FIG. 5, each of the switch transistors . . . Q11.sub.-2, Q11.sub.-3, Q11.sub.-4 . . . is coupled between the input terminal i of a respective one of the inverters 50.sub.-n (where n is an integer) and the output terminal o.sub.2 of another respective one of the inverters 50.sub.-(n-1), while each of the switching transistors . . . , Q12.sub.-1, Q12.sub.-2, Q12.sub.-3, . . . , is coupled between the output o.sub.1 of a respective one of the respective inverters 50.sub.n and the input of another respective one of the inverters 50.sub.-(n-1).

Since in the embodiment of FIG. 5, each inverter 50.sub.-n is provided with a pair of electrically common output terminals o.sub.1 and o.sub.2, only one conductive contact need be made to each output terminal. This provides the advantage in the fabrication process that double connections to each output may be avoided, so that there is no need to form conductive contact between two different conductive layers and the output, thus to reduce the number of steps required.

Referring now to FIG. 6, still another embodiment of a reversible shift register which may be utilized in place of the horizontal shift register 7 of FIG. 2 is illustrated therein. In this embodiment, the shift register of FIG. 6 is fabricated on the same substrate as the remainder of the device as depicted in FIG. 2. As shown in FIG. 6, each of the inverters 8.sub.-1 through 8.sub.-4 of FIG. 2 has been replaced by a respective inverter 70.sub.-1, 70.sub.-2, 70.sub.-3 and 70.sub.-4 arranged in succession and in that order generally along a common axis indicated as 72 in FIG. 6. Each of the inverters 70.sub.-1 through 70.sub.-4 has first and second opposed sides 74 and 75 on opposing sides of the axis 72. Each of the inverters 70.sub.-1 through 70.sub.-4 is provided with a pair of electrically common input terminals i.sub.1 and i.sub.2 and a pair of electrically common output terminals o.sub.1 and o.sub.2. The electrically common input terminals i.sub.1 and i.sub.2 of each of the inverters are positioned at respectively different opposed sides thereof on the common substrate so that the input terminals i.sub.1 and i.sub.2 are arranged diagonally of the respective inverter. Each of the electrically common output terminals o.sub.1 and o.sub.2 of each inverter is arranged on the same side thereof as a respective one of the input terminals i.sub.1 and i.sub.2, such that the output terminals o.sub.1 and o.sub.2 are arranged diagonally on respective sides of the inverter.

Each of the switching transistors . . . , Q12.sub.-1, Q12.sub.-2, Q12.sub.-3, . . . has its source-drain circuit coupled between the output o.sub.2 of a first respective one of the inverters 70.sub.-n and the input i.sub.2 of a second respective one of the inverters 70.sub.-(n-1), while each of the switching transistors . . . , Q11.sub.-2, Q11.sub.-3, Q11.sub.-4, . . . has its source-drain circuit coupled between the input i.sub.1 of a first respective one of the inverters 70.sub.-n and the output o.sub.1 of another respective one of the inverters 70.sub.-(n-1).

It will be seen that the structure of the horizontal shift register illustrated in FIG. 6 avoids the need to form double connections at any of the inputs i.sub.1 and i.sub.2 and the outputs o.sub.1 and o.sub.2, so that the process for fabricating the shift register of FIG. 6 is further simplified as compared with that of the shift register of FIG. 5.

It will be seen from the foregoing that the present invention provides a solid state imaging device and method wherein either a normal image signal or a mirror image signal may be produced with the use of a single horizontal scanning circuit possessing the capability of producing a scanning signal in a selected one of opposing directions. Accordingly, the need for two horizontal scanning circuits, as in the case of conventional devices, may be avoided with the use of the present invention, so that the circuit complexity of solid state imaging devices in accordance with the present invention is reduced as compared with conventional devices. Moreover, the present invention provides the ability to fabricate a solid state imaging device having both normal and mirror image capabilities on a single substrate such that an image sensor portion of the device may be made advantageously large, employing a relatively large number of picture elements and providing the ability to improve the resolution of the image signals produced with the use of the device.

Although specific embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.