Data Switching Device

The invention relates to a data switching device comprising external ports for connection to the exterior, switching modules having switching ports connected to the external ports by means of a connections network.

Such a device is widely used for concentrating or switching data from terminals or modems.

This type of device is required to have a certain degree of insusceptibility to failure. Thus, failure of a single module should not cause the entire device to be rendered unserviceable and thereby inflict substantial nuisance on the external subscribers connected to the device.

The international Patent Application WO 90/13957 describes a device of this type in which steps have been taken to correct for failure of one of the modules; therefore, if a module fails a replacement module is called upon.

However, the procedure adopted in this known device has some drawbacks.

It is not certain that the replacement module is in good working order when put into operation.

It is necessary to provide a connection network for this auxiliary module, which becomes more difficult as the capacity of the switching device increases.

In order to mitigate these drawbacks to a satisfactory extent the invention is characterized in that a certain number of connection ports of the modules are designated for backing-up, and connection network is adapted to connect said back-up ports to the external ports to be backed up.

The invention will now be described in more detail, by way of example, with reference to the accompanying drawings.

FIG. 1 shows the diagram of a switching device in accordance with the invention.

FIG. 2 shows the diagram of a switching module.

FIG. 3 illustrates the connection network.

The device shown in FIG. 1 comprises a certain number of switching modules M1, M2, M3, M4, MS, M6, M7, M8 and M9. Each of these modules comprises two groups of six switching ports each: A1, . . ., A6 for the first group and B1 . . ., B6 for the second group. These different groups of switching ports are connected to external ports C1 to C72 by means of interface circuits I1 to 112, which regroup 6 external ports each. These circuits enable subscriber circuits of different natures (terminals, modems . . .) to be connected to the switching ports. The (6) outputs of the interface circuits are connected to the switching ports A1, . . ., A6, B1, . . ., B6 of the modules M1 to M9 by means of a connection network shown diagrammatically in broken lines and double lines in FIG. 1.

It is to be noted that the exchange of information between modules is effected by links.

Thus, the modules

M1, M2 and M3 are interconnected by the link L123

M4, M5 and M6 are interconnected by the link LA56

M7, M8 and M9 are interconnected by the link L789

M1, M4, M7 are interconnected by the link LI47

M2, M5, M8 are interconnected by the link L258

M3, M6, M9 are interconnected by the link L369.

A connection network connects the six output ports (S1 . . ., S6) of the circuits to the switching ports of the switching modules. In FIG. 1 this network is shown simply in double lines and broken lines.

Thus, in accordance with the invention, when the device is in its correct and normal mode of operation the outputs

S1 to S6 of the circuit I1 are connected to the ports A1 to A6 of the module M1,

S1 to S6 of the circuit 12 are connected to the ports A1 to A6 of the module M2,

S1 to S6 of the circuit 13 are connected to the ports A1 to A6 of the module M3,

S1 to S6 of the circuit 14 are connected to the ports B1 to B6 of the module M3,

S1 to S6 of the circuit 15 are connected to the ports A1 to A6 of the module M4,

S1 to S6 of the circuit 16 are connected to the ports A1 to A6 of the module MS,

S1 to S6 of the circuit 17 are connected to the ports A1 to A6 of the module M6,

S1 to S6 of the circuit 18 are connected to the ports B1 to B6 of the module M6,

S1 to S6 of the circuit 19 are connected to the ports A1 to A6 of the module M7,

S1 to S6 of the circuit I10 are connected to the ports A1 to A6 of the module MS,

S1 to S6 of the circuit I11 are connected to the ports A1 to A6 of the module M9,

S1 to S6 of the circuit 112 are connected to the ports B1 to B6 of the module M9.

In the case of incorrect operation the outputs S1 to S6 of I1 may be connected to the ports B1 to B6 of M2, S1 to S6 of I2 may be connected to the ports B1 to B6 of M1, S1 to S6 of I3 may be connected to the ports B1 to B6 of M1, S1 to S6 of I4 may be connected to the pens B1 to B6 of M2.

In a similar way there are spare links for M4, MS, M6 and M7, MS, M9.

FIG. 2 is a more detailed diagram of the switching module M1, the other modules having a similar structure. Said module comprises four microprocessors .mu.P1, .mu.P2, .mu.P3 and .mu.P4 in a master-slave arrangement (.mu.P1 and .mu.P3 being the masters and .mu.P2 and .mu.P4 being the respective slaves). Preferably, these microprocessors are of the type MOTOROLA 68302. Each of these microprocessors has three communication ports used as switching ports A1 to A6 and B1 to B6. The ports A1, A2 and A3 are connected to the microprocessor .mu.P1, the ports A4, A5 and A6 to the microprocessor .mu.P2, the ports B1, B2 and B3 to the microprocessor .mu.P3, and the ports B4, B5 and B6 to the microprocessor .mu.P4. These microprocessors employ a common memory WM. This memory has been loaded with operating programs which can inter alia process the routing of the various data to said ports A1 . . ., A6, B1, . . ., B6. An arbitration circuit AR controls the access to the memory WM for the master-slave combination .mu.P1 and .mu.P2 or for the combination .mu.P3 and .mu.P4. Said arbitration circuit has been described in the Applicant's French Patent Application FR 90 11 799, filed on Sep. 25 1990. The information to be switched can also be routed to the other modules M2 . . ., M9, for example by means of the links L123 and L147. For this purpose a controller .mu.C of a type known as a transputer (for example INMOS T222) is used. A switching memory SM is used to enable the exchange of dam between the microprocessors .mu.P1, .mu.P2, .mu.P3, .mu.P4 and .mu.C. The ports of this common switching memory SM are controlled by another arbitration circuit AS.

To detect the correct operation of the module the memory WM contains a test program, which supplies a correct-operation signal. This program is mainly controlled by a master microprocessor .mu.P1, which addresses a resettable monostable MN in time intervals which are always shorter than its switching time, in such a way that in the case of correct operation the signal transmitted via a line WDG1 connected to the module M1 remains active as long as the module is in good working order.

The outputs of said monostables are thus connected to the lines WDG1 to WDG9 associated with the modules M1 to M9.

FIG. 3 illustrates the connection network. This Figure shows a single row of the device, the other rows being derived therefrom.

The connection network relating to the row comprising the modules M1, M2 and M3 basically comprises four connection circuits CX1, CX2, CX3 and CX4 connected to the interface circuits I1, I2, I3 and I4. These circuits have a port IN connected directly to the ports of the circuits I1 to I4, and two ports OUT1 and OUT2. Once the connections have been established these connection circuits axe defined by the lines WGD1, WGD2 and WGD3. The following Tables give the connections made as a function of the signals produced by these circuits. In the Tables

0 and 1 mean that the signal indicates a correct operation and an incorrect operation respectively,

X means that it is indifferent whether the value is 1 or 0,

* means that the output is in the disconnected state (3-state logic).

Note: The system has been designed to provide a back-up for one out of 3 modules in a logic unit (M1-M2-M3, M4-MS-M6, M7-M8-M9).