Method of Intelligent Computing and Neural-Like Processing of Time and Space Functions

1. A method of intelligent computing and neural-like processing of time and space functions comprising the following method steps: providing a system bus for allowing a plurality of function blocks to communicate with each other, said system bus having a control bus with a plurality of lines where signals indicative of timing, cycles, states and modes of operation can be conveyed between said function blocks, an address bus with a plurality of lines where signals indicative of an address can be conveyed between said function blocks, a data bus with a plurality of lines where signals indicative of information in digital form can be conveyed between said function blocks; providing, as one of said plurality of function blocks, a CPU having a control bus, an address bus and a data bus, each having a plurality of lines, for executing software program instructions and causing computations and sequences of events to take place and connecting said lines of CPU's control bus, said lines of CPU's address bus and said lines of CPU's data bus to the corresponding lines in said system bus, said CPU's address bus having fewer address lines than are available in said system bus; providing, as one or more of said plurality of function blocks, a plurality of memory banks each having a control bus, an address bus and a data bus, each having a plurality of lines, for storing information in digital form, one of said memory banks being memory bank 0 (zero) used to store the program instructions to be executed by said CPU, and connecting said lines of each memory bank's control bus, said lines of each memory bank's address bus and said lines of each memory bank's data bus to the corresponding lines in said system bus; providing, as one of said plurality of function blocks, a memory control function block with outputs connected to said address lines in system bus not already connected to said CPU, said lines not already connected being hereafter referred to as high-order bits, and using said high-order bits to select one of said plurality of memory banks, and in said memory control function block first storing in a latch B1 the high order address of a memory bank from which it is desired to read data, in a latch B2 the high order address of a memory bank into which it is desired to write data, and later connecting said high-order bits to the output of said latch B1 when said CPU is executing a memory read instruction, or said high-order bits to the output of said latch B2 when said CPU is executing a memory write instruction, or said high-order bits to ground in order to select said memory bank 0 (zero) during a time that said CPU is fetching a program instruction; providing, as one of said plurality of function blocks, a shared memory with two ports, port 1 and port 2, to be shared between two separate users, user 1 and user 2, with said port 1 having control, address and data terminals connected to said user 1, and said port 2 having control, address and data terminals connected to said user 2, said user 1 typically being said CPU connected through said system bus, said shared memory being shared according to a method comprising the steps of temporarily storing the address supplied by said user 1 in a latch A1 as soon as a select signal is received from the control bus of said user 1 and, if said user 1 has supplied a write request signal at or before the time of said select signal, latching in a latch DW1 the data supplied by said user 1 at the data terminals of said port 1, and then, if or when said shared memory is not already busy storing or retrieving information for said user 2, storing said data now in said latch DW1 in said shared memory at the address now contained in said latch A1, if, on the other hand, said user 1 has supplied a read request signal at or before the time of said select signal, then, if or when said shared memory is not already busy storing or retrieving information for said user 2, reading the data stored in said shared memory at the address now contained in said latch A1, storing it in a latch DR1 connected to said data terminals of said port 1 and waiting for said user 1 to read it form there, simultaneously following the same steps in regard to said user 2, substituting for said latches A1, DW1 and DR1 their equivalent latches A2, DW2 and DR2 and waiting if or when said shared memory is already busy storing or retrieving information for said user 1 and servicing both said user 1 and said user 2 during a time interval smaller than the maximum memory access times listed in the specifications of either said user 1 or said user 2, so that no wait states are ever needed for and timing never affected in either said user 1 or said user 2; providing, as one of said plurality of function blocks, a multiplexer for selectively acquiring, in random order and in real time, signals from external sources and connecting the inputs of said multiplexer to sources of said signals from external sources; providing, as one of said plurality of function blocks, an organic memory with its input connected to the output of said multiplexer for storing items of information that can be enhanced or degraded after each new access in said organic memory, and within said organic memory providing an internal random access memory RAM, having its own control, address and data terminals, for storing intermediate values, providing a first multiplier, a second multiplier and an adder, providing logic circuits for latching previous values of said intermediate values and gating new values of said intermediate values, providing means for causing a new set of signals ID, W, Q and A to be provided each time after each said new access, for generating control signals for said internal RAM and for controlling said logic circuits, connecting the output of said multiplexer to the first input of said first multiplier, connecting said signals ID, W Q and A respectively to the control input of said multiplexer, to the second input of said first multiplier, to the first input of said second multiplier and to the address terminals of said internal RAM, connecting the output of said first multiplier and the output of said second multiplier to the inputs of said adder, connecting the second input of said second multiplier and the output of said adder to the data lines of said internal RAM through said logic circuits, and for each said new access multiplying said acquired signals from external sources by said signal W indicative of a weight factor in said first multiplier to obtain a first product, multiplying a previous signal value obtained from said internal RAM at an address location indicated by said signal A by said signal Q indicative of a quality factor in a second multiplier to obtain a second product, adding said first product and said second product in said adder to obtain a sum, storing said sum back into said internal RAM at said address location A, and instead of said internal RAM, using a separate shared memory, identical to said shared memory function block described above, as the means for storing said intermediate values, connecting the control lines of said port 1 of said separate shared memory to the corresponding control lines of said system bus, the address lines of said port 1 of said separate shared memory to the corresponding address lines of said system bus connecting the data lines of said port 1 of said separate shared memory to the corresponding data lines of said system bus, and substituting the said control, address and data terminals of port 2 of said separate shared memory to the control, address and data terminals of said internal RAM.