Control System for Sensorless Brushless DC Motor

This invention relates to the controlled application of drive voltage to a brushless direct current motor and in particular to the controlled application of drive voltage to a sensorless brushless direct current motor.

Brushless direct current motors are well known in the art. The phase windings in these motors are sequentially energized at appropriate times so as to produce a rotating magnetic field relative to a permanent magnet rotor. The timing of such energization is a function of where the permanent magnetic rotor is relative to a phase winding that is to be energized. Various means have been heretofore used to sense the position of the permanent magnet rotor relative to the phase windings. These have included optical sensors and Hall effect devices which feed a position signal to switching logic that selectively switches power on and off to the respective phase windings. These sensing devices add cost to a system and may moreover require expensive hermetically sealed connecting leads. These devices and associated connecting leads can also require maintenance from time to time to assure continued proper operation. As a result of these drawbacks, attention has recently been focused on "sensorless" systems which are not premised on any direct sensing of the rotor position itself. These systems generally attempt to measure the effect of the back electromotive forces produced in the energized windings by a rotating rotor. These systems have achieved various degrees of success in accurately measuring the effect of this back electromotive force.

It is an object of the invention to provide an improved system for accurately sensing the back electromotive force (emf) voltage in a brushless direct current motor.

It is another object of the invention to provide a controlled drive system for a brushless direct current motor that is premised on an accurate sensing of the back electromotive force voltage in the motor.

The above and other objects are achieved by providing a controlled drive system for a brushless direct current motor which is premised on constructing phase to phase back emf signals representing the differences between the back electromotive force effects produced in each phase winding of the motor. These signals are constructed by individual circuits, each of which receives the voltages from two successive phase windings. These voltages are attenuated and adjusted so as to take into account the impedance effects produced by the particular phase windings. The adjustment for impedance effects includes a pair of resistance and capacitance configurations having current source circuitry associated therewith. The thus adjusted voltages in each individual circuit are applied to a differential amplifier which produces the phase to phase back emf signals between the two successive windings. The resulting phase to phase back emf signals are used to produce binary signals having logic level changes at zero crossover points in the phase to phase back emf signals. The logic level changes are preferably generated by comparator circuits which are selectively activated when zero crossover is anticipated. The resulting logic level signals are used to define well known switching signals that control when each phase winding is to be selectively energized.

Other objects and advantages of the present invention will be apparent from the following description in conjunction with the accompanying drawings in which:

FIG. 1 illustrates the controlled drive system for the phase windings of a three phase brushless direct current motor;

FIG. 2 illustrates one of three separate circuits which restore the phase to phase back electromotive force voltage of the three phase brushless direct current motor;

FIG. 3 illustrates one of two motor phase current source circuits that operate with the circuit of FIG. 2;

FIG. 4 illustrates the phase to phase signals produced by all circuits associated with the phase windings;

FIG. 5 illustrates zero crossing comparator circuitry which further processes the phase to phase signals produced by the circuits associated with the phase windings; and

FIG. 6 illustrates the signal processing by the circuitry of FIG. 5.

Referring to FIG. 1, a schematic representation of a brushless direct current motor 10 is seen to include phase windings 12, 14 and 16 each having an inductance value L associated therewith. The impedance of each phase winding also includes a resistance component having a resistance value of R. Each phase winding 12, 14 and 16 will experience a back emf voltage denoted as e.sub.1, e.sub.2, or e.sub.3 in the energized phase windings produced by the rotation of a permanent magnetic rotor (not shown). The energization of the phase windings is accomplished by timed application of the phase voltages V.sub.1, V.sub.2, V.sub.3 causing phase currents I.sub.1, I.sub.2, I.sub.3 to flow in the respective phase windings.

The phase voltages V.sub.1, V.sub.2, and V.sub.3 as well as the phase currents I.sub.1, I.sub.2, and I.sub.3 are applied to a phase to phase back emf restoring circuit 24. The restoring circuit is operative to produce gain adjusted phase to phase back emf voltages e.sub.1 -e.sub.2, e.sub.2 -e.sub.3, and e.sub.3 -e.sub.1. These signals are further processed by gated zero crossing comparator circuitry 26 which compares the phase to phase back emf voltage levels to ground just prior to zero crossover. Logic level signals equivalent to that obtained from Hall effect sensing devices are generated by the gated zero crossing comparator circuitry 26. These signals are applied to commutation logic 27 which produces commutation logic level signals q.sub.1, q.sub.2, q.sub.3, q.sub.4, q.sub.5, and q.sub.6.

The commutation logic level signals q.sub.1 through q.sub.6 are applied to a modulator 28 which also receives a current loop error signal from current control loop 29. It is to be appreciated that the commutation logic 27, the modulator 28 and the current control loop 29 are well known in the art. This circuitry is operative to produce the switching signals Q.sub.1 through Q.sub.6 which are applied to a three phase bridge driver circuit 30. The bridge driver circuit in combination with a power supply source 32 selectively applies the voltages V.sub.1, V.sub.2, and V.sub.3 to the phase windings 12, 14 and 16. The selective application is dictated by power semiconductor switches responsive to the switching signals Q.sub.1 through Q.sub.6 in a manner well known in the art. The power supply associated with the three phase bridge driver is preferably a resonant link bus providing a fifty kilohertz signal of 450 peak volts sustainable for twenty microseconds. It is to be appreciated that the invention is equally applicable to a driver using a direct current bus and pulse width modulation (PWM) control.

Top switches in the three phase bridge drive circuit 30 connect the resonant link bus 32 to the respective phase windings of the motor 10. Bottom switches associated with each winding connect respective windings back to the resonant link return bus 32. The modulator 28 produces the top switch signals Q.sub.1, Q.sub.2, and Q.sub.3 for the respective top switches directly from the commutation logic level signals q.sub.1, q.sub.2 and q.sub.3. The commutation logic 27 in combination with the modulator 28 and the current control loop 29 produces the signals Q.sub.4, Q.sub.5, and Q.sub.6 for the bottom switches. The drive signal to the three bottom switches is modulated by the current control loop error signal in order to maintain a defined current in the brushless dc motor phase windings. Logic level changes in the q.sub.1 through q.sub.6 signals occur at the zero crossover points of phase to phase back emf voltages generated by the phase to phase back emf voltage restoring circuit which will be hereinafter described in detail.

Referring to FIG. 2, a circuit 34 within the phase to phase back emf restoring voltage circuit 24 is illustrated in detail. The circuit 34 produces an output voltage equivalent to the difference between the back emf voltages e.sub.1 and e.sub.2. It is to be understood that there are two additional circuits not shown which produce output voltages equivalent to e.sub.2 -e.sub.3 and e.sub.3 -e.sub.1. The circuit 34 includes resistors 36, 38, 40, and 42 which preferably perform a fifty to one voltage attenuation of the voltages V.sub.1 and V.sub.2. The voltages V.sub.1 and V.sub.2 are the high voltage levels from the resonant link bus applied to the windings 12 and 14 respectively. The resulting attenuated voltages are furthermore each adjusted by RC configurations comprising capacitor 44 and resistor 46 for voltage V.sub.1 and capacitor 48 and resistor 50 for voltage V.sub.2. The current drawn through each RC configuration is governed by a respective current source circuit. An example of a current source circuit is shown in FIG. 3.

Referring to FIG. 3, an LEM current sensor 52 develops a signal voltage across a resistor 54 which is proportional to the measured phase current, I.sub.1. This signal voltage is applied through a resistance 56 to an operational amplifier 58 having feed back resistance 60. The resulting inverted phase current signal, -I.sub.1, preferably generates a voltage based on a ratio of amps of the current, I.sub.1, per volt to be experienced by the corresponding RC configuration of capacitor 44 and resistor 46. It is to be appreciated that the current signal produced by the circuitry of FIG. 3 could be done by alternative circuitry not necessarily using a LEM sensor. It is furthermore to be appreciated that a similar current source circuit produces a similar current effect of five amperes per volt for the current I.sub.2. This inverted current signal, -I.sub.2, is experienced by the RC configuration comprising the capacitor 48 and resistor 50.

As will be explained in detail hereinafter, each current source circuit works with its respective RC configuration in the circuit 34 to cancel or subtract out the signal component of the corresponding attenuated voltage of either V.sub.1 or V.sub.2 caused by the inductance and resistance of the phase winding for the particular V.sub.1 or V.sub.2 voltage.

The thus adjusted voltages downstream of the respective RC configurations are applied to a differential amplifier 62 in FIG. 2 having the feed back resistance 42 and the ground reference resistance 38. As will be explained in detail hereinafter, the output of the differential amplifier configuration will be equivalent to the phase to phase difference in the back emf voltages e.sub.1 and e.sub.2 in the brushless d.c. motor 10 with the exception of a fifty kilohertz noise component and a noise spike coincident with communication switching. Both of these noise components are minimal with ideal cancellation (null balance) of the signal components in V.sub.1 and V.sub.2 caused by the inductance and resistance of the respective phase winding. They increase in amplitude with deviation from null balance which is caused by changes in motor phase winding parameters. A two pole RC low pass filter 64 having a band pass of two kilohertz attenuates these noise components. These components are further filtered out by the zero crossing comparator circuitry of FIG. 5 in a manner which will be addressed hereinafter.

As has been previously noted, the output of the differential amplifier 62 will be equivalent to the phase to phase difference in the back emf voltages e.sub.1 and e.sub.2. This is accomplished by configuring the circuits of FIGS. 2 and 3 in a manner which will now be described. As has been previously noted, current source circuits such as the circuit of FIG. 3 produce a given ratio of voltage to be experienced by an associated RC configuration per amperes of current in the phase windings. This ratio is preferably five amperes of phase winding current per volt to be experienced by an RC configuration. This given ratio allows the values of capacitance and resistance for each RC configuration in FIG. 2 to be accurately calculated as will now be described. Referring to FIG. 2, the capacitors 44 and 48 are to have a capacitance value of "C" and the resistors 46 and 50 are to have resistance values of R.sub.3. The input resistors 36 and 40 are to have resistance values of R.sub.1 and the resistors 38 and 42 are to have resistance values of R.sub.2. Based on the above assigned variables, the following equation can be derived for the output voltage, V.sub.o, of the differential amplifier 62 in FIG. 2: ##EQU1## The following equation can also be written for the difference between the voltages V.sub.1 and V.sub.2 as a function of currents I.sub.1, I.sub.2 and the phase winding inductances L and resistances R in the schematic representation of the brushless d.c. motor 10 of FIG. 1: ##EQU2## This equation can be rewritten as follows: ##EQU3## By setting V.sub.o =e.sub.1 -e.sub.2 and noting the following values, one can solve for C and R.sub.3 :

500 volts at the motor =10V in circuit 34

50 A at the motor =10V at circuit 34

L=3.1 mH

R=0.34 ohms

R.sub.1 =150 Kilo ohms

R.sub.2 =3 Kilo ohms

The above defines a voltage power to signal ratio of fifty (500V/10V) and a current power to signal ratio of five (50A/10V). It follows that: ##EQU4##

It is hence to be appreciated that the circuit 34 of FIG. 2 can be precisely configured to produce the phase to phase emf signal for e.sub.1 -e.sub.2.

It is to be appreciated that two similar circuits with associated current source circuits generate the phase to phase back emf signals of e.sub.2 -e.sub.3 and e.sub.3 -e.sub.1. These circuits are all within the overall phase to phase back emf restoring circuit 24. The resulting periodic signals are illustrated in FIG. 4. It is to be noted that these signals have several undesirable spikes attributable to commutation switching. These signals are applied to the gated zero crossing comparator circuitry 26 which detects the zero crossing points of each signal having the undesirable spikes.

Referring to FIG. 5, the gated zero crossing comparator circuitry 26 is illustrated in detail. This circuitry is seen to include a bank of gated comparative amplifiers 66, 68, and 70 having feedback loops which are selectively disabled by gating logic 72 in association with switching configurations 74, 76, and 78. The feedback loop of each operational amplifier is disabled prior to the zero cross over of the respective phase to phase back emf signal applied to the amplifier and again enabled after crossover. Disablement of the feedback loop for the comparative amplifier 66 occurs when the switch in the switching configuration 74 is opened. This produces a zero voltage condition at the positive input of this comparative amplifier 66. Enablement of the feedback loop occurs when the switch in the switching configuration is closed. The resistance in the feedback loop attenuates the plus or minus output of the amplifier 66 so as to produce plus or minus ten volts at its plus input. These voltage levels are greater than the e.sub.3 -e.sub.1 signal level and hence prevent a change in the comparative decision.

Referring to FIG. 6, the phase to phase back emf signal of e.sub.3 -e.sub.1 that is to be sampled for zero crossover is illustrated. This signal includes the undesirable spikes which are attributable to commutation switching. The gating signal for the switching configuration 74 associated with the operational amplifier 66 is also illustrated in FIG. 6. The gating logic signal produces gating pulses P.sub.1, P.sub.2, P.sub.3, and P.sub.4 immediately prior to zero crossover of the phase to phase back emf signal. The pulse width is preferably sixty degrees minus a five hundred microsecond period of time. As a result of these pulses, the operational amplifier 66 receives a comparator reference input signal as shown in FIG. 6 which is zero volts only during the window periods defined by the pulses and is otherwise minus ten volts during the negative voltage periods of e.sub.3 -e.sub.1 and plus ten volts during the positive voltage periods of this signal. These reference voltage levels cause the operational amplifier 66 to not respond to any non zero voltage level in the e.sub.3 -e.sub.1 signal including the denoted voltage spikes. As a result, the operational amplifier 66 produces the zero comparator output signal illustrated in FIG. 6. This signal is seen to be applied to the gating logic 72 which consists of appropriate AND and OR gates and inverters that monitor the comparator output signals of the amplifiers 66, 68 and 70. These logic elements develop sixty degree width pulses. Zero crossover decisions from the amplifiers 66, 68 and 70 also preferably trigger a multivibrator within the gating logic which develops logic pulses of five hundred microseconds. These latter pulses are used to shorten the period of each sixty degree pulse at its start. The resulting gating logic pulses such as P.sub.1, P.sub.2, P.sub.3, and P.sub.4 for the feedback circuit 74 are generated on the output line 80 in FIG. 5. Similar gating logic pulses would be produced on output lines 82 and 84 for the feedback circuits 76 and 78.

Referring again to FIG. 4, the zero comparator signal out of comparative amplifier 66 is seen to have leading and trailing edges defining zero voltage crossover points of the phase to phase back emf signal e.sub.3 -e.sub.1. It is to be noted that similar zero comparator signals are produced by the operational amplifiers 68 and 70 for the zero crossover points of the phase to phase back emf signals e.sub.2 -e.sub.3 and e.sub.1 -e.sub.2. These signals are illustrated relative to the corresponding phase to phase back emf signals in FIG. 4.

The zero comparator signals are applied to the commutation logic 27 which produces the switching logic signals q.sub.1 through q.sub.6 As can be seen in FIG. 4, the switching signals q.sub.1 and q.sub.4 are responsive to the zero comparator signal from the operational amplifier 66 whereas q.sub.2 and q.sub.5 are responsive to the zero comparator signal from the operational amplifier 70 and the switching signals q.sub.3 and q.sub.6 are responsive to the zero comparator signal from the operational amplifier 68. As has been previously discussed with regard to FIG. 1, the commutation logic signals q.sub.1 through q.sub.6 are applied to modulator 28. The modulator 28 produces the top switching signals Q.sub.1, Q.sub.2 and Q.sub.3 directly from the signals q.sub.1, q.sub.2 and q.sub.3. The commutation logic 27 in conjunction with the modulator 28 and current control loop 29 produces the bottom switching signals Q.sub.4, Q.sub.5 and Q.sub.6. The logically high portions of these signals define when a corresponding switch in the three phase bridge driver 30 is "on" so as to allow drive voltage to be appropriately applied to a particular phase winding in the brushless direct current motor 10.

It is to be appreciated that a particular embodiment of the invention has been described. Alterations, modifications, and improvements thereto will readily occur to those skilled in the art. Such alterations, modifications and improvements are intended to be part of this disclosure even though not expressly stated herein and are intended to be within the scope of the invention. Accordingly the foregoing description is by way of example only. The invention is limited only as defined in the following claims and the equivalents thereto.