Memory Device Delaying Timing of Outputting Data in a Test Mode as Compared With a Normal Operating Mode

1. Field of the Invention

The present invention relates to memory devices, and particularly to a memory device having reduced test time of memory cells in a test mode.

2. Description of the Background Art

A memory device, such as a dynamic random access memory (DRAM), is generally provided with a circuit for testing a function of each of memory cells constituting a memory cell array.

FIG. 6 is a block diagram showing one example of a conventional memory device. In FIG. 6, a memory cell array 11 comprises a multiplicity of memory cells (not shown) two-dimensionally arranged in row and column directions. Data reading circuits 1 to 4 constituting data reading means respond to a read control signal .phi..sub.R, to be described later, which is supplied from a waveform shaping circuit 9 to read simultaneously data from respective selected memory cells among the memory cells constituting memory cell array 11, amplify the read data, and then apply the amplified data to a data processing circuit 5 as data D.sub.1 to D.sub.4.

When a mode designating signal .phi..sub.T supplied from a signal source, not shown, designates a normal operation mode, data processing circuit 5 serves as a data selecting circuit, selecting any one of the data D.sub.1 to D.sub.4 in response to an address signal .phi..sub.A of four bits supplied from an address signal source, not shown, to provide the selected data as read data D.sub.R . When the mode designating signal .phi..sub.T designates a test mode, data processing circuit 5 serves as an exclusive OR (EX-OR) circuit, providing the signal D.sub.R which indicates whether all of the four data D.sub.1 to D.sub.4 are the same, or at least any one of them is different from the others. Data processing circuit 5 will be described later in detail.

The data D.sub.R provided from data processing circuit 5 is applied to a data output circuit 6. Data output circuit 6 provides the aforementioned data D.sub.R as output data D.sub.O at the timing defined by an output control signal .phi..sub.C supplied from an output control circuit 7 to supply the data D0 to the outside through an external output terminal 8. Data output circuit 6 and output control circuit 7 will be described later in detail.

A row address strobe (RAS) signal supplied from a signal source, not shown, is applied to a timing generating circuit 10, which generates a predetermined timing signal .phi..sub.R ' synchronized with the RAS signal to apply the same to waveform shaping circuit 9.

Waveform shaping circuit 9 comprising two stages of inverters (not shown) applies waveform shaping to the above mentioned timing signal .phi..sub.R ' to generate the read control signal .phi..sub.R and apply the same to output control circuit 7, as well as to data reading circuits 1 to 4 as described above. Output control circuit 7 generates the above mentioned output control signal .phi..sub.C based on the read control signal .phi..sub.R.

FIGS. 7, 8 and 9 are schematic diagrams showing examples of the structures of data processing circuit 5, data output circuit 6 and output control circuit 7, respectively, and FIGS. 10 and 11 are waveform diagrams showing the operation of the conventional memory device shown in FIG. 6. Referring to FIGS. 6 to 11, the operation of the conventional memory device will be hereinafter described in detail.

In the normal operation mode, the mode designating signal .phi..sub.T is assumed to be at a low (L) level. Therefore, in FIG. 7, a switching transistor 57 of a switching circuit 82 in data processing circuit 5 is turned off in response to the signal .phi..sub.T, while a switching transistor 58 of switching circuit 82 is turned on in response to an inverted signal of the signal .phi..sub.T by an inverter 59.

Also, in the normal operation mode, four bits (.phi..sub.A1, .phi..sub.A2, .phi..sub.A3, .phi..sub.A4) of the address signal .phi..sub.A are applied to the control inputs of switching transistors 51 to 54 of a selecting circuit 81, respectively, so that only one of them is turned on. Accordingly, only one data, among the four input data D.sub.1 to D.sub.4, corresponding to the switching transistor which is turned on is provided as read data D.sub.R through the corresponding transistor and transistor 58 of switching circuit 82.

In the test mode, on the other hand, the mode designating signal .phi..sub.T is assumed to be at a high (H) level. Therefore, in FIG. 7, switching transistor 57 of switching circuit 82 in data processing circuit 5 is turned on in response to the signal .phi..sub.T, while switching transistor 58 of switching circuit 82 is turned off in response to an inverted signal of the signal .phi..sub.T by inverter 59.

In the test mode, the address signal .phi..sub.A for selecting read data is invalid, and the above described data selection is not carried out. Instead, the four data D.sub.1 to D.sub.4 are exclusive-ORed by an EX-OR gate 55 in a logic operation circuit 83, and the result is provided as the read data D.sub.R through an inverter 56 and transistor 57. As a result, when all of the four data D.sub.1 to D.sub.4 read from the memory cell array coincide with each other, the read data D.sub.R at an H level is provided, and in the other cases the read data D.sub.R at an L level is provided.

The output control signal .phi..sub.C supplied from output control circuit 7 comprising two stage of inverters 71 and 72, as shown in FIG. 9, is a control signal which is inactive at an L level, and is assumed to be in the inactive state during a period corresponding to read data of a so-called invalid address (invalid data) in memory cell array 11, based on the read control signal .phi..sub.R synchronized with the RAS signal.

Referring to FIG. 10 in which the operation in the normal operation mode is shown, the read data D.sub.R (FIG. 10(b)) is invalid data corresponding to an invalid address during the period the output control signal .phi..sub.C (FIG. 10 (a)) is at an L level, so that the output D.sub.O (FIG. 10 (c)) of data output circuit 6 comprising an NAND gate 61 and an inverter 62, as shown in FIG. 8, is rendered in a high impedance state (Hi-Z).

With the address of read data changing from invalid to valid, the read data D.sub.R changes from invalid data to valid data (FIG. 10 (b)). The control signal .phi..sub.C (FIG. 10 (a)) rises to an H level at a timing defined in advance with respect to the timing of this change to be in the active state. As a result, data output circuit 6 of FIG. 8 provides the data D.sub.R supplied from data processing circuit 5 to the outside as the output data D.sub.O (FIG. 10 (c)).

Referring to FIG. 11 in which the operation in the test mode is shown, the basic operation is the same as that shown in FIG. 10, except that the read data D.sub.R (FIG. 11(b)) is not the one selected from the four data D.sub.1 to D.sub.4, but the one obtained by EX-OR processing of the data D.sub.1 to D.sub.4. However, it should be noticed that time required for the EX-OR operation causes delay by a certain time period in the timing of change of the read data D.sub.R from invalid to valid in the test mode, with respect to the timing of such change of the read data D.sub.R in the nominal operation mode.

Also in the test mode, the output control signal .phi..sub.C has the same waveform as in the normal operation mode, as shown by the solid line (FIG. 11 (a)), which results in partial output of the invalid data D.sub.R as the output data D.sub.O from data output circuit 6, as shown by the solid line of FIG. 11 (c).

The following problem arises in the conventional memory device having the structure described above. In the test mode, when the read data D.sub.R changes from invalid to valid at the timing shogun in FIG. 11 (b) (the timing later than that in the normal operation mode of FIG. 10 (b)), a part of the invalid data is once provided as the data output D.sub.O as shown by the solid line of FIG. 11 (c) because the waveform of the output control signal .phi..sub.C is fixed. Time required for change of the once-provided invalid data to valid data causes significant delay in output of the original valid data. Therefore, in the conventional memory device described above, the problem arises that access time of valid data in the test mode becomes long, resulting in a long time required for a function test of the memory device.

Accordingly, if the timing when the output control signal .phi..sub.C rises is delayed as shown by the broken line of FIG. 11 (a), the output data D.sub.0 in the high impedance state changes to valid data at the timing shown by the broken line of FIG. 11 (c), so that the output of invalid data as described above can be prevented, and consequently delay in the timing of reading in the test mode can be reduced.

The delay in rise of the output control signal .phi..sub.C, however, causes delay in rise of the signal .phi..sub.C also in the normal operation mode, so that the problem arises that high speed operation of the memory device in the normal operation mode is difficult to be performed.

One object of the present invention is to provide a memory device having reduced time required for a function test of memory cells in the test mode without impairing high speed operation in the normal operation mode.

The memory device in accordance with the present invention includes a plurality of memory cells, data reading circuits, a data processing circuit and a control circuit. The data reading circuits read data from respective ones of memory cells selected from the plurality of memory cells. The data processing circuit applies a predetermined logical operation processing to the data read from said selected memory cells to convert the read data into data the number of which is less than that of the read data in the test mode. The control circuit delays the timing of output of the data from the data processing circuit in the test mode as compared with that in the normal operation mode.

In accordance with another aspect of the present invention, the memory device includes a memory cell array, data reading circuits, a mode designating signal supplying source, a data processing circuit and an output control circuit. The memory cell array includes a plurality of memory cells. The data reading circuits read data from respective ones of memory cells selected from the memory cell array. The mode designating signal supplying source supplies a mode designating signal for designating either a normal operation mode or a test mode. The data processing circuit, when the mode designating signal indicates the normal operation mode, selects at least one data from the data read from the selected memory cells to provide the selected data, and when the mode designating signal indicates the test mode, applies a predetermined logical operation processing to the data read from said selected memory cells with a certain delay time period to convert the read data into data the number of which is less than that of the read data to provide the converted data. The output control circuit, when the mode designating signal indicates the normal operation mode, provides an output data from the data processing circuit at a predetermined timing, and when the mode designating signal indicates the test mode, provides an output data from the data processing circuit at a timing delayed by said certain delay time period from said predetermined timing.

In the memory device according to the present invention, the timing of data output from the data processing circuit in the test mode is delayed from that in the normal operation, thereby preventing output of invalid data to the outside, and consequently advancing timing at which valid data is provided to the outside.

Additionally, in the memory device according to the present invention, the timing of data output from the data processing circuit in the test mode is delayed by a certain time required for the data processing circuit to perform logical operation, allowing reduction of access time in the test mode.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram showing a memory device according to one embodiment of the present invention.

FIG. 2 is a schematic diagram showing in detail the delay circuit shown in FIG. 1.

FIG. 3 is a waveform diagram showing the operation of the delay circuit shown in FIG. 2.

FIG. 4 is a waveform diagram showing the operation of the embodiment shown in FIG. 1.

FIG. 5 is a block diagram showing a memory device according to another embodiment of the present invention.

FIG. 6 is a block diagram showing one example of a conventional memory device.

FIG. 7 is a schematic diagram showing in detail the data processing circuit shown in FIG. 6.

FIG. 8 is a schematic diagram showing in detail the data output circuit shown in FIG. 6.

FIG. 9 is a schematic diagram showing in detail the output control circuit shown in FIG. 6.

FIG. 10 is a waveform diagram showing the operation in the normal operation mode of the conventional example shown in FIG. 6.

FIG. 11 is a waveform diagram showing the operation in the test mode of the conventional example shown in FIG. 6.

An embodiment of the present invention will hereinafter be described with reference to the drawings. FIG. 1 is a block diagram showing a memory device according to one embodiment of the present invention. The embodiment shown in FIG. 1 is the same as the conventional memory device shown in FIG. 6 except the following points, and the description of the common portion is not repeated.

In the embodiment of FIG. 1, a delay circuit 12 is provided in place of waveform shaping circuit 9 of FIG. 6 between timing generating circuit 10 and output control circuit 7. Delay circuit 12 and output control circuit 7 constitute a control circuit which delays the timing when data output circuit 6 provides data from data processing circuit 5 to an output terminal 8 in the test mode, from the timing of data output to output terminal 8 in the normal operation. Delay circuit 12 has a function to delay rise of a timing signal .phi..sub.R ' in the test mode in response to a mode designating signal .phi..sub.T from a signal source, not shown, and specifically has the structure shown in FIG. 2, for example. FIG. 3 is a waveform diagram schematically showing the operation of delay circuit 12 shown in FIG. 2.

In the normal operation where the mode designating signal .phi..sub.T (FIG. 3 (a)) is at an L level, the signal .phi..sub.T is inverted to an H level by an inverter 121 to be continuously applied to one input of an NOR gate 122. To the other input of NOR gate 122 the signal .phi..sub.R ' (FIG. 3 (b)) from timing generating circuit 10 is applied, and NOR gate 122 generates a signal which is always at an L level in the normal operation mode.

The signal at an L level is inverted through an inverter circuit 123 including three stages of inverters to be continuously applied as a signal at an H level to one input of an NAND gate 124. To the other input of NAND gate 124 the timing signal .phi..sub.R ' is directly applied. As a result, an inverted signal of the signal .phi..sub.R ' is obtained from NAND gate 124, which is further inverted by an inverter 125 and provided as a read control signal .phi..sub.R (FIG. 3 (c)). Specifically, as shown in the left half of the waveform diagram of FIG. 3, delay operation by delay circuit 12 is not performed in the normal operation mode where the mode designating signal .phi..sub.T is at an L level, resulting in the timing signal .phi..sub.R ' being provided as it is, as the read control signal .phi..sub.R.

In the test mode where the mode designated signal .phi..sub.T (FIG. 3 (a)) is at an H level, the signal .phi..sub.T is inverted to an L level by inverter 121 to be continuously applied to one input of NOR gate 122. As a result, NOR gate 122 serves as an inverter inverting the timing signal .phi..sub.R ' applied to the other input thereof. Inverters 121 and 122 correspond to waveform shaping circuit 9 in the conventional example of FIG. 6.

More specifically, if the timing signal .phi..sub.R ' is at an L level when the signal .phi..sub.T is at an H level (FIG. 3 (b)), both inputs of NOR gate 122 are at an L level, so that the output of NOR gate 122 is brought into an H level. The output at an H level is inverted to an L level by inverter circuit 123 to be applied to one input of NAND gate 124. Since the signal .phi..sub.R ' at the other input of NAND gate 124 is also at an L level, the output of NAND gate 124 is brought into an H level, which is inverted by inverter 125 to be provided as the read control signal .phi..sub.R ' at an L level (FIG. 3 (c)).

If the timing signal .phi..sub.R ' to an H level when the signal .phi..sub.T is at an H level (FIG. 3 (b)), the output of NOR gate 122 changes from an H level to an L level simultaneously. The change in the output of NOR gate 122 is transmitted to one input of NAND gate 124 with a delay of certain time period by inverter circuit 123.

When the signal .phi..sub.R ' changes to an H level, the other input of NAND gate 124 also changes to an H level, while transmission of the change to one input of NAND gate 124 is delayed as described above, whereby the output of NAND gate 124 remains at an H level during the certain time period (delay time period). When the certain delay time period described above has passed after the change of .phi..sub.R ', the situation is achieved wherein two inputs of NAND gate 124 are both at an H level, changing the output of NAND gate 124 to an L level. This change is inverted to a change to an H level by inverter 125, and provided as the read control signal .phi..sub.R.

That is, as shown in the right half of the waveform diagram in FIG. 3, in the test mode where the mode designating signal .phi..sub.T is at an H level, rise of the timing signal .phi..sub.R ' to an H level is delayed by a certain time period by delay circuit 12 as shown by the solid line of FIG. 3 (c), and provided as the read control signal .phi..sub.R.

When the signal .phi..sub.R ', further changes to an L level, the other input of NAND gate 124 is immediately brought into an H level, so that the output of NAND gate 124 is brought into H level simultaneously. This change is inverted to change to an L level by inverter 125. Specifically, in the test mode, the read control signal .phi..sub.R falls simultaneously with fall of the timing signal .phi..sub.R ' (FIG. 3 (b) and (c)).

FIG. 4 is a waveform diagram showing the whole operation of the embodiment shown in FIG. 1. The operation in the normal operation mode of the embodiment in FIG. 1 is the same as that of the conventional example, because the timing signal .phi..sub.R applied to output control circuit 7 is a signal at the same timing as that of the timing signal .phi..sub.R in the conventional example described in conjunction with FIGS. 6 and 10. Therefore, the description thereof is not repeated, and only the operation in the test mode will be described.

In the test mode, four data D.sub.1 and D.sub.4 are read from memory cell array 11 as in the normal operation, to be subjected to EX-OR operation by EX-OR circuit 55 (FIG. 7). Since the EX-OR operation requires a certain time period, the timing when read data D.sub.R (FIG. 4 (c)) changes from invalid to valid in the test mode will be delayed by the certain time period from the timing in the normal operation mode.

In accordance with this embodiment, therefore, the timing of activation of the read control signal .phi..sub.R is delayed by the certain time period in the test mode (the solid line in FIG. 4 (a)) from the normal timing (the broken line in FIG. 4 (a)), whereby the output control signal .phi..sub.C provided from output control circuit 7 is also delayed by the certain time period (the solid line in FIG. 4 (b)) from the normal operation (the broken line in FIG. 4 (b)). Accordingly, partial output of invalid data (the broken line in FIG. 4 (d)) is not provided from data output circuit 6, unlike in the conventional example, so that only valid data alone is provided as the output data D.sub.O (the solid line in FIG. 4 (d)).

Specifically, according to this embodiment, as can be seen from FIG. 4, the read control signal .phi..sub.R is delayed by a certain time period to prevent partial output of invalid data in comparison with the delay time period of output of valid data caused by partial output of invalid data in the case where the read control signal .phi..sub.R is not delayed. In other words, since a longer time period than the delay time period by the data processing circuit is required for changing invalid data into valid data after the invalid data has once been provided, delay of the timing of the output control signal by the above described delay time period results in the timing of output valid data being advanced. Consequently, access time in the test mode, that is, time required for a function test of the memory device can be reduced.

Although the case is described in the aforementioned embodiment, in which one selected data D.sub.R is provided out of the four data D.sub.1 to D.sub.4 in the normal operation mode and one EX-ORed data D.sub.R is provided in the test mode, the number of the data is not limited to the case in this embodiment. The present invention is applicable to a case where the number of output data is less than that of data read from the memory cell array; for example, a case where one output data is provided out of eight data read from the memory cell array, or where two output data are provided out of eight data read from the memory cell array.

FIG. 5 is a block diagram showing the embodiment in which two output data are provided out of eight data read from the memory cell array. In this embodiment, four data D.sub.1a to D.sub.4a read from memory cell array 11 by data reading circuits 1a to 4a are processed in one data processing circuit 5a, while four data D.sub.1b to D.sub.4b read from memory cell array 11 by data reading circuits 1b to 4b are processed in the other data processing circuit 5b. Data processing circuits 5a and 5b are assumed to have the same structure as data processing circuit 5 shown in FIG. 7. Data processing circuits 5a and 5b are operated by an address signal .phi..sub.A and a mode designating signal .phi..sub.T commonly applied thereto.

Read data D.sub.Ra provided from data processing circuit 5a is applied to a data output circuit 6a and provided as output data D.sub.Oa through a terminal 8a, while read data D.sub.Rb provided from data processing circuit 5b is applied to a data output circuit 6b and provided as output data D.sub.Ob at a terminal 8b. Data output circuits 6a and 6b are assumed to have the same structure as data output circuit 6 shown in FIG. 8. The other structure and operation thereof is the same as in the embodiment of FIG. 1.

Even when two output data are obtained in parallel out of eight read data, common control over the timing of respective data output in the test mode by a single delay circuit 12 will thus prevent output of invalid data in respective outputs, whereby access time of valid data can be reduced.

As described above, according to the embodiment of the present invention, an output control circuit is provided which delays the timing of data output from data processing circuit in the test mode from that in the normal operation mode, thereby preventing output of invalid data to the outside in the test mode, and thus enabling timing of output of valid data to the outside to be advanced, and reduction of access time in the test mode.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.