Reference Potential Generating Circuit

The present invention relates to a reference potential generating circuit, and more particularly to a reference potential generating circuit for use in a semiconductor integrated circuit such as a memory of the type used by internally dropping a power supply voltage externally supplied.

In recent years, for purposes of reducing power consumption and enhancing high integration density in a semiconductor integrated circuit such as a semiconductor memory device, there is an increase in use of an arrangement in which an externally supplied power voltage is dropped within a chip and a reference potential thus generated is used as a power source.

An example of a conventional reference potential generating circuit of the kind to which the present invention relates is shown in FIG. 1A. In the reference potential generating circuit shown in FIG. 1A, a threshold potential difference .DELTA.V.sub.TP between two P-channel MOS field effect transistors (hereinafter referred to as "PMOS transistors") whose threshold voltages are different from each other is produced by a .DELTA.V.sub.TP potential generating circuit 1. The potential V.sub.3 (=.DELTA.V.sub.TP) which is produced by the .DELTA.V.sub.TP potential generating circuit 1 is input to a comparator 2. An output terminal 3 of the reference potential generating circuit is driven by a PMOS transistor Q.sub.3 which receives at its gate an output from the comparator 2. The reference potential V.sub.REF which is output from the output terminal 3 is expressed as follows:

wherein the resistance values of a resistor R.sub.1 and a resistor R.sub.2 are R.sub.1 (.OMEGA.) and R.sub.2 (.OMEGA.), respectively.

FIG. 1B is a circuit diagram showing an example of the .DELTA.V.sub.TP potential generating circuit 1. In the .DELTA.V.sub.TP potential generating circuit 1 shown in FIG. 1B, there are three PMOS transistors Q.sub.10, Q.sub.11 and Q.sub.12 which are connected in series between a power supply terminal 4 and a ground terminal 5 and which produce a voltage whose potential is lower than the power supply voltage V.sub.CC by two times the threshold voltage .vertline.V.sub.TP .vertline. of the PMOS transistor. The potential thus produced is input to the gates of three PMOS transistors Q.sub.13, Q.sub.16 and Q.sub.20 which have the same operating capacity. Since the gate potentials of the PMOS transistors Q.sub.13, Q.sub.16 and Q.sub.20 are the same, the source-drain currents are the same respectively.

Further, as to an N-channel MOS field effect transistor (hereinafter referred to as "NMOS transistor") Q.sub.21 which is provided in series with the PMOS transistor Q.sub.20 and an NMOS transistor Q.sub.19 since these transistors are made to have the same operating capacity and have gates connected with each other, the respective source-drain currents coincide with each other.

That is, the source-drain currents all coincide among the PMOS transistor Q.sub.14 which is connected in series with the PMOS transistor Q.sub.13 and other PM0S transistors including the PMOS transistor Q.sub.17 connected in series with the PMOS transistor Q.sub.16 namely, the PMOS transistors Q.sub.13, Q.sub.14, Q.sub.16, Q.sub.17 and Q.sub.20 as well as the NMOS transistors Q.sub.19 and Q.sub.21.

In the above circuit configuration, the value of the threshold voltage of the PMOS transistor Q.sub.14 is made to be larger than that of the threshold voltage of the other PMOS transistors. Then, when the power supply voltage V.sub.CC becomes larger than the threshold voltage of the PMOS transistor Q.sub.14, the output voltage V.sub.3 of the .DELTA.V.sub.TP potential generating circuit 1 results in

with the .DELTA.V.sub.TP being the potential difference between the threshold voltage of the transistor Q.sub.14 and that of the transistor Q.sub.17.

Next, to facilitate the related explanation to be made later, consideration is now given to the relation between the power supply voltage V.sub.CC and the reference potential V.sub.REF in the reference potential generating circuit having the .DELTA.V.sub.TP potential generating circuit 1 described above. In the graph shown in FIG. 2, the solid line shows the relation between the power supply voltage V.sub.CC and the reference potential V.sub.REF in the case where the threshold voltages -V.sub.TP14, =-V.sub.TP17 of the PM0S transistors Q.sub.14, Q.sub.17 are -V.sub.TP14 =-1.50 (V) and -V.sub.TP17 =-0.75 (V), respectively, and R.sub.1 :R.sub.2 =2.55:0.75.

In light of FIGS. 1A, 1B and FIG. 2, it is noted that the power supply voltage V.sub.CC starts to rise from 0 (V) and, upon reaching 0.75 (V), causes the PMOS transistors Q.sub.13, Q.sub.16 and Q.sub.20 to start flowing their source-drain currents whereby the output potential V.sub.3 starts to rise. Subsequently, the power supply voltage V.sub.CC rises further and, upon reaching 1.50 (V), causes the PMOS transistor Q.sub.14 to start flowing its source-drain current and the output potential results in V.sub.3 =.DELTA.V.sub.TP =0.75 (V). Further, when the power supply voltage V.sub.CC reaches or becomes larger than the voltage which is determined by the equation (1) given above, the voltage being {(R.sub.1 +R.sub.2)/R.sub.2 }V.sub.3 =}(2.55+0.75)/0.75}.times.0.75 =3.3 (V), then the reference potential V.sub.REF becomes stable at V.sub.REF =3.3 (V).

As explained above, the conventional reference potential generating circuit is so arranged that the threshold voltage difference of the PMOS transistors having threshold voltages different from each other is differentially amplified by the comparator to obtain the reference potential.

Therefore, from the stand point of signal/noise (S/N) ratio. It is desirable that the threshold potential difference .DELTA.V.sub.TP be made large and the amplification factor be made small. However, since the threshold voltages of the PMOS transistors are determined by their structural and manufacturing conditions, there is a limit in the threshold potential differences which are obtainable therefrom.

As an alternative approach for obtaining a large threshold potential difference, a method available is to make a circuitry modification to such .DELTA.V.sub.TP potential generating circuit as shown in FIG. 1B. That is, whereas, in the above .DELTA.V.sub.TP potential generating circuit, the threshold voltage difference is derived from a threshold voltage difference of the PMOS transistors Q.sub.14 and Q.sub.17 and the output voltage obtained is .DELTA.V.sub.TP =(V.sub.TP14 -V.sub.TP17), these PMOS transistors may be stacked in a plurality thereof which result in a threshold voltage difference of n(V.sub.TP14 -V.sub.TP17) wherein "n" represents the stack number of the PMOS transistors.

With the conventional reference potential generating circuit. When the threshold voltage difference is made large as explained above, there is a problem in that the circuit after the power being switched on may not operate properly until the power supply voltage becomes stable at a predetermined value. This problem is explained hereinafter.

It is now assumed that the .DELTA.V.sub.TP potential generating circuit in this example is one in which the PMOS transistors for determining threshold voltage differences are stacked in two. Such .DELTA.V.sub.TP potential generating circuit (hereinafter referred to as "2.DELTA.V.sub.TP potential generating circuit") is shown in a circuit diagram of FIG. 3. As shown therein, the difference in this 2.DELTA.V.sub.TP potential generating circuit from the .DELTA.V.sub.TP potential generating circuit shown in FIG. 1B is the arrangement wherein a PMOS transistor Q.sub.15 is connected between the PMOS transistor Q.sub.14 and the ground terminal 5 and also a PMOS transistor Q.sub.18 is connected in series with the PMOS transistor Q.sub.17.

In this 2.DELTA.V.sub.TP potential generating circuit, the source-drain currents of all of the PMOS transistors Q.sub.13, Q.sub.16 and Q.sub.20 and the NMOS transistors Q.sub.19 and Q.sub.21 are the same as in the previously described .DELTA.V.sub.TP potential generating circuit. Further, once the power supply voltage exceeds a certain value, the output potential V.sub.3 becomes V.sub.3 =V.sub.TP14 =V.sub.TP 15-V.sub.TP17 -V.sub.TP18 (V) with the threshold voltages of the PMOS transistors Q.sub.14, Q.sub.15, Q.sub.17 and Q.sub.18 being -V.sub.TP14, -V.sub.TP15, -V.sub.TP17 and -V.sub.TP18, respectively.

When the 2.DELTA.V.sub.TP potential generating circuit as described above is used, the relation between the output potential of the reference potential generating circuit and the power supply voltage V.sub.CC will be as shown in a dotted line in the graph of FIG. 2. In this case, in the arrangements shown in FIG. 1A and FIG. 3, the threshold voltage of each of the PMOS transistors Q.sub.12, Q.sub.14 and Q.sub.15 is made -1.50 (V) and that of each of the other PMOS transistors is made -0.75 (V). This means that .DELTA.V.sub.TP =0.75 (V). Also, the ratio between the resistance value R.sub.1 and that of R.sub.2 is R.sub.1 :R.sub.2 =1.8: 1.5. The reason that the threshold voltage of the PMOS transistor Q.sub.12 is made large is for making the power consumption small.

With reference to FIG. 1A, FIG. 2 and FIG. 3, the reference potential V.sub.REF at the output terminal 3 which is driven by the 2.DELTA.V.sub.TP potential generating circuit starts to rise when the magnitude of the threshold voltage of the PMOS transistor Q.sub.12 and that of the power supply voltage V.sub.CC become the same (i.e., V.sub.CC =1.5V). When the power supply voltage V.sub.CC becomes equal to the sum value (=3.0 V) of the threshold voltages of the PMOS transistors Q.sub.14 and Q.sub.15, respectively, the output potential V.sub.3 becomes V.sub.3 = 2.DELTA.V.sub.TP =1.5 (V). Thereafter, the power supply voltage V.sub.CC further rises and, when it reaches or exceeds a value (=3.3V) which is determined by {(R.sub.1 +R.sub.2)/R.sub.2 }V.sub.3 ={(1.8+1.5)/1.5}.times.1.5, the potential at the output terminal 3 becomes constant at V.sub.REF =3.3 (V).

Here, the relation between the power supply voltage V.sub.CC and the reference potential V.sub.REF of the output when the power supply voltage V.sub.CC is 3.0 (V) or below is V.sub.REF =2 (V.sub.CC -1.50) (V).

The above relation indicates that, when the time period in which the power supply voltage V.sub.CC rises immediately after the power supply is switched to an on-state from an off-state is considered, the potential difference between the output reference potential V.sub.REF and the power supply voltage V.sub.CC, which develops in the 2.DELTA.V.sub. TP potential generating circuit during that time period is, as apparent from FIG. 2, larger than that when the .DELTA.V.sub.TP potential generating circuit is used. This means that to make the threshold voltage difference large by employing the 2.DELTA.V.sub.TP potential generating circuit is effective in relation to the S/N ratio but results in a disadvantage in the point of ensuring the stable operation of other circuits during the period in which the power supply voltage becomes stable upon the switching-on of the power supply.

It is, therefore, an object of the present invention to overcome the problems existing in the conventional reference potential generating circuit and to provide an improved reference potential generating circuit which has an excellent capability of ensuring the stable operation of other circuits immediately after the switching-on of the power supply and which produces a reference potential that has a good S/N ratio and is stable when the power supply voltage reaches or becomes above the target output potential.

According to an aspect of the invention, there is provided a reference potential generating circuit of a type in which a reference potential is obtained by amplifying a threshold voltage difference of a plurality of MOS field effect transistors which have different threshold voltages, comprising a reference potential driver circuit which, during the period in which a power supply potential externally supplied is lower than a predetermined target value of the reference potential, drives an output terminal for producing a potential corresponding to the power supply potential supplied externally.

The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention explained with reference to the accompanying drawings, in which:

FIG. 1A is a circuit diagram showing a conventional reference potential generating circuit;

FIG. 1B is a circuit diagram showing a .DELTA.V.sub.TP potential generating circuit in the circuit shown in FIG. 1A;

FIG. 2 is a graph showing the relation between the reference potential and the power supply voltage for explaining performance of the conventional reference potential generating circuit;

FIG. 3 is a circuit diagram showing a 2.DELTA.V.sub.TP potential generating circuit used in the conventional potential generating circuit and in the circuit of the first embodiment according to the invention;

FIG. 4 is a circuit diagram showing a reference potential generating circuit of a first embodiment according to the invention;

FIG. 5 is a circuit diagram showing a 2.vertline.V.sub.TP .vertline. potential generating circuit in the circuit shown in FIG. 4;

FIG. 6A is a graph showing the relation between the potential of a power-on signal and the power supply voltage in the circuit shown in FIG. 4;

FIG. 6B is a graph showing the relation between the reference potential of the output and the power supply voltage for explaining performance of the circuit of the first embodiment according to the invention; and

FIG. 7 is a circuit diagram showing a circuit which produces a potential V.sub.2 and a potential V.sub.3.

Now, preferred embodiments of the invention will be explained with reference to the accompanying drawings. Throughout the following explanation, similar reference symbols or numerals refer to the same or similar elements in all figures of the drawings.

FIG. 4 is a circuit diagram showing a reference potential generating circuit of a first embodiment according to the invention. As shown therein, the circuit includes a power-on signal generating circuit 6 which detects the switching-on of the power supply; a first driver PMOS transistor Q.sub.1 which receives a power-on signal at its gate and drives an output terminal 3; a 2.vertline.V.sub.TP .vertline. potential generating circuit 7 which produces a potential V.sub.2 that is two times the threshold .vertline.V.sub.TP .vertline. of the PMOS transistor; a comparator 8 which compares the potential V.sub.2 and the reference potential V.sub.REF of the output; a second driver PMOS transistor Q.sub.2 which receives an output of the comparator 8 and drives the output terminal 3; a 2.DELTA.V.sub.TP potential generating circuit 9 which produces a potential V.sub.3 that is two times the threshold difference .DELTA.V.sub.TP between the two PMOS transistors having threshold voltages different from each other; resistors R.sub.1 and R.sub.2 which are connected in series between the output terminal 3 and the ground terminal 5 and which have resistance values R.sub.1 (.OMEGA.) and R.sub.2 (.OMEGA.), respectively; a comparator 2 which compares the potential V.sub.3 and a potential at the series connection point A between the resistor R.sub.1 and the resistor R.sub.2, and a third driver PMOS transistor Q.sub.3 which receives an output of the comparator 2 at its gate and drives the output terminal 3.

In this embodiment, the 2.DELTA.V.sub.TP generating circuit 9 employed is the same circuit as that shown as the conventional circuit in FIG. 3.

Next, the 2.vertline.V.sub.TP .vertline. potential generating circuit 7 is explained with reference to FIG. 5. In the circuit shown in FIG. 5, three PMOS transistors Q.sub.4, Q.sub.5 and Q.sub.6 connected in series between the power supply terminal 4 and the ground terminal 5 produce a potential which is lower by two times the threshold voltage of the PMOS transistor than the power supply voltage V.sub.CC. The potential thus produced is inputted to the gate of the PMOS transistor Q.sub.7 and the potential V.sub.2 is outputted from the drain of this PMOS transistor Q.sub.7. The potential V.sub.2 is a potential which is higher than the ground potential by the magnitude corresponding to the sum of the threshold voltages of the two PMOS transistors Q.sub.8 and Q.sub.9.

In this embodiment, the power-on signal P.sub.ON produced by the power-on signal generating circuit 6 depends on the power supply voltage V.sub.CC as shown in FIG. 6A. That is, in the graph of FIG. 6A, until the power supply voltage V.sub.CC reaches a predetermined value (in this example, 2.0V) immediately after the power is switched on, the potential of the power-on signal P.sub.ON remains 0 (V). Then, at and above the predetermined value (=2V) of the power supply voltage V.sub.CC the potential of the power-on signal P.sub.ON becomes the same as that of the power supply voltage V.sub.CC.

Hereunder, the operation of the circuit according to the above first embodiment will be explained in detail. FIG. 6B is a graph showing the relation between the reference potential V.sub.REF and the power supply voltage V.sub.CC.

In the 2.vertline.V.sub.TP .vertline. potential generating circuit 7 shown in FIG. 5, the threshold voltage of each of the PMOS transistors Q.sub.6, Q.sub.8 and Q.sub.9 is -1.50 (V) and that of other PMOS transistors is -0.75 (V). Also, in the 2.DELTA.V.sub.TP potential generating circuit 9 shown in FIG. 3, the threshold voltage of each of the PMOS transistors Q.sub.12, Q.sub.14 and Q.sub.15 is -1.50 (V) and that of other PMOS transistors is -0.75 (V) in the same way as above, and the resistance ratio between the resistor R.sub.1 and the resistor R.sub.2 is R.sub.1 :R.sub.1 =1.8: 1.5. In this embodiment, the reason that the threshold voltage of the PMOS transistors Q.sub.6 and Q.sub.12 is made large is for reducing the current consumption involved.

First, consideration is given to the case wherein, in the present embodiment, the output terminal 3 is driven only by the third driver PMOS transistor Q.sub.3 by the potential V.sub.3 from the 2.DELTA.V.sub.TP potential generating circuit 9.

In this case, the relation between the reference potential V.sub.REF and the power supply voltage V.sub.CC is as shown in a solid line in the graph of FIG. 6B. Specifically, as already explained, when the power supply voltage V.sub.CC is 3.0 V or below, the reference potential V.sub.REF is:

so that the value of the reference potential V.sub.REF becomes considerably lower than the value of the power supply voltage V.sub.CC, which results in the lack of assurance for stable operation of other related circuits when the power supply voltage is low.

The problem is overcome by the provision of the second drive by the potential V.sub.2 from the 2.vertline.V.sub.TP .vertline. potential generating circuit 7. As shown by a dotted line in the graph of FIG. 6B, the reference potential V.sub.REF of the output terminal 3 driven by the second drive is:

when the power supply voltage V.sub.CC becomes 1.5 (V) or above which is the threshold voltage of the PMOS transistor Q.sub.6 and becomes stable at

when the power supply voltage V.sub.CC rises to 3.0 (V) or above.

On the other hand, as shown by a dashed line in the graph of FIG. 6B, the potential V.sub.REF of the output terminal which receives the power-on signal P.sub.ON from the power-on signal generating circuit 6 and which is driven by the first driver PMOS Q.sub.1 is:

after the power supply voltage V.sub.CC rises from 0.75 (V), which corresponds to the threshold voltage of the PMOS transistor Q.sub.1 until the power signal P.sub.ON becomes high (in this example, until V.sub.CC becomes V.sub.CC =2 V).

In conclusion, in the reference potential generating circuit of this embodiment, when the power supply voltage V.sub.CC is in a range of 0.75 (V)<V.sub.CC <3.30 (V), the reference potential V.sub.REF of the output will be V.sub.REF =V.sub.CC, and when the power supply voltage V.sub.CC is in a range of V.sub.CC >3.30 (V), the reference potential of the output will be V.sub.REF =3.30 (V).

It can be appreciated from the foregoing that the reference potential generating circuit of this embodiment has the same capability as in the conventional circuit as to the ensuring of stable operation of other related circuits immediately after the power supply is switched on and, in addition, has excellent characteristics as to the S/N ratio after the power supply voltage has reached a predetermined value.

Next, an explanation is made of a second embodiment according to the present invention. FIG. 7 is a circuit diagram of a circuit for obtaining a potential V.sub.2 and a potential V.sub.3 according to this second embodiment. In this embodiment as shown in FIG. 7, the 2.vertline.V.sub.TP .vertline. potential generating circuit and the 2.DELTA.V.sub.TP potential generating circuit are not separately prepared and, instead, in the 2.DELTA.V.sub.TP potential generating circuit as shown in FIG. 3, a potential which is produced in the course of obtaining the potential V.sub.3 of 2.vertline.V.sub.TP .vertline. is used as 2.vertline.V.sub.TP .vertline.=V.sub.2, and this contributes to the simplification of the circuit configuration involved.

Also, in the circuit of this embodiment, the PMOS transistor Q.sub.12 shown in the circuit of FIG. 3 has been replaced by a resistor R.sub.3 so that, when the power supply voltage V.sub.CC rises to or above the threshold voltage of each of the PMOS transistors Q.sub.13, Q.sub.16 and Q.sub.20, the output termlnal 3 is driven such that a potential is caused to be equal to the power supply voltage V.sub.CC also by the second drive of the potential V.sub.2.

As explained above, the reference potential generating circuit according to the present invention is provided with a circuit which drives an output terminal in such a way that the power supply voltage and the internal reference potential are caused to be equal to each other when the power supply voltage is lower than the target value of the internal reference voltage. Thus, the circuit for setting the target value of the internal reference potential can be designed without the need of consideration as to circuit performance when the power supply voltage is low but only with the consideration as to circuit capability when the power supply voltage rises from the target value of the internal reference potential. Therefore, the present invention can provide an improved reference potential generating circuit in which the S/N ratio is good and the circuit operation is stable. This is a very significant advantage for reducing the power consumption and for increasing the integration density in semiconductor integrated circuit devices.

While the invention has been described in its preferred embodiments, it is to be understood that the words which have been used are words of description rather than limitation and that changes within the purview of the appended claims may be made without departing from the true scope and spirit of the invention in its broader aspects.