Semiconductor Device

FIG. 1 is a partially sectional perspective view showing a resin-sealed type semiconductor device for sealing a DRAM according to Embodiment I of the present invention;

FIG. 2 is a top plan view of FIG. 1;

FIG. 3 is a section taken along line I--I of FIG. 2;

FIG. 4 is a layout showing the schematic structure of the DRAM shown in FIG. 1;

FIG. 5 is an overall top plan view showing the lead frame shown in FIG. 1;

FIGS. 6 and 7 are sections showing essential portions showing the relations between the inner leads and the semiconductor chip shown in FIG. 1;

FIG. 8 is a section showing the schematic structure of the resin molding according to another embodiment of the insulator shown in FIG. 1.

FIG. 9 is a sect ion taken along line II--II of FIG. 8;

FIG. 10 is a section showing the adhered portions of the resin molding and the semiconductor chip of FIG.

FIG. 11 is an exploded assembly view showing the relations among the semiconductor chip, the insulator and the lead frame shown in FIG. 1;

FIGS. 12, 13 and 24 are diagrams for explaining the characteristics of mold resin materials;

FIGS. 15 to 19 are diagrams for explaining a package optimized for injecting the mold resin of the resin-sealed semiconductor device shown in FIG. 1 into a mold;

FIGS. 20, 21A, 21B, 22A and 22B are diagrams for explaining the schematic structure of a resin-sealed semiconductor device according to Embodiment II of the present invention and a process for fabricating the same;

FIGS. 23, 24A, 24B, 25, 26, 27, and 28 are diagrams for explaining the schematic structure of a resin-sealed semiconductor device according to Embodiment III of the present invention and a process for fabricating the same;

FIG. 29 is a partially sectional perspective view showing the schematic structure of a resin-sealed type semiconductor device according to Embodiment IV of the present invention;

FIG. 30 is a section Taken along V--V of FIG. 29 and showing the state before the resin molding;

FIG. 31 is a section showing a resin-sealed type semiconductor device according to another embodiment before the resin molding in case a flexible/fluid substance of FIG. 29 is used;

FIGS. 32 and 33 are sections showing a resin-sealed type semiconductor device according to another embodiment before the resin molding in case a flexible/fluid substance is used;

FIG. 34 is a section showing a resin-sealed type semiconductor device according to another embodiment before the resin molding in case a flexible/fluid substance is used;

FIG. 35 is a section showing the schematic section of a resin-sealed type semiconductor device according to Embodiment V of the present invention;

FIGS. 36A, 37A, 38A, 39A, 40A and 41A are top plan views taken from the opposite side to the modified principal surface of the semiconductor chip of FIG. 35;

FIGS. 36B, 37B, 38B, 398, 40B and 41B are sections taken along the transverse center lines of FIGS. 36A, 37A, 38A, 39A, 40A and 41A;

FIG. 42 is a section showing another embodiment relating to the Embodiment

FIG. 43 is a partially sectional perspective view showing the schematic structure of a resin-sealed type semiconductor device according to Embodiment VI of the present invent ion:

FIG. 44 is a section taken along line VI--VI of FIG. 43;

FIG. 45 is a partially sectional perspective view showing the schematic structure of a resin-sealed type semiconductor device modified from the Embodiment VI of the present invention;

FIG. 46 is a section taken along line VII--VII of FIG. 45;

FIG. 47 is a partially sectional perspective view showing the schematic structure of a resin-sealed type semiconductor device modified from the Embodiment VI of the present invention;

FIG. 48 is a section taken along line VIII--VIII of FIG. 47;

FIG. 49 is a partially sectional perspective view showing the schematic structure of a resin-sealed type semiconductor device according to Embodiment VII of the present invention;

FIG. 50 is a section taken along line IX--IX of FIG. 49;

FIG. 51 is a top plan view showing the layout of the element of the semiconductor chip of the Embodiment VII and the layout of the bonding pads BP;

FIG. 52 is an overall top plan view showing the lead frame of the Embodiment VII:

FIG. 53 is a top plan view showing the schematic structure of the lead frame of the resin-sealed type semiconductor device according to Embodiment VIII of the present invention;

FIGS. 54A, 54B and 54C are sections showing the semiconductor chip fixing portions of the resin-sealed type semiconductor device according to the Embodiment VIII of the present invention, respectively;

FIGS. 55, 56 and 57 are sections showing the modifications of the resin-sealed type semiconductor device according to the Embodiment VIII of the present invention before the resin molding;

FIGS. 59A, 59B, 50A, and 50B are layouts of the semiconductor chips of the resin-sealed type semiconductor device according to Embodiment IX of the present invention;

FIG. 60 is a section for explaining the package of the resin-sealed type semiconductor device according to the Embodiment IX of the present invention;

FIG. 61 is a perspective view showing the side opposed to the wiring substrate of a resin-sealed type semiconductor device according to Embodiment X;

FIG. 62 is a section taken along line XI--XI of FIG. 61;

FIG. 63 is a section showing a modification of the resin-sealed type semiconductor device of the Embodiment X;

FIGS. 64 , 65 , 66 and 67 are sections showing other modifications of the semiconductor device of the Embodiment X;

FIGS. 68 and 69 are sections showing the state in which the resin-sealed type semiconductor device of the Embodiment X is packed in the wiring substrate;

FIG. 70 is an overall perspective view showing the schematic structure of the resin-sealed type semiconductor device for sealing the DR;[M according to Embodiment XI of the present invention;

FIG. 71 is a partially sectional perspective view of FIG. 70;

FIG. 72 is a section taken along line XII--XII

FIG. 74 and showing a semiconductor device according to one embodiment of the present invention;

FIG. 73 is a partially broken section taken along line XIII--XIII of FIG. 74;

FIG. 74 is a general too plan view showing the semiconductor device;

FIG. 75 is a general top plan view of a semiconductor chip showing the circuit block of the semiconductor device:

FIG. 76 is a section taken along line XV--XV FIG. 77 and showing a semiconductor device according to another embodiment of the present invention;

FIG. 77 is a general top plan view showing the semiconductor device:

FIG. 78 is a general top plan view of a semiconductor chip showing the circuit block of the semiconductor device; and

FIG. 79 is a partially broken section showing a semiconductor device according to another embodiment of the present invention.

The present invention will be specifically described in the following in connection with the embodiments thereof with reference to the accompanying drawings.

Throughout all the drawings for explaining the embodiments , the portions having identical functions are designated at identical reference characters, and their repeated descriptions will be omitted.

A resin-sealed type semiconductor device for sealing a DRAM according to the embodiment I of the present invention is shown in FIG. [(in partially sectional perspective view), in FIG. 2 (in top plan view) and in FIG. 3 (in section taken along line I--I of FIG. 2).

As shown in FIGS. 1, 2 and 3, a DRAM (i.e., a semiconductor chip) I is sealed with an SOJ (Small Outline J-bend) type resin-sealed package 2. The DRAM 1 is made to have a large capacity of 16 (M bits).times.1 (bit) and a rectangular area of 16.48 (mm).times.8.54 (mm). This DRAM 1 is sealed with the resin-sealed package 2 of 400 (mil).

The DRAM 1 has its principal surface arranged mainly with a memory cell array and a peripheral circuit. The memory cell array is arranged in a matrix form with a plurality of memory cells (or elements) for storing information of 1 (bit), as will be described in detail hereinafter. The peripheral circuit is comprised of a direct peripheral circuit and an indirect peripheral circuit. The direct peripheral circuit is one for directly controlling the information writing and reading operations of the memory cells. This direct peripheral circuit includes a row-address decoder, a column address decoder and a sense amplifier. The indirect peripheral circuit is one for controlling the operations of the direct peripheral circuit indirectly. This indirect peripheral circuit includes a clock signal generator and a buffer.

The principal surface of the DRAM 1, i.e., the surface arranged with the memory cell array and the peripheral circuit is arranged with inner leads insulating films 4 are sandwiched between the DRAM and the inner leads 3A. The insulating films 4 are made of a resin film of polyimide or the like. The individual surfaces of the insulating films 4 at the sides of the DRAM 1 and the inner leads 3A are formed with adhesive layers. These adhesive layers are made of a resin such as a polyether amide-imide resin or an epoxy resin. The resin-sealed package 2 of this kind adopts the LOC (Lead On Chip) structure in which the inner leads 3A are arranged over the DRAM 1. The resin-sealed type package 2 adopting this LOC structure can handle the inner leads 3A freely without being restricted by the shape of the DRAM 1 so that it can seal up the DRAM 1 having a size enlarged according to the free handling. In other words, the resin-sealed package 2 adopting the LOC structure can suppress the sealing (or package) size, even if the DRAM 1 has its size enlarged according to the large capacity, thereby to enhance the packing density.

The inner leads 3A have their one-side ends made integral; with outer leads 3B. These outer leads 3B are specified with signals to be applied thereto, on the basis of the standards and are numbered. In FIG. 1, the lefthand foremost one is the 1st terminal, and the righthand foremost one is the 14terminal. The righthand rear one (the terminal number of which is shown at the inner lead JA) is the 15th terminal, and the lefthand rear one is the 28th terminal. In short, the resin-sealed type package 2 is comprised of totally 24 terminals, i.e., the 1st to 6th terminals, the 9th to 14th terminals, 15th to 20th terminals and 23th to 28th terminals.

The 1st terminal is one for a power source voltage V.sub.CC. This power source voltage V.sub.CC is at 5 (V) for operating the circuit, for example. The 2nd terminal is a data input signal terminal (D); the 3rd terminal is an idle terminal; the 4th terminal is a write enable signal terminal (W); the 5th terminal is a row address strobe signal terminal (RE); and the 6th terminal is an address signal terminal (A.sub.11).

The 9th terminal is an address signal terminal (A.sub.10); the 10th terminal is an address signal terminal (A.sub.0); the 11th terminal is an address signal terminal (A.sub.1); the 12th terminal is an address signal terminal (A.sub.2); and the 13terminal is an address signal terminal (A.sub.3) . The 14th terminal is a power source voltage V.sub.CC terminal.

The 15th terminal is a reference voltage V.sub.SS terminal. This reference vol rage V.sub.SS is at the reference Level of 0 (V) of the circuit. The 16th terminal is an address signal terminal (A.sub.4); the 17th terminal is an address signal terminal (A.sub.5); the 18th terminal is an address signal terminal (A.sub.6); the 19th terminal is an address signal terminal (A.sub.7); and the 20th terminal is an address signal terminal (A.sub.8 ) .

The 23rd terminal is an address signal terminal (A.sub.9); the 24th terminal is an idle terminal; the 25th terminal is a column address strobe signal terminal (CAB); the 26th terminal is an idle terminal; and the 27th terminal is a data output signal terminal. The 28th terminal is a reference voltage V.sub.SS terminal.

The other-side ends of the inner leads 3A are extended across the longer sides of the rectangular DRAM 1 to the center of the DRAM 1. The other ends of the inner leads 3A have their extensions connected with bonding pads (or external terminals) BP arrayed at the center of the DRAM 1 through bonding wires 5. These bonding wires 5 are made of aluminum (Al) but may be exemplified by gold (Au) wires, copper (Cu) wires or coated wires which are prepared by coating metal wires with an insulating resin. The bonding wires 5 are bonded by the method using the hot contact bonding together with the ultrasonic vibrations.

Of the inner leads 3A, The 1st and 14th (V.sub.CC) terminals 3A are made integral with each other, and their central portions of the DRAM 1 are extended in parallel with their longer sides (namely, the inner leads (V.sub.CC) 3A are called the "common inner leads" or "bus bar inner leads"). Likewise, the 15th and 28th inner lead terminals (V.sub.SS) 3A are made integral with each other and their central portions of the DRAM 1 are extended in parallel with their longer sides (namely, these inner leads (V.sub.SS) 3A are called the "common inner leads" or "bus bar inner leads"). The inner leads (V.sub.CC) 3A and the inner leads (V.sub.SS) 3A are extended in parallel in the regions which are defined by the other-side leading ends of the remaining inner leads 3A. These inner leads (V.sub.CC) 3A and inner leads (V.sub.SS) 3A are so constructed as can supply the power source voltage V.sub.CC and the reference voltage V.sub.SS in any position of the principal surface of the DRAM 1. In short, this resin-sealed type semiconductor device is constructed to absorb the power source noises easily and to speed up the operations of the DRAM 1.

The shorter side of the rectangular DRAM 1 is equipped with a chip supporting lead 3C.

The inner leads 3A, the outer leads 3B and the chip supporting lead 3C are cut from the Lead frame and are molded. This lead frame is made of a Fe-Ni alloy (containing 42 to 50 (%) of Ni) or Cu.

The DRAM 1, bonding wires 5, inner leads 3A and chip supporting lead 3C thus far described are sealed up with a mold resin 2A. In order to drop the stress, this mold resin 2A is exemplified by an epoxy resin to which are added a phenol hardener, silicone rubber and a filler. The silicone rubber has an action to drop the modulus of elasticity of the epoxy resin as well as the thermal expansion coefficient. The filler is made of balls of silicon oxide and has an action to drop the thermal expansion coefficient. On the other hand, the package 2 is formed in its predetermined position with an index ID (in the form of a notch located at the lefthand end of FIGS. 1 and 2).

Next, the structure of the DRAM 1 sealed up with the resin-sealed type package 2 is schematically shown in FIG. 4 (in a chip layout).

As shown in FIG. 4, the DRAM 1 is arranged substantially all over its surface with a memory cell array (MA) 11. The DRAM 1 of the present embodiment I has its memory cell array coarsely divided into four memory cell arrays 11A to 11D. although not limitative thereto. As shown in FIG. 4, the two memory cell arrays 11A and 11B are arranged at the upper side of the DRAM 1 whereas the two memory cell arrays 11C and 11D are arranged at the Lower side. Each of these four memory cell arrays 11A to 11D is finely divided into sixteen memory cell arrays (MA) 11. In short, the DRAM 1 is arranged with sixty four memory cell arrays 11. Each of these sixty four memory cell arrays 11 has a capacity of 256 (Kbits).

Between every two of the sixty four memory cell arrays 11 of the DRAM 1, there is arranged a sense amplifier (SA) 13. This sense amplifier 13 is constructed of a complementary MOSFET (i.e., CMOS). Of the four memory cell arrays of the DRAM 1, each of the memory cell arrays 11A and lib is arranged at its lower end with a column address decoder (YDEC) 12. Likewise, each of the memory cell arrays 11C and 11D is arranged at its upper end with a column address decoder (YDEC) 12.

Of the four memory cell arrays of the DRAM 1, each of the memory cell arrays 11A and 11C is arranged at its righthand end with a word driver (WD) 14, a row address decoder (XDEC) 15 and a unit mat controller 16, which are disposed sequentially from the left to the right. Likewise, each of the memory cell arrays 11A and 11C is arranged at its lefthand end with a word driver (WD) 14, a row address decoder (XDEC) 15 and a unit mat controller 16, which are disposed sequentially from the right to the left.

Each of the sense amplifier 13, column address decoder 12, word driver 14 and row address decoder 15 described above constitutes of the direct one of the peripheral circuits of the DRAM 1. This direct peripheral circuit is one for directly controlling the memory cells which are arranged in the finely-divided memory cell arrays 11.

Peripheral circuits 17 and external terminals BP are interposed between the memory cell arrays 11A and 11B and between the memory cell arrays 11C and 11D of the four memory cell arrays of the DRAM 1. The peripheral circuits 17 are exemplified by a main amplifier 1701, an output buffer 1702, a substrate potential generator (i.e., V.sub.BB generator) 1703 and a power source circuit 1704. Totally sixteen main amplifiers 1701 are arranged four at a unit. Totally four output buffers 1702 are arranged.

The external terminals BP are arranged at the center of the DRAM 1 because the aforementioned resin-sealed type semiconductor device 2 is constructed to have the LOC structure so that the inner leads 3A are extended to the center of the DRAM 1. The external terminals 1 are arranged from the upper to the lower sides of the DRAM 1 within the regions which are defined by the memory cell arrays 11A and 11C, and 11B and 11D. The signals to be fed to the bonding pads (or external terminals) BP have been described before in connection with the resin-sealed type semiconductor device 2 shown in FIG. 4, and their descriptions will be omitted here. Since the inner leads 3A fed with the reference voltage (V.sub.SS) and the power source voltage (V.sub.CC)are basically extended from the upper to the lower sides on the surface of the DRAM 1, the DRAM 1 is arranged the plural external terminals BP for the reference voltage (V.sub.SS) and the power source voltage (V.sub.CC) in the extending direction thereof. In short, the DRAM 1 is so constructed as can feed the reference voltage (V.sub.SS ) and the power source voltage (V.sub.CC) sufficiently. The data input signals (D), the data output signals (Q), the address signals (A.sub.0 to A.sub.11), the clock signals and the control signals are concentrated at the center of the DRAM 1.

Peripheral circuits 18 are interposed between the memory cell arrays 11A and 11C and the memory cell arrays 11B and 11D of the four memory cell arrays of the DRAM 1. These peripheral circuits 18 are exemplified at a lefthand side by a row address strobe (RE) circuit 1801, a write enable (W) circuit 1802, a data input buffer 1803, a power source voltage (V.sub.CC) limitter 1804, an X-address driver (or logical stage) 1805, an X-redundancy circuit 1806, And an X-address buffer 1807. The righthand side of the peripheral circuits are exemplified by a column address strobe (CE) circuit 1808, a test circuit 1809, a VDL limitter 1801, a Y-address driver (or logical stage) 1811, a Y-redundancy circuit 1812 and a Y-address buffer 1813. The center of the peripheral circuits 18 are exemplified by a Y-address driver (or drive stage) 1814, an X-address driver (or drive stage) 1815 and a mat selection signal circuit (or drive stage) 1816.

The aforementioned peripheral circuits 17 and 18 (and 16) are used as the indirect peripheral circuits of the DRAM 1.

Next, the detail of the lead frame will be described in the following.

The lead frame of the present embodiment I is equipped, as shown in FIG. 1 and FIG. 5 (i.e., in a top plan view of the whole lead frame), with twenty signal inner leads 3A.sub.1 and two common inner leads 3A.sub.2. The inner leads 3A (i.e., the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2) are so stepped that the gap between the portions of the inner leads 3A to be adhered to the insulating films (or members) 4 and the semiconductor chip 1 is larger than the gap between the portion to be bonded to the insulatiing films (or members) 4 and the semiconductor chip 1. Thanks to the stepped structure of the inner leads 3A, the stray capacity between the semiconductor chip and the leads is smaller than that of the prior art. As a result, it is possible to improve the signal transmission rate and to drop the electrical noises.

On the other hand, the adhesion between the principal surface of the semiconductor chip 1 and the insulating film 4 and the adhesion between the insulating film 4 and the inner leads 3A are effected by means of an adhesive 7, as shown in FIG. 6. Alternatively, this adhesive 7 may be used not for adhering the principal surface of the semiconductor chip 1 and the insulating film 4 but only for adhering the insulating film 4 and the inner leads 3A, as shown in FIG. 7.

Incidentally, the inner leads 3A can attain the aforementioned effects even if they are applied to a package having none of the common inner leads 3A.sub.2.

In the predetermined positions of the lead frame, as shown in FIGS. 1 and 5, there are disposed the chip supporting (or suspending) leads 3C which are not supplied with any electric power but for adhering and fixing the principal surface of the semiconductor chip 1.

Since the semiconductor chip 1 firmly fixed by adhering and fixing the principal surface of the semiconductor chip 1 by means of the suspending leads 3C of no power supply, it is possible to improve the reliability and the moisture resistance of the semiconductor device.

Next, the detail of the insulating films 4 will be described in the following.

The area of the principal surface of the semiconductor chip 1 occupied by the insulating films 4 is at most one half of the area of the semiconductor chip 1. Since the area of the insulating films 4 is thus made at most one half of the area of the semiconductor chip 1, the moisture absorption by the insulating films 4 can be reduced to prevent the influences of both the heat during the fellow and the steam which is generated by the heat of the temperature cycle. In other words, the package can be prevented from being cracked to improve the reliability of the semiconductor device.

Since, moreover, the stray capacity between the semiconductor chip 1 and the leads is smaller than that of the prior art, it is possible to improve the signal transmission rate and to drop the electrical noises.

Still moreover, the aforementioned effects can be made more prominent by practically minimizing the area of bonding the insulating films 4 and the principal surface of the semiconductor chip 1. On the other hand, the leakage between the leads can be reduced because only the portions of the inner leads to be adhered to the semiconductor chip are covered with the insulating films.

On the other hand, the insulating films 4 over the principal surface of the semiconductor chip 1 may be modified, as shown in FIG. 8, such that a resin molding 6 containing portions of the aforementioned inner leads 3A is used to sufficiently enlarge the gap between the semiconductor chip 1 and the inner leads 3A thereby to reduce the stray capacity between the semiconductor chip 1 and the inner leads 3A.

Thus, the resin molding 6 and the mold resin 2A can be made of the material of good affinity so that the leads can be less peeled at their interfaces.

The adhesion between the resin molding 6 and the semiconductor chip 1 may be effected by means of the adhesive 7, as shown in FIG 10.

The base material of the insulating films 4 and the resin molding 6 are molded of: one or more major components, which are selected from an epoxy resin, a BT (Bismaleimide Triazine) resin, a phenol resin (i.e., resol) and a polyimide resin (e.g., aromatic polyimide or cycloaliphatic polyimide containing ether and carbonyl bonds; and an inorganic filler, a fibrous hardener or various additives, if necessary.

Other examples of the base material of the insulating films 4 and the resin molding 6 are molded of: a major component of a thermoplastic resin such as cycloaliphatic polyimide, polyester, polysulfone, aromatic polyether amide, aromatic polyester imide, polyphenylene sulfide, polyamide-imide or its modified, polyether etherketone, polyether sulfone or polyether amide-imide; and an inorganic filler, fibers and an additive, if necessary.

On the other hand, the adhesive for bonding the insulating films 4 or the resin molding 6 to the inner leads 3A and the semiconductor chip 1 can be selected from one of: an epoxy resin, a BT resin, a phenol resin (or resol), a polyimide resin, an isomelanic resin and a silicon resin: a thermoset resin modified from the above-specified resins: and a thermoplastic resin such as aromatic polyether amide, polyether-ether-ketone, polysulfone, aromatic polyester imide, polyester or cycloaliphatic polyimide.

In the face mounting package type integrated circuit such as SOJ, the vapor-phase reflow solder method or the infrared fellow solder method is used in the case of solder packaging on a printed circuit board (PCB). In this case, however, the moisture in the package may be gasified and expanded by the fellow temperature (at 215.degree. to 260.degree. C.) to peel the adhesion at the chip interface until the the internal pressure in the peeled faces is raised to crack the sealing resin.

Since the LOC structure is made by bonding the inner leads 3A and the semiconductor chip 1 with the insulating films 4 and the resin molding 6, the aforementioned phenomena are accelerated by the moisture absorption of the insulating films 4 or the resin molding 6. For avoiding the phenomena, therefore, it is effective to reduce the volume of the insulating films 4 thereby to decrease the moisture absorption.

The lower limit of the bonded area is that which can stand the external force to be borne at the wire bonding step and the resin molding step.

Here will be examined the physical properties of the insulator of the aforementioned insulating films 4 or the resin molding 6.

The bonding insulating material to be used between the inner leads 3A and the semiconductor chip 1 of the semiconductor device having the LOC structure or the COL (Chip On Lead) structure has to satisfy at least two of the following seven conditions:

(1) The saturated moisture adsorption is equal to lower than that of the sealing resin;

This condition is effective for preventing the resin cracking when in the vapor-phase solder (VPS).

(2) The dielectric constant is 4.0 or less (at 10.sup.3 Hz at the room temperature to 200.degree. C.);

This condition reduces the stray capacity between the inner leads and the semiconductor chip.

(3) The Barcol hardness at 200.degree. C. is 20 or more;

This condition improves the wire bonding properties.

(4) The contents of U and Th are 1 ppb or less, and the amount of an soluble halogen extracted at 120.degree. C. for 100 hours is 10 ppm or less;

This condition is effective for preventing the soft error and improving the moisture resistance.

(5) The contactness of the semiconductor chip and the inner leads is excellent;

This condition can retain the wire bonding property, improve the moisture resistance and prevent the current leakage between the inner leads.

(6) The linear thermal expansion coefficient is 20.times.10.sup.-6 /.degree.C. or less; and

This condition reduces the warpage, in case an insulating material is bonded to the inner leads 3A, to improve the bondability to the semiconductor chip at a subsequent step.

(7) The glass transition temperature Tg is 220.degree. C. or higher in the case of the thermoplastic resin.

This condition is effective for preventing the material having a glass transition temperature Tg of 220.degree. C. or lower from being thermally deformed at a high temperature (e.g., 215.degree. C.) in the reflow solder to cause a package cracking.

Examples of the material satisfying at least two of the above-specified conditions will be described in the following.

For example, the film prepared by the following process was the material satisfying the above conditions except the item (1): The process includes: the step of roughing the two sides of the Kapton 500 H (i.e., the polyimide film produced by Du Pont or Upilex S (i.e., the polyimide film produced by Ube Kosan K.K.); and the step of coating the two sides with 25 microns of polyether amide having a glass transition temperature Tg of 220 or more.

The conditions (1) to (6) were satisfied by the film which was prepared by applying and drying an adhesive of 10 to 25 microns, which was selected from an epoxy resin, a resol resin, an isomelamine resin, a phenol-modified epoxy resin and an epoxy-modified polyimide resin, to the two sides of a bismaleimide, epoxy or epoxy-modified polyimide film of 125 microns reinforced by highly pure quartz fibers or aramid fibers.

On the other hand, the following film satisfied all the conditions and was featured in its low moisture absorptibity and small dielectric constant. The film was prepared: by improving the adhesiveness of the two sides of the film of Teflon PFA (i.e., a copolymer of tetraethylenefluoride-perfluoroalkoxy, Teflon EFP (i.e., a copolymer of tetraethylenefluoride-perhexapropylenefluoride) or Kapton F-type (i.e., the product of Toray and Du Pont, the Kapton film having its two sides thinly coated with the Teflon FEP); and by coating the two sides of the film with an adhesive selected from an epoxy resin, a resol resin, an aromatic polyetheramide resin and a polyimide precursor.

Here will be described the method of adhering and fixing the semiconductor chip 1 to the lead frame 3 through the insulating films 4 by means of an adhesive.

As shown in FIG. 11 (in a development presenting the relations among the lead frame 3, the insulating films 4 and the semiconductor chip 1), the insulating films 4 are divided and adhered to those portions of the principal surface of the semiconductor chip 1, which face the signal inner leads 3A, the common inner leads 3A.sub.2 and the suspending leads 3C, by means of the adhesive 7 (shown in FIGS. 1 and 6). Next, as shown in FIG. 6, the signal inner leads 3A.sub.1, the common inner leads 3A.sub.2 and the suspending leads 3C of the lead frame 3 are fixedly adhered by the adhesive 7.

The examples of the mold resin material (or resin) will be described in the following:

(1) The resin composite to be used is exemplified by a thermoset resin which is blended with 70 wt. % of a substantially spherical inorganic filler having a particle size distribution of 0.1 to 100 microns, an average particle diameter of 5 to 20 microns and the maximum packing density of 0.8 or more.

The resin component in this case may be any of epoxy, resol or polyimide.

Thus, the mold resin material using the above-specified spherical inorganic filler (e.g., molten silica) can be more blended to reduce the thermal expansion of the material, because its material exerts little influence upon the molten viscosity and fluidicity, as shown in FIG. 12 (plotting the relation between the packing density of the filter and the fluidicity). By increasing the loading of the filler, moreover, the thermal stress of the moldings can be dropped, as shown in FIG. 13 (plotting the relations between the amount of synthesis of the filler and the physical properties of the moldings) and FIG. 14 (plotting the relations between the amount of synthesis of the filler and the thermal stress). This improves the cracking resistance to a satisfactory extent.

Thus, it is possible to prevent a semiconductor device, which has an especially fine structure such as the LOC structure, from being deformed or damaged when it is to be molded.

(2) The resin compound to be used is comprised mainly of at least one kind of a highly pure phenol-set type epoxy resin, resol type phenol resin and bismaleimide resin.

The properties of the set device in case the an unpurified resol resin is used are highly different from those of the purified device such that the bulk resistance is different by three figures or more at 140.degree. C., as tabulated in Table 1 (as located at the tailing page). Because of much ionic impurity, moreover, there is also found a large difference in the electric conductivity of an extracted liquid.

The purified resol resin was produced, for example, by pouring 500 g of phenol, 550 g of formalin of 30% and 5 g of zinc acetate as a hardener into a flask, by gradually agitating and hearing them, and by circulating and heating them at 90.degree. C. for 60 minutes. After this, the inside of flask was evacuated to 20 mmHg, and the condensate and the unreacted components were removed. Next, 300 g of acetone was added to dissolve the reaction products, and pure water was added to agitate them violently at 50.degree. C. for 30 minutes. After the cooling, the upper water layer was removed, and the reaction products were dissolved again into 300 g of acetone. Pure water was then added to agitate them violently at 50.degree. C. for 30 minutes. After the cooling, the upper water layer was removed. These cleaning operations were repeated five times. After each of these cleaning operations, the reaction products were partially taken out and dried at 40.degree. C. for 48 hours under an evacuated condition, to produce six kinds of resol type phenol resins of different degrees of refinement.

The number of purifications, the melting point and the setting characteristics of the resol type phenol resins thus obtained; the analytical results of the hydrogen ion density (pH) and the electric conductivity of the extracted water, which was prepared by adding 50 g of pure water to 50 g of resol type phenol resins and by heating them at 120.degree. C. for 120 hours; and the analytical result of the concentration of the ionic impurities extracted are tabulated in Table 2 (as located at the trailing page).

As is apparent from Table 2, the resol type phenol resins having been subjected to the aforementioned cleaning operations by five times contain remarkably small amounts of ion impurities.

Thus, the purifications can improve the reliabilities in the moisture resistance of the moldings, the hot lifetime of the Au/Al bonded portions, and the characteristics of the element due to the differences in the aforementioned characteristics.

(3) The molding resin materials to be used are exemplified by the examples 2 and 3 of Table 1, which are comprised mainly of resol type phenol resins or bismaleimide resins of high purity and whose moldings have a bending strength of 3 kgf/mm.sup.2 or more at 215.degree. C.

Since the sealing materials using the resol type phenol resins or polyimide resins of high purity have a high heat resistance for their moldings and a bending strength of 3 kgf/mm.sup.2 or more at 215.degree. C., the reflow resistance (to package cracking) in the case of the packages having absorbed the moisture and the reliabilites in the moisture resistance and the resistance to the thermal shocks are improved to a remarkably statisfactory extent.

(4) The inorganic filler to be blended into the base resin of the foregoing item (2) or (3) is exemplified by any of the Examples 1, 2 and 3 of Table 1, i.e., substantially spherical silica having a particle size distribution of 0.1 to 100 microns, an average particle diameter of 5 to 20 microns and the maximum packing density of 0.8 or more.

Thus, the sealing material using the above-specified spherical molten silica has its molten viscosity and fluidicity little influenced so that its thermal expansion can be dropped by increasing its loading. As a result, the package acquires an excellent cracking resistance in addition to the effects of he foregoing item (2) and (3).

(5) The aforementioned resin sealing material is a composite, in which more than 67.5 vol. % of spherical molten silica having a particle size distribution of 0.1 to 100 microns, an average particle diameter of 5 to 20 microns and the maximum packing density of 0.8 or more is blended as the inorganic filler and whose molding has a linear expansion coefficient of 1.4.times.10.sup.-5 /.degree.C. This resin sealing material is exemplified by any of the Examples 1, 2 and 3 of Table 1.

Thus, the aforementioned effects of the spherical molten silica can be further improved.

(6) The aforementioned resin sealing material is exemplified by any of the Examples 1, 2 and 3 of Table 1, which is mixed with ion exchange water in an amount of ten times, and which has a pH of 3 to 7 as an extracted liquid, in case it is extracted at 120.degree. C. for 100 hours, an electric conductivity of 200 .mu.S/m and an extraction of ions of halogen, ammonia and metal of 10 ppm or less.

Next, one experiment of the Examples (1) to (6) of the above-specified resin sealing materials will be described in the following.

Three kinds of resin sealing materials were prepared, as tabulated in Table 1: by using an epoxy resin, the resol type phenol resin (Example 1) and the bismaleimide resin (Example 2) as the base material of the thermoset resin; by adding to this base material both spherical molten silica having a particle size distribution of 0.1 to 100 microns, an average particle diameter of 5 to 20 microns and the maximum packing density of 0.90 as a filler and a variety of additives; by melting and heating the resultant mixture by a biaxial roll heated to about 80.degree. C.; and by pulverizing the heated mixture after a cooling.

Next, each of the resin sealing materials was used to mold a semiconductor device having the LOC structure shown in FIG. 1, i.e., the 16MDRAM by a transfer molding machine. The molding process was accomplished at a mold temperature of 180.degree. C., under a transfer pressure of 70 kgf/mm.sup.2 and for a molding period of 90 secs.

According to the experiment, the following effects could be attained:

(1) The sealing material, which used as its filler the substantially spherical molten silica having the particle size distribution of 0.1 to 100 microns, the average particle diameter of 5 to 20 microns and the maximum packing density of 0.8 or more, had a lower molten viscosity and a better fluidicity than the sealing material using the generally existing square molten silica. During the molding process, therefore, the bonding wires 5 of Au or the like and the lead frame 3 were neither deformed nor forced the semiconductor chip 1 to flow. In addition, the sealing material could fill up the narrow gap of the package excellently.

(2) The above-specified spherical molten silica exerted little influence upon the molten viscosity and fluidicity of the material so that the thermal expansion of the material could be dropped by increasing the loading of the molten silica. As a result, the package had an excellent cracking resistance. (3) In the semiconductor sealing material of the prior art, the epoxy resin was used, but the phenol resin or the polyimide resin were not used, because the latter two resins contained many ionic impurities and were inferior in electric characteristics and the reliablities in the moisture resistance so that they were not practical. If, however, a highly pure resol type phenol resin or polyimide resin was used, satisfactory reliabilities could be attained.

(4) The sealing resin using the highly pure resol type phenol resin or polyimide resin had a high heat resistance in its molding form and was excellent especially in the mechanical strength at a high temperature. As a result, the sealing resin was remarkably excellent either in the reflow resistance (to package cracking) in case the package absorbed moisture or in the reliabilities in the moisture resistance and the resistance to the thermal shocks after reflow.

Here will be described means for preventing formation of voids and bending and charge shortage of the bonding wires when the resin sealing material is to be poured into a mold.

As shown in FIG. 1, the plural inner leads 3A are adhered to the principal surface of the semiconductor chip 1 through the insulating films 4 for electrically insulating them from the semiconductor chip 1, by means of the adhesive 7. The inner leads 3A and the semiconductor chip 1 are electrically connected through the bonding wires 5 and are sealed up with the resin, thus producing the 16MDRAM. In this 16MDRAM, as shown in FIG. 15 (presenting the section of an essential portion of FIG. 1), the package structure is made such that the distance H.sub.1 between the portion of the inner leads 3A adhered to the semiconductor chip 1 and the outer wall of the package 2 is larger than the distance H.sub.2 between the side of the semiconductor chip opposite to the circuit-formed side and the outer wall of the package.

Thanks to this package structure, as shown in FIG. 16 (presenting the section of a model of FIG. 15), FIG. 17 (presenting the section taken along line III--III of FIG. 16) and FIG. 18 (presenting the section taken along line IV--IV of FIG. 16), the relations among the depths h.sub.31 and h.sub.32 of flow paths of the upper portions of the inner leads 3A, the depth h.sub.2 of an intermediate portion between the inner leads 3A and the semiconductor chip 1, and the depth h.sub.1 of a flow path of the lower portion of the semiconductor chip 1 are expressed by the following Equations:

and

wherein:

h.sub.c : Cavity depth;

t.sub.c : Chip thickness;

t.sub.f : Lead frame thickness;

W.sub.c : Cavity width; and

W.sub.f : Length of the lead frame floating from the chip.

The above-specified Equations are graphically plotted in FIG. 19.

Thus, the resin flow passage of the package 2 is divided into three: the upper flow path of the inner leads 3A; the intermediate flow path between the inner leads 3A and the semiconductor chip 1; and the lower flow path of the semiconductor chip 1. The individual flow path depths and the resin flow path structures are so set as to equalize the average resin flow speeds in the individual flow paths. As a result, the average resin flow speeds in the flow paths, as indicated at circled numerals 1, 2 and 3 in FIG. 17, can be equalized to prevent the generation of voids, the bending of the the bonding wires for (Au) and the packing shortage.

Since, moreover, the average flow speeds of flow paths designated at the circled numerals 1, 2 and 3 are equal, the semiconductor chip and the inner leads 3A can be prevented from being deformed so that a highly reliable package can be produced.

In the semiconductor integrated circuit device according to the Embodiment II of the present invention is constructed, as shown in FIG. 20, FIGS. 21A and 21B and FIGS. 22A and 22B, the insulating films 4 adhered to the principal surface of the semiconductor chip 1 of the foregoing Embodiment I are modified such that insulating films 4A are arranged all over or partially of those sides of the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2, which are located in the closest position to face the semiconductor chip 1.

More specifically, as shown in FIG. 20, the aforementioned insulating films 4A are placed in advance all over the most closest sides of the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 facing the principal surface of the semiconductor chip 1 and are then fixedly adhered to the semiconductor chip 1, when assembled.

The lead frame 3 thus carrying the insulating films 4A is manufactured altogether with the signal inner leads 3A.sub.1. the common inner leads 3A.sub.2 and the insulating films 4A by adhering the insulating films 4 to that whole principal surface of the thin sheet for the inner leads, which is the closest to face the semiconductor chip 1, and by shaping and cutting the insulating films 4 by a press.

Thus, the area of the insulating films 4 can be reduced. Moreover, the signal inner leads 3A.sub.1, the common inner leads 3A.sub.2 and the insulating films 4A can be held in predetermined positions. Furthermore, the signal inner leads 3A.sub.1 and the common leads 3A.sub.2 can be prevented from any leakage because no insulating film 4 is interposed inbetween.

Here, these insulating films 4 can be less influenced by the thermal stress, if divided into a plurality or four sheets, than they are adhered in a single sheet.

As shown in FIG. 21A, moreover, of the whole (back) side facing and closest to the principal surface of the semiconductor chip 1, only the side portions corresponding to the signal inner leads 3A.sub.1 and the common leads 3A.sub.2 are arranged with the insulating films 4B. Then, the area of the semiconductor chip 1 to be occupied by the insulating films 4 can be minimized.

The lead frame 3 with the insulating films 4B occupying the minimum area of the semiconductor chip 1 is prepared, as shown in FIG. 21B, by adhering four sheets of insulating films 4 having holes a in predetermined positions, to the whole sides of the signal inner leads 3A.sub.1 and the common leads 3A.sub.2 facing and closest to the principal surface of the semiconductor chip 1, and by shaping and cutting them by a press to adhere the insulating films 4B to only the positions corresponding to the bonding portions of the signal inner leads 3A.sub.1 and the common leads 3A.sub.2.

As compared with the Embodiment shown in FIG. 20, the amount of the insulating films can be made smaller to reduce the moisture absorption. Moreover, the semiconductor chip 1 can be fixed more easily with the suspending leads.

In the embodiment shown in FIG. 21A, the insulating films 4A are arranged only in the portions corresponding to the bonding portions but may be arranged partially in other portions, if necessary.

As shown in FIG. 22A, on the other hand, the insulating films 4A shown in FIG. 20 are also arranged with insulating films 4C to extend and intersect the common inner leads 3A.sub.2 and the signal inner leads 3A.sub.1.

The inner leads 3A with the insulating films 4C are prepared, as shown in FIG. 22B, by forming one sheet of insulating film 4 having holes b leaving only the portions corresponding to the signal inner leads 3A.sub.1, and by cutting the insulating film 4 along the longitudinal center line into two halves. These two insulating film halves 4C are adhered to the common inner leads 3A.sub.2 and the signal inner leads 3A.sub.1.

Thus, it is sufficient to cut the insulating film 4 in advance in the predetermined pattern to form the insulating films 4C and to adhere the insulating films 4C to the common inner leads 3A.sub.2 and the signal inner leads 3A.sub.1. As a result, the method of preparing the insulating films 4C can be facilitated. Since, moreover, the insulating films 4C are adhered to the common inner leads 3A.sub.2 and the signal inner leads 3A.sub.1, the leading ends of the signal inner leads 3A.sub.1 can be flattened to facilitate the subsequent working steps.

The adhesions between the insulating films 4C and the common inner leads 3A.sub.2 and the signal inner leads 3A.sub.1 are effected by the contact hot bonding in the case of a thermoplastic adhesive and are effected by the setting after the tack holding in the case of a thermoset adhesive.

incidentally, the insulating films 4A, 4B and 4C shown In FIGS. 20, 21A and 22A may be either wider or narrower than the inner leads.

As is now apparent from the description made above, according to the present embodiment II, the insulating films 4 to be sandwiched between the semiconductor chip 1 and the signal inner leads 3A.sub.1 and the common leads 3A.sub.2 are far less than those of the prior art so that the amount of moisture to be absorbed by the semiconductor device can be reduced even if the device is held in a wet circumstance for a long time. As a result, the vapor pressure in the semiconductor device during the solder reflow step can be dropped to provide a semiconductor device freed from the resin cracking.

In the semiconductor integrated circuit device according to the Embodiment III of the present invention, as shown in FIG. 23, the whole region of the principal surface of the semiconductor chip 1 except the bonding pads BP of the principal surface of the semiconductor chip 1 of the foregoing Embodiment I is coated with an alpha ray shielding polyimide film 8, and the principal surface of the semiconductor chip 1 is further formed with insulating films 4D on its portions go which at least the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 are to be adhered.

The alpha ray shielding polyimide film 8 has a thickness of 2.0 to 10.0 microns.

The insulating films 4D have a thickness of 75 microns or more. The resin suited for the insulating films 4D is exemplified by a thremoset resin containing a printable inorganic filler.

The area occupied by the insulating films 4D is at most one half of that of the semiconductor chip 1.

The semiconductor chip 1 is further formed with a polyimide film 9 on the side opposed to its principal surface.

With reference to FIGS. 23 and 24A (presenting the flow chart of fabrication and the sections of the individual steps), there will be described one embodiment of the method of coating the whole region of the principal surface of the semiconductor chip 1 except the bonding pads BP of the principal surface of the semiconductor chip 1 with the alpha ray shielding polyimide film 8 and forming the insulating films 4D on the principal surface of the semiconductor chip 1 on its portions to which at least the signal inner leads 3A. and the common inner leads 3A.sub.2 are to be adhered.

First of all, the alpha ray shielding polyimide film 8 is applied to the whole region of a silicon wafer 10, as shown in FIG. 25 (presenting the top plan view of the principal surface of the silicon wafer). After partially set, the polyimide film 8 is photo-etched to expose the bonding pads (or external terminals) BP to the outside (as indicated at step 101 in FIG. 24A ).

Next, a solvent-peeling type dry film A is adhered (at Step 102 ). This solvent-peeling type dry film A is exposed (at Step 103 ) to a predetermined pattern and then developed (at Step 104 ) to form a hole B.

Next, a pasty insulating material (or printing paste ) C is applied, buried with (printing) squeeze and cured (at Steps 105, 106 and 107). Then, the solvent-peeling type dry film A is peeled to form the insulating films 4D. After this, a dicing is accomplished along the solid lines over the silicon wafer 10 shown in FIG. 25, thus completing the semiconductor chip with the insulating films 4D.

Another embodiment of the method of forming the aforementioned alpha ray shielding polyimide film 8 and the insulating films 4D is shown in FIG. 24B (presenting the fabrication flow chart and the sections of he chip at the individual steps). As shown, the alpha ray shielding polyimide film 8 is applied to the whole region of the silicon wafer 10 and is photo-etched expose the bonding pads (or external terminals) BP (at Step 201 in FIG. 24B).

Next, a dry film D for solder resists is adhered (at Step 202). This solder resist dry film D is exposed (at Step 203) to a predetermined pattern and is developed (at Step 204) to form the insulating films 4D. After this, a dicing is accomplished along the solid lines of the silicon wafer 10 shown in FIG. 25 to complete the semiconductor chip with the insulating films 4D.

Incidentally, the silicon wafer 10 is not warped even if the insulating films 4D having the aforementioned thickness are prepared by the silicon wafer process, because the films 4D are formed only partially.

On the other hand, FIGS. 26 to 28 present various patterns of the insulating films 4D to be formed in the portions of the principal surface of the semiconductor chip 1, to which at least the leading ends of the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2, and the suspending leads are to be adhered.

As is now apparent from the foregoing description, according to the present Embodiment III, the whole region of the principal surface of the semiconductor chip 1 except the bonding pads (or external terminals) BP is coated with the alpha ray shielding polyimide film 8, and the principal surface of the semiconductor chip 1 is formed with the insulating films 4D at the portions to which at least the leading ends of the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 are to be adhered. As a result, the whole region of the circuit can be shielded from the alpha ray shielding polyimide film 8, and the semiconductor chip 1 can be fixedly adhered by the insulating films 4D.

Since, moreover, the insulating films 4D are formed at the portions on the principal surface of the semiconductor chip 1, to which at least the leading ends of the inner leads 3A and the suspending leads 3C are adhered, it is possible to reduce the stray capacity between the semiconductor chip 1 and the inner leads 3A.

Since, furthermore, the insulating films 4D are made of the thermoset resin containing the printable inorganic filler, they can be formed highly accurately during the wafer process.

Since, furthermore, the semiconductor chip 1 and the resin are excellently adhered by forming the polyimide film 9 on the side of the semiconductor chip 1 opposite to the principal surface, it is possible to prevent the package cracking.

Furthermore, the insulating films 4D are formed highly accurately by the batch wafer process including the steps of: adhering the solvent-peeling type dry film A to the silicon wafer 10; applying the pasty insulator (or printing paste) after the ordinary exposing and developing steps; burying it with the squeeze; heating and curing it; and peeling the solvent-peeling type dry film. Thus, it is possible to improve the productivity.

Since, furthermore, the insulating films 4D are formed only by exposing and developing the solder resist dry film D, the productivity can be further improved.

The resin-sealed type semiconductor device according to the Embodiment IV of the present invention is constructed, as shown in FIG. 29 (presenting a perspective view in partial section): such that the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 are adhered to the principal surface of the semiconductor chip 1 of the foregoing Embodiment I through the insulating films 4 for insulating them electrically from the semiconductor chip 1; and such that the signal inner leads 3A.sub.1, the common inner leads 3A.sub.2 and the semiconductor chip 1 are electrically connected through the bonding wires 5 and sealed with a mold resin 2A. The semiconductor device is further constructed, as shown in FIG. 30 (presenting a section taken along lone V--V of FIG. 29 an showing the state before molded with a resin), such that the principal surface of the semiconductor chip 1 is so partially covered with a substance 20, which is more flexible or fluid than the mold resin, as to shield all over the bonding wires 5, and such that the substance 20 is sealed up at its outer side with resin 2A.

More specifically, there is provided a dam 21 for covering all over the bonding wires 5 extending across the common inner leads 3A.sub.2 with the flexible/fluid substance 20. This substance 20 may be made of fluid silicone gel, for example, and is dropped and set on the bonding wires 5 until it is sealed with the resin by the transfer mold.

The dam 21 is made of silicone rubber containing a highly viscous silica filler.

On the other hand, the aforementioned flexible/fluid substance 20 need not always be the above-specified gel but may be exemplified by various materials such as silicone grease or rubber if it has such a flexibility or fluidicity as to deform the bonding wires 5 therein. Thus, the bonding wires 5 can freely follow the deformations, even if the principal surface of the semiconductor chip 1 is peeled to expand the steam when the package having absorbed moisture is to be subjected to the reflow soldering treatment, so that they can be prevented from being broken.

Moreover, the bonding wires 5 are suppressed from being deformed during the transfer molding of the mold resin 2A. Even if the wires 5 are extended to run across the common inner leads 3A.sub.2, the bonding wires 5 can be prevented from being deformed during the molding, from being shorted to each other or from contacting with the common inner leads 3A.sub.2.

On the other hand, the substance covering the bonding wires 5 need not be the flexible/fluid substance if it is used with a view to preventing the deformations of the bonding wires 5. The substance may be exemplified by an epoxy resin having a modulus of elasticity as high as that of the outer resin 2A transfer-molded, if it can pot the bonding wires 5 over the principal surface of the semiconductor chip 1.

In case the flexible/fluid substance 20 has a fluidicity, is viscosity has to be higher than the molten viscosity of the resin 2A in the transfer mold.

Since, moreover, the resin 2A is kept away from direct contact with the bonding wires 5 by the flexible/fluid substance 20, the bonding wires 5 are prevented from being repeatedly deformed in the temperature cycle by he relative thermal deformations between the semiconductor chip 1 and the mold resin 2A so that they are no broken by the fatigue.

In case the flexible/fluid substance 20 is used, the bonding pads BP are prevented from having their surfaces gapped by the thermal stress so that their aluiminum can be prevented from being corroded by the moisture.

FIG. 31 is a section showing the state before the resin mold showing the resin-sealed type semiconductor device according to another embodiment in case the flexible/fluid substance 20 is used.

Since the interfaces between the signal inner leads 3A.sub.1 and the resin 2A are more reluctant to be gapped than the principal surface of the semiconductor chip 1, as shown in FIG. 31, the bonding portions of the bonding wires 5 at the side of the signal inner leads 3A.sub.1 are less broken. According to this embodiment, therefore, only the (first) bonding portions liable to be broken at the semiconductor chip 1 are formed with the flexible/fluid substance 20. As a result, a break preventing effect can be attained to some extent if the bonding wires 5 can be freely deformed.

Moreover, this embodiment makes use of the common inner leads 3A.sub.2 in place of the foregoing dam 21 of FIG. 30.

Since, in the case of this embodiment, all the bonding wires 5 are not covered with he flexible/fluid substance 20, they are subjected to repeated deformations by the relative thermal deformations between the semiconductor chip 1 and the mold resin 2A, in case the package is held in the temperature cycle, so that they are more liable to be broken due to fatigue than those of the embodiment of FIG. 30.

Since, moreover, the flexible/fluid substance 20 can be made less and lower, it is possible not only to prevent the disconnections during the reflow soldering operations and the wire deformations during the transfer mold but also to thin the package as a whole thereby to improve the packing density. FIG. 32 is a section showing the state before the resin mold of the resin-sealed type semiconductor device according to another embodiment of the present invention in case the flexible/fluid substance 20 is used.

According to this embodiment, as shown in FIG. 32, all the bonding wires 5 are covered to shield all over the principal surface of the semiconductor chip 1 with the flexible/fluid substance 20.

Effects similar to those of the foregoing embodiment of FIG. 30 can be attained, and the whole region of the principal surface of the semiconductor chip 1 is covered with the flexible/fluid substance 20 so that the moisture resistance can be better improved.

Since, however, the flexible/fluid substance 20 has a large surface area, the interfaces with the mold resin 2A are gapped during the reflow soldering operation so that the upper mold resin 2A is liable to be cracked when it is exposed to a vapor pressure.

FIG. 33 is a section showing the state before the resin mold of the resin-sealed type semiconductor device of another embodiment in case the flexible/fluid substance 20 is used.

According to this embodiment, as shown in FIG. 33, all the bonding wires 5 mounted over the principal surface of the semiconductor chip 1 are covered with the substance 20 which is more flexible or fluid than the mold resin 2A.

The flexible/fluid substance 20 covering the bonding wires 5 need not be shaded to rise on the principal surface of the semiconductor chip 1 but may be applied to only the surfaces of the bonding wires 5.

In order to effect such coverage, the flexible fluid substance 20 is first diluted to a low viscosity with a solvent and is then dropped to the semiconductor chip 1 to cover the bonding wires 5. After this, the solvent is evaporated to make the coverage.

In this case the thicker layer of the flexible/fluid substance over the surfaces of the bonding wires 5 has the better effects for preventing the disconnections and the deformations of the bonding wires 5.

Thanks to this structure, the amount of the flexible/fluid substance 20 for attaining the effects similar to those of the foregoing embodiment shown in FIG. 30 can be reduced to prevent the package crack which might otherwise be caused by the vapor pressure between the flexible/fluid substance 20 and the mold resin 2A.

FIG. 34 is a section before the resin mold of the resin-sealed type semiconductor device according to another embodiment in case the flexible/fluid substance 20 is used.

According to this embodiment, as shown in FIG. 34, the bonding wires 5 are covered with the flexible/fluid substance 20, and the mold resin 2A at the side opposite to the principal surface of the semiconductor chip 1 is bored with a hole 22 to expose a portion of the semiconductor chip 1 substantially to the outside.

Here, the word "substantially imagines the inevitable existence of either a thin cover film of the mold resin 2A at the side opposite to the principal surface of the semiconductor chip or such a thin resin layer as will be easily broken in case the steam pressure is established in the package 2.

Since the moisture resistance of the bonding pads BP can be retained by the flexible/fluid substance 20 without breaking the bonding wires 5 in the temperature cycle when in the reflow soldering operations, it is not degraded even if the hole 22 is formed in the portion of the mold resin 2A.

Since, moreover, the seam generated in the package during the reflow soldering operation is released through the hole 22 to the outside, the pressure is not built up to prevent the resin cracking.

Furthermore, the side of the hole opposite to the principal surface of the semiconductor chip 1 need not be completely exposed but may be clogged with the mold resin 2A if this resin 2A can be easily cleared by the vapor pressure.

As is now apparent from the description thus far made, according to the embodiment IV, the bonding wires 5 can be prevented from being broken, even if the principal surface of the semiconductor chip 1 is peeled to expand the steam during he reflow soldering operation.

It is also possible to prevent the bonding wires 5 from being shorted during the transfer mold or from contacting with the common inner leads 3A.sub.2.

The resin cracking during the reflow soldering operation can be prevented without degrading the moisture resistance of the bonding pads BP and causing the disconnections of the bonding wires 5 in the temperature cycle.

The resin-sealed type semiconductor device according to the Embodiment V of the present invention is modified from the resin-sealed type semiconductor device of the foregoing Embodiment I such that the side of the semiconductor chip 1 opposite to the principal surface is recessed or raised at 101, i.e., formed with a round recess, as shown in FIG. 35 (presenting a ection).

The mold resin 2A is restrained on the semiconductor chip 1 by that recess 101 so that the reflow cracking can be prevented by reducing the stress which is to be established in The mold resin portions of the corners of the side of The semiconductor chip 1 opposed to the principal surface.

Here, the recess 101 may be formed by the etching or another method.

FIG. 36A (presenting a Top plan view taken from the side opposite to the principal surface of FIG. 3) and FIG. 36B (presenting section taken on the transverse center line of FIG. 36A) show a modification of the recess 101 which is formed in the side opposite to the principal surface of the semiconductor chip 1. In this modification, an annular recess 101a is formed in the side opposite to the principal surface of the semiconductor chip 1.

FIG. 37A (presenting a top plan view) and FIG. 37B (presenting a section) show another modification of the recess 101 which is formed in the side opposite to the principal surface of the semiconductor chip 1. In this modification, a square recess 101b is formed in the side opposite to the principal surface of the semiconductor chip 1.

FIG. 38A (presenting a top plan view) and FIG. 38B (presenting a side elevation) show another modification of the recess 101 which is formed in the side opposite to the principal surface of the semiconductor chip 1. in this modification, a round rise 101c is formed in the side opposite to the principal surface of the semiconductor chip 1.

FIG. 39A (presenting a top plan view) and FIG. 39B (presenting a side elevation) show another modification of the recess 101 which is formed in the side opposite to the principal surface of the semiconductor chip 1. In this modification, a square rise 101d is formed in the side opposite to the principal surface of the semiconductor chip 1.

FIG. 40A (presenting a top plan view) and FIG. 40B (presenting a side elevation) show another modification of the recess 101 which is formed in the side opposite to the principal surface of the semiconductor chip 1 In this modification, an elliptical recess 101e is formed in the side opposite to the principal surface of the semiconductor chip 1.

FIG. 41A (presenting a top plan view) and FIG. 41B (presenting a side elevation) show another modification of the recess or rise 101 which is formed in the side opposite to the principal surface of the semiconductor chip 1. In this modification, recesses or rises 101f are formed in the groove shape in the side opposite to the principal surface of the semiconductor chip 1. The grooves may take in the form of a lattice.

Since one of the recesses or rises 101a to 101f is formed in the side opposite to the principal surface of the semiconductor chip 1, as has been described above, the semiconductor chip 1 can be firmly restricted by the mold resin 2A.

It is also possible to reduce the stress which is generated in the mold resin 2A by the corner portions at the side opposite to the principal surface of the semiconductor chip 1.

FIG. 42 shows another embodiment according to the present invention and belonging to the Embodiment V. The aforementioned recess or rise is formed in the side opposite to the principal surface of the semiconductor chip 1 while leaving an silicon oxide film 102 on the side opposite to the principal surface of the semiconductor chip 1 of the Embodiment V.

Since the silicon oxide film 102 is thus left on the side opposite to the principal surface of the semiconductor chip 1, the adhesion between the silicon oxide film 102 and the mold resin 2A is so strong that the mold resin 2A can be prevented from being peeled off from the side opposite to the principal surface of the semiconductor chip 1.

Thanks to the recess or rise 101, moreover, the semiconductor chip 1 can be firmly restricted by the mold resin 2A.

The resin-sealed type semiconductor device according to the Embodiment VI of the present invention is constructed, as shown in FIG, 43 (presenting a perspective view in partial section) and FIG. 44 (presenting a section taken along line .gradient.--.gradient. of FIG. 43): such that the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 are adhered to the principal surface of the semiconductor chip 1 of the foregoing Embodiment I through the insulating films 4 for insulating them electrically from the semiconductor chip 1; and such that the signal inner leads 3A.sub.1 , the common inner leads 3A.sub.2 and the semiconductor chip 1 are electrically connected through the bonding wires 5 and sealed with a mold resin 2A. The semiconductor device is equipped at the longitudinal centers of the sides of the package 2 with radiating leads 301a which are insulated from the semiconductor chip 1 and which have their one-side ends extended to above the exothermic portions of the principal surface of the semiconductor chip 1 and their other ends extended to below the outside of the side of the package 2 opposite to the principal surface of the semiconductor chip 1.

Thus, the one-side ends of the radiating leads 301a electrically insulated from the semiconductor chip 1 are extended at the longitudinal centers of the sides of the package to above the exothermic portions of the principal surface of the semiconductor chip 1, and the other ends of the radiating leads 301a are extended to below the outside of the package 2 opposite to the principal surface of the semiconductor chip 1, so that the radiation efficiency of the exothermic portions of the semiconductor chip 1 can be improved.

FIGS. 45 (presenting a perspective view in partial section) and FIG. 46 (presenting a section taken along line VII--VII of FIG. 45) show a modification of the radiating leads 301a shown in FIG. 43. The modified radiating leads 301b have their one-side ends extended to above the exothermic portions of the principal surface of the semiconductor chip 1 and their other ends extended to above the outside of the package 2 at the side of the principal surface of the semiconductor chip 1.

The radiating leads 301b have their extensions providing the radiating plates.

Thus, at the longitudinal centers of the sides of the package, the one-side ends of the radiating leads 301b electrically insulated semiconductor chip 1 are extended to above the exothermic portions of the principal surface of the semiconductor chip 1, and the other ends of the radiating leads 301b are extended to above the outside of the package 2 at the side of the principal surface of the semiconductor chip 1, so than the radiating efficiency of the exothermic portions of the semiconductor chip 1 can be improved.

Here, the other ends of the radiating leads 301b extended to above the outside of the package 2 at the side of the principal surface of the semiconductor chip 1 may be folded to have their volumes reduced, as indicated by broken lines in FIG. 46.

On the other hand, the lead frames for the aforementioned radiating leads 301a and 301b are fabricated integrally with the signal lead frame.

FIG. 47 (presenting a perspective view in partial section) and FIG. 48 (presenting a section taken along line VIII--VIII of FIG. 48) show a modification of the Embodiment VI shown in FIG. 39. In this modification, radiating leads 301c have their one-side ends extended to the sides opposite to the exothermic portions of the principal surface of the semiconductor chip 1 and their other ends extended to below the outside of the package 2 opposite to the principal surface of the semiconductor chip 1.

Thus, at the longitudinal centers of the sides of the package, the one-side ends of he radiating Leads 301c electrically insulated from the semiconductor chip 1 are extended to the sides opposite to the exothermic portions of the principal surface of the semiconductor chip 1, and the other ends of the radiating leads 301c are extended to below the outside of the package 2 opposite to the principal surface of the semiconductor chip 1, so that the radiating efficiency of the exothermic portions of the semiconductor chip 1 can be improved.

The one-side ends of the radiating leads 301c need not always be electrically insulated from the semiconductor chip 1 by means of the insulating film.

In this case, moreover, the lead frame of the radiating leads 301c is fabricated separately of the signal lead frame.

The resin-sealed type semiconductor device according to the Embodiment VII of the present invention is constructed, as shown in FIG. 49 (presenting a perspective view in partial section) and FIG. 50 (presenting a section taken along line IX--IX of FIG. 49): such that the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 are adhered to the principal surface of the semiconductor chip 1 of the foregoing Embodiment I shown in FIG. 1 through the insulating films 4 for insulating them electrically from the semiconductor chip 1; and such that the signal inner leads 3A.sub.1, the common inner leads 3A.sub.2 and the semiconductor chip 1 are electrically connected through the bonding wires 5 and sealed with a resin. In this semiconductor device, the principal surface of the semiconductor chip 1 is arranged with the bonding pads BP which do not intersect the bonding wires 5 and the common inner leads 3A.sub.2 arranged on the principal surface.

The element layout and bonding pads BP of the semiconductor chip 1 of the present Embodiment VII are shown in FIG. 51 (presenting a layout top plan view).

Specifically, the memory array (MA) is arranged substantially all over the area of the DRAM 1. In this DRAM 1 of The present embodiment VII, the memory cell array is coarsely divided into eight memory cell arrays 11A to 11H, although not limitative thereto. As shown in FIG. 51, the four memory cell arrays 11A, 11B, 11C and 11D are arranged at the upper side of the DRAM 1, and the four memory cell arrays 11E, 11F, 11G and 11H are arranged at the lower side. Each of these eight memory cell arrays 11A to 11H is further finely divided into sixteen memory cell arrays (MA) 11. In short, the DRAM 1 is arranged with one hundred and twenty eight memory cell arrays 11E. Each of the 128 memory cell arrays 11 has a capacity of 128 [Kbits].

The sense amplifier (SA) 13 is interposed between the two of the 128 memory cell arrays 11 of the DRAM1 . The sense amplifier 13 is constructed of a complementary MOSFET (CMOS). The column address decoder (YDEC) 12 is arranged at one lower end of each of the four 11A, 11B, 11C and 11D of the eight memory cell arrays of the DRAM I . Likewise, the column address decoder (YDEC) 12 is arranged at one upper end of each of the memory cell arrays 11E, 11F, 11G and 11H.

The peripheral circuit 17 and the external terminals BP are interposed between the two 11A and 11B, the two 11C and 11D, the two 11E and 11F, and the two 11G and 11H of the eight memory cell arrays of the DRAM 1. On the other hand, the peripheral circuits 17 and the peripheral circuits 18 are disposed at the individual lower regions of the memory cell arrays 11A, 11B, 11C and 11D and at the individual upper regions of the memory cell arrays 11E, 11F, 11G and 11H. The peripheral circuits 17 are exemplified by a main amplifier, an output buffer circuit, a substrate potential generator (or V.sub.BB generator) and a power source circuit.

The peripheral circuit 18 is further exemplified by a row address strobe (RAS) circuit, a write enable (WE) circuit, a data input buffer, a V.sub.CC limitter, an X-address driver (i.e., logical stage), an X-redundancy circuit, an X-address buffer, a column address strobe (CAB) circuit, a test circuit, a VDL limitter, a Y-address driver (i.e., Logical stage), a Y-redundancy circuit, a Y-address buffer, a Y-address driver (i.e., drive stage), an X-address driver (i.e., drive stage), and a mat selecting signal circuit (i.e., drive stage) (as should be referred to FIG. 4 and its description).

Since the aforementioned resin-sealed type semiconductor device 2 is constructed to have the LOC structure and since the inner leads 3A are extended to the central portion of the DRAM 1, the external terminals BP are arranged at the central portion of the DRAM 1 and on the principal surface of the semiconductor chip 1 such that they are kept away from intersecting the bonding wires 5 and the common inner leads 3A.sub.2 arranged on the principal surface of the semiconductor chip 1.

The external terminals BP are arranged within the regions defined by the memory cell arrays 11A, 11B, 11C, 11D, 11E, 11F, 11G and 11H from the upper to the lower ends of the DRAM 1. The signals to be applied to the external terminals BP will not be described here because they have been described in connection with the resin-sealed type semiconductor device 2 shown in FIG. 1.

Since the inner leads 3A supplied with the reference voltage (V.sub.SS) and the power source voltage (V.sub.CC) are extended from the upper to the lower ends of the surface of the DRAM 1, the DRAM 1 is arranged with the plural external terminals BP for the reference voltage (V.sub.SS) and the power source voltage (V.sub.CC) in the extending direction. In short, the DRAM 1 is constructed to effect sufficient supply of the reference voltage (V.sub.SS) and the power source voltage (V.sub.CC).

As has been described above, according to the present Embodiment VII, he principal surface of the semiconductor chip 1 is arranged with the bonding pads BP which do not intersect with the bonding wires 5 and the common inner leads 3A.sub.2 arranged on the same surface. Thus, it is possible to prevent the shorting between the bonding wires 5 for connecting the signal inner leads 3A.sub.1 and the semiconductor chip 1 and the common inner leads 3A.sub.2.

Next, the lead frame will be described in detail in the following.

As shown in FIG. 52 (presenting an overall top plan view of the lead frame), the lead frame 3 of the present Embodiment VII is equipped with twenty signal inner leads 3A.sub.1 and two common inner leads 3A.sub.2. The inner leads 3A.sub.1 are stepped, as shown in FIG. 50 (presenting a section), such that the gap between their portions nearer the outer leads 3B than their portions contacting with the insulating films 4 and the semiconductor chip is larger than the gap between their portions contacting with the insulating films (or insulators) 4 and the semiconductor chip 1. By thus adopting the stepped structure in the semiconductor chip 1, the stray capacity between the semiconductor chip 1 and the signal inner leads 3A.sub.1 can be reduced to a lower level than that of the prior art to improve the signal transmission rate and to drop the electrical noises.

The present Embodiment VII is identical to the foregoing Embodiment I except the arrangement of the bonding pads BP on the principal surface of the semiconductor chip 1 and the lead frame.

Incidentally, the techniques of the foregoing Embodiments II-VI can naturally be applied to the present Embodiment VII.

The resin-sealed type semiconductor device according to the Embodiment VIII of the present invention is, as shown in FIG. 53 (plan presenting the schematic mechanism of the lead frame in Embodiment VIII) a modification of the lead frame of the foregoing Embodiment I, in which inner leads 3C.sub.1 (suspending leads) to be supplied with no power are folded to fix the side of the semiconductor chip 1 opposite to the principal surface.

As shown in FIG. 54A (presenting a section showing the semiconductor chip fixing portion) and FIG. 56 (presenting a section showing the signal inner leads and the common inner leads before the resin molding), moreover, the semiconductor chip 1 is adhered and fixed with the adhesive 7 by the suspending leads 3C.sub.1 such that the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 are arranged in floating states from the principal surface of the semiconductor chip 1.

The adhesive 7 may be any of the aforementioned adhesives such as epoxy resins or resol resins.

On the other hand, the adhesions may be effected through the insulating films 4 between the suspending leads 3C.sub.1 and the semiconductor chip 1.

In this case, the connections of the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 and the bonding pads BP of the semiconductor chip 1 by means of the bonding wires 5 are accomplished by holding the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 on the semiconductor chip I by means of a jig. If the holding jig is removed after the wire bondings, the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 are brought into the state shown in FIG. 56 by the springback effect of the suspending leads 3C.sub.1.

As shown in FIG. 54B, on the other hand, the signal inner leads 3A, and the common inner leads 3A.sub.2 may be arranged in a floating state from the principal surface of the semiconductor chip 1 (as shown in FIG. 56) by sandwiching the insulating films 4 of a predetermined thickness between the suspending leads 3C of the lead frame 3 applied to the foregoing Embodiment 1 and the principal surface of the semiconductor chip 1 and adhering them by means of the adhesive 7. In this case, the insulating films 4 ordinarily have a thickness of 150 microns but can have a larger thickness.

As shown in FIG. 55 (presenting a section showing the state before the resin molding), on the other hand, insulating plates 40 may be sandwiched between the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 and the principal surface of the semiconductor chip 1 to connect the signal inner leads 3A.sub.1, the common inner leads 3A.sub.2 and the semiconductor chip 1 electrically by the bonding wires 5 and to seal them up with the mold resin.

As shown in FIG. 57 (presenting a section showing the state before the resin molding), moreover, the insulating plate 40 may be sandwiched only between the one-side, e.g., lefthand signal inner lead 3A.sub.1 and common inner lead 3A.sub.2 and the semiconductor chip 1, whereas the righthand signal inner lead 3A.sub.1 and common inner lead 3A.sub.2 and the semiconductor chip 1 may be electrically connected through the bonding wires 5 and sealed with the mold resin such that the signal inner lead 3A.sub.1 and the common inner lead 3A.sub.2 are floating from the principal surface of the semiconductor chip 1.

In order that the signal inner leads 3A.sub.1 and the common inner leads 3A.sub.2 may be arranged in a floating state from the principal surface of the semiconductor chip 1 (as shown in FIG. 56), as shown in FIG. 54C, the suspending leads 3C.sub.1 may be deeply folded to form suspending leads 3C.sub.2 for fixedly adhering the side of the semiconductor chip 1 opposite to the principal surface. As a result, the side of the semiconductor chip 1 opposite to the principal surface is adhered and fixed by the suspension leads 3C.sub.2 so that the signal inner leads 3A.sub..sub.1 and the common inner leads 3A.sub.2 are floating from the principal surface of the semiconductor chip 1, thus eliminating the step of adhering the insulating films 4. Moreover, the semiconductor chip 1 is firmly fixed. Since no lead line is adhered to the memory cells, it is possible to reduce the breakage of the memory cells.

As has been described above, according to the present Embodiment VIII, the moisture absorption can be reduced by eliminating or minimizing the use of the insulating films 4 to make the solder reflow resistance advantageous.

In the Embodiment VIII, it is preferable to apply the alpha ray shielding polyimide film to the whole region of the principal surface of the semiconductor chip 1 except the bonding pads.

In the resin-sealed type semiconductor device according to the Embodiment IX of the present invention, as shown in FIGS. 58 and 59 (presenting layouts of the semiconductor chip), there are provided two semiconductor chips 1A and 1B which are formed in a mirror symmetry with the bonding pads BP (or solder bumps) connected with the inner leads.

In FIG. 58, the CAS0 terminals (i.e., bonding pads BP) and the CAS1 terminals (i.e., bonding pads BP) are shared, and the other terminals (i.e., bonding pads BP) are held in common. This layout doubles the capacity in the word direction.

In FIG. 59, the Do terminals and the Di terminals are shared, whereas the other terminals are held in common. This layout doubles the capacity in the bit direction.

As shown in FIG. 60 (presenting a section for explaining the package), moreover, at the sides of the individual principal surfaces of the two semiconductor chips 1A and 1B and across the inner leads 3A, these inner leads 3A and the bonding pads BP of the semiconductor chip 1 are electrically connected through the solder bumps 5C and sealed up with the mold resin.

Thus, in the two semiconductor chips 1A and 1B formed in the mirror symmetry with the inner leads 3A and the bonding pads BP, the inner leads 3A and the bonding pads BP of the semiconductor chip 1 are electrically connected at the sides of the individual principal surfaces and across the inner leads 3A through the solder bumps 5C and sealed up with the mold resin so that an element having a twice capacity can be packaged without changing the contour of the package 2.

In the resin-sealed type semiconductor device according to the Embodiment X of the present invention, as shown in FIG. 61 (presenting a perspective view taken from the side opposed to the wiring substrate of the resin-sealed type semiconductor device of the Embodiment X) and FIG. 62 (presenting a section taken along line XI--XI of FIG. 61), the package 2 of the semiconductor device of the foregoing Embodiment I is formed, at its side facing the substrate, with a radiating groove 50 which is opened to the outside. In this case, the distance between the bottom 50A of the radiating groove 50 and the semiconductor chip 1, i.e., the thickness of the mold resin 2A below the semiconductor chip 1 is set at 0.3 mm or less.

By forming the radiating groove 50, as shown in FIGS. 68 and 69 (presenting sections showing the state in which the resin-sealed type semiconductor device of the Embodiment X is packed in the wiring substrate), the gap 51D between a substrate 51A or 51B and the bottom 50A of the radiating groove 50 is so enlarged that it is supplied with the cooling air, if directed normal to the drawing surface, whereby the radiation is effected from the bottom 50A of the radiating groove 50, too, to reduce the heat resistance of the semiconductor device.

Incidentally, in the structure of the present embodiment, the mold resin 2A below the semiconductor chip 1 is thinned to make it necessary to make a device when in the resin molding operation. If the mold resin 2A having a low molten viscocity in the molding operation, the package 2 can be formed, as shown in FIG. 61.

Next, a modification of the resin-sealed type semiconductor device of the foregoing Embodiment X is shown in FIG. 63 (presenting a section).

In this modified semiconductor device, as shown in FIG. 63, the upper surface of the package 2 shown in FIG. 61 is also formed with an open radiating groove 53. The distance between the bottom 50A of the radiating groove 50 and the bottom 53A of the radiating groove 53, i.e., the thickness of the mold resin below and above the semiconductor chip 1 is set at 0.3 mm or less.

By thus thinning the mold resin 2A of the package 2 above the semiconductor chip 1, the heat transfer surface is increased, but the heat resistance of the semiconductor device is decreased, so that the whole heat resistance can be accordingly reduced. As shown in FIG. 69, moreover, the gap when the semiconductor device is mounted on the substrates 51A and 51B can be shortened by twice as large as the depth of the groove so that the packing density can be increased.

Another modification of the semiconductor device according to the Embodiment X is shown in FIGS. 64 or 65.

In this modified semiconductor device, as shown in FIGS. 64 or 65, the mold resin 2A of the package of FIGS. 62 or 63 below the semiconductor chip 1 is removed to expose the side of the semiconductor chip 1, which is opposed to the principal surface, to the outside.

Thus, the mold resin 2A of the package 2 below the semiconductor chip 1 is removed to expose the side opposite to the principal surface of the semiconductor chip 1 to the outside so that the heat resistance of the semiconductor device can be dropped to reduce the overall heat resistance accordingly.

Thus, it is possible to prevent the cracking from the corner portions of the semiconductor chip 1 due to the temperature cycle.

Another modification of the semiconductor device of the Embodiment X is shown in FIGS. 66 or 67.

In this modified semiconductor device, as shown in FIGS. 66 or 67, the relation between the semiconductor chip 1 and the output leads 3B is reversed in the semiconductor device in which the mold resin 2A of the package 2 shown in FIGS. 62 and 64 below the semiconductor chip 1 is removed to expose the side of the semiconductor chip 1 opposite to the principal surface to the outside.

Thus, the cooling efficiency can be improved in case the cooling of the upper surface of the packing substrate 51 is dominant.

In the modification shown in FIGS. 66 or 67, the the package 2 is further formed with the radiating groove at the side of the substrate.

Next, one embodiment of a method of packing the substrate of the resin-sealed type semiconductor device of the present invention shown in FIGS. 61 to 67 will be described in the following.

In the embodiment of the method of packing the substrate of the resin-sealed type semiconductor device shown in FIGS. 61 to 67, as shown in FIG. 68, the resin-sealed type semiconductor devices 60A to 60H shown in FIG. 61 are planarly packed on the respective two sides of the substrates 51A and 51B by means of solder 61.

By thus packing the resin-sealed type semiconductor devices 60A to 60H on the substrates 51A and 51B, it is possible to improve the packing density of the semiconductor device and to radiate from the substrates 51A and 51B of the package 2, too. More specifically, since the radiations of the resin-sealed type semiconductor devices 60A to 60H are effected through the gap 51D between each of their packages 2 and the substrate 51A or 51B packing the former, the resistance to the cooling draft can be reduced to improve the radiating efficiency.

As shown in FIG. 69, the radiating groove 53 and the rise 54 above the package 2 of the resin-sealed type semiconductor device of the embodiment shown in FIG. 63 are packed together between the two substrates 51A and 51B.

Since the resin-sealed type semiconductor device is thus packed, its packing density can be further improved. The radiations can also be accomplished from the side of the substrate 51A or 51B of the package 2. Specifically, the gap when the resin-sealed type semiconductor device is placed over the substrate 51A or 51B can be shortened to one half of the depth of the groove, the packing density, can be increased (to 1.5 times as high as that of the embodiment of FIG. 64).

Since, moreover, the radiations of the resin-sealed type semicondutor device are accomplished through the gap 51D between the package 2 and its packing substrate 51A or 51B, the resistance to the cooling draft can be reduced to improve the radiating efficiency.

The resin-sealed type semiconductor device for sealing the DRAM according to the Embodiment XI of the present invention is shown in FIG. 70 (presenting a perspective view showing the exterior) and FIG. 71 (presenting a partially sectional view of FIG. 70).

As shown in FIGS. 70 and 71, the DRAM (or semiconductor chip) 1 is sealed up with the ZIP (Zigzag In-line Package) type resin-sealed package 2. The DRAM 1 is constructed to have a large capacity of 16 [Mbits].times.1 [bit] and a rectangular shade of 16.48 [mm].times.8.54 [mm]. This DRAM 1 is sealed in the resin-sealed type package 2 of 450 [mil].

The DRAM 1 has its principal surface arranged mainly with a memory cell array and a peripheral circuit, as shown in FIG. 71. The memory cell array is arranged in a matrix form with memory cells (or elements) for storing information of 1 [bit], as will be described later in detail. The peripheral circuit is composed of a direct peripheral circuit and an indirect peripheral circuit. The direct peripheral circuit is one for directly controlling the information writing operations and the information reading operations of the memory cells. The direct peripheral circuit is exemplified by a row address decoder, a column address decoder or a sense amplifier. The indirect peripheral circuit is one for controlling the operations of the direct peripheral circuit indirectly. The indirect peripheral circuit is exemplified by a clock signal generator or a buffer.

The principal surface of the DRAM 1, i.e., the surface arranged with the memory cell array and the peripheral circuit is further arranged with the inner leads 3A. The insulating films 4 are sandwiched between the DRAM 1 and the inner leads 3A. The insulating films 4 are made of a polyimide resin, for example. The surfaces of the insulating films 4 at the individual sides of the DRAM 1 and the inner leads 3A are formed with adhesive layers.

These adhesive layers are made of a polyester amideimide resin or an epoxy resin. The package 2 of this kind adopts the LOC (Lead On Chip) structure in which the inner leads 3A are arranged over the DRAM 1. Since the package 2 adopting the LOC structure can handle the inner leads 3A freely without being restricted by the shape of the DRAM 1, it can seal the DRAM 1 having a size enlarged according to the free handling. In other words, the package 2 adopting the LOC structure can have its packing density increased because the sealing (or package) size can be suppressed to a small value even if the size of the DRAM 1 is enlarged with the large capacity.

The aforementioned inner leads 3A have their one-side ends made integral with the outer leads 3B. These outer leads 3B are regulated with signals to be applied and are numbered according to the standards. In FIGS. 70 and 71, the upper step. is equipped sequentially from its left with terminals of odd numbers, e.g., 1st, 3rd, 5th, . . . , 21st and 23rd, and the lower step is equipped sequentially from its left with terminals of even numbers, e.g., 2nd, 4th, 6th, . . . , 22nd and 24th. In short, this package 2 is composed of totally twenty four terminals, i.e., the twelve terminals at each of the upper and lower steps.

The 1st one is an address signal terminal (A.sub.9); the 2nd one is an idle terminal; the 3rd one is a column address strobe signal terminal (CAS); the 4th one is an idle terminal; the 5th one is a data output signal terminal; and the 6th one is a reference voltage V.sub.SS terminal. This reference voltage V.sub.SS is the circuit operation voltage of 0 [V], for example. The 7th one is a power source voltage V.sub.CC terminal. This power source voltage V.sub.CC is the circuit operation voltage of 5 [V], for example.

The 8th one is a data input signal terminal (D.sub.in); the 9th one is an idle terminal; the 10th one is a write enable signal terminal (WE); the 11th one is a row address strobe signal terminal (RAS); the 12th one is an address signal terminal (A.sub.11); and the 13th one is an address signal terminal (A.sub.10). The 14th one is an address signal terminal (A.sub.0); the 15th one is an address signal terminal (A.sub.1): the 16th one is an address signal terminal (A.sub.2); the 17th one is an address signal terminal (A.sub.3); and the 18th one is a power source voltage V.sub.CC terminal. This power source voltage V.sub.CC is the circuit operation voltage of 5 [V], for example.

The 19th one is a terminal for the reference voltage V.sub.SS, which is the circuit operation voltage of 0 [V], for example.

The 20th one is an address signal terminal (A.sub.4); the 21th one is an address terminal (A.sub.5); the 22th one is an address terminal (A.sub.6); the 23th one is an address terminal (A.sub.7); and the 24th one is an address terminal (A.sub.8).

The other ends of the inner leads 3A are extended across the individual longer sides of the rectangle of the DRAM 1 to the center of the DRAM 1. The extensions of the other ends of the inner leads 3A are connected with the external terminals (i.e., bonding pads) BP arrayed at the central portion of the DRAM 1 through the bonding wires 5. These bonding wires 5 are made of aluminum (Al) but may be coated wires prepared by coating gold (Au), copper (Cu) or another metal wires with an insulating resin. The bonding wires 5 are bonded by the hot contact bonding method using ultrasonic vibrations.

Of the inner leads 3A, the inner leads (V.sub.CC) 3A of the 7th and 18th terminals are made integral and extended along the center portion of the DRAM 1 in parallel with the longer sides of the same (as will be called the common inner leads or the bus bar inner leads). Likewise, the inner leads (V.sub.SS) 3A of the 6th and 19th terminals are also made integral and extended along the center portion of the DRAM 1 in parallel with the longer sides of the same (as will be called the common inner leads or the bus bar inner leads). The inner leads (V.sub.SS) 3A are individually extended in parallel in the regions which are defined by the leading ends of the other ends of the remaining inner leads 3A. Each of those inner leads (V.sub.CC) 3A and (V.sub.SS) 3A is enabled to supply the power source voltage V.sub.CC and the reference voltage V.sub.SS to any position of the principal surface of the DRAM 1. In short, the package 2 is constructed to absorb the power source noises easily thereby to speed up the operations of the DRAM 1.

The shorter sides of the rectangle of the DRAM 1 are equipped with the chip supporting leads 3C.

Each of the inner leads 3A, the output leads 3B and the chip supporting leads 3C is cut from the lead frame and is molded. This lead frame is made of a Fe-Ni alloy (containing 42 to 50 [%] of Ni) or Cu, for example.

The DRAM 1, the bonding wires 5, the inner leads 3A and the chip supporting leads 3C are sealed up with the resin sealing portion 6. This resin sealing portion 6 is is made of an epoxy resin to which are added a phenol hardener, silicon rubber and a filler so as to reduce the stress. The silicon rubber is effective to drop the modulus of elasticity and the thermal expansion coefficient of the epoxy resin. The filler is formed in spherical grains of silicon oxide and is effective to drop the thermal expansion coefficient.

As is apparent from the description thus far made, according to the present Embodiment XI, the 16MDRAM 1 of the ZIP package type is packed in the vertical form in the substrate so that its packing density can be improved.

Although the present invention has been specifically described in connection with the embodiments thereof, it should not be limited thereto but can naturally be modified in various manners without departing from the gist thereof.

The effects to be obtained from the representatives of the invention disclosed herein will be briefly enumerated in the following:

(1) The semiconductor device is enabled to improve the reliability;

(2) The semiconductor device is enabled to improve the signal transmission rate and reduce the electrical noises by the stray capacity between the semiconductor chip and the leads;

(3) The semiconductor device is enabled to improve the radiation efficiency of the hear generated;

(4) The semiconductor device is enabled to reduce the influences of the heat during the reflow;

(5) The semiconductor device is enabled to reduce the influences of the heat in the temperature cycle;

(6) The semiconductor device is enabled to prevent the molding defect;

(7) The semiconductor device is enabled to improve the productivity; and

(8) The semiconductor device is enabled to improve the moisture resistance.

FIG. 72 is a section showing a semiconductor device according to another embodiment of the present invention and taken along line XII--XII of FIG. 74; FIG. 73 is a partially broken section taken along line XIII--XIII of FIG. 74; FIG. 74 is a general top plan view showing the semiconductor device; and FIG. 75 is a general top plan view showing the semiconductor chip in a circuit block of the semiconductor device.

The present Embodiment XII is directed to the resin-sealed type semiconductor device which has the DIP (Dual In-line Package) package structure using the tabless lead frame.

A package body 401 is made of a resin which is prepared by filling an epoxy resin with a filler such as silica (SiO.sub.2) to have a thermal expansion coefficient near that of silicone and which has a structure strong against the bending and the reflow cracking.

From the longitudinal two sides of the package body 401, there are extended to the outside and folded downward a plurality of leads 402 which constitute input/output pins and power source pins. These leads 402 are made of Cu, for example, and have their surfaces plated with a Sn-Ni alloy, for example.

To the surfaces of the leads 402 buried in the package body 401, there are bonded through an adhesive 404 rectangular insulating films 403a which are made of a polyimide resin, for example. The adhesive 404 is made of a polyimide resin, for example.

The leads 402 are folded, as shown in FIG. 74, below the insulating films 403a generally at a right angle in the horizontal direction such that their leading end portions plated with Ag, for example, extend from the shorter sides of the insulating films 403a to the outside.

As shown in FIGS. 72 and 73, moreover, the leads 402 are further folded midway downward below the insulating films 403a. To the resultant gaps between the leads 402 and the insulating films 403a, there are adhered second insulating films 403b which has a substantially equal thickness, so as to prevent the leads 402 from being deformed when in the molding operation. Incidentally, the insulating films 403b are made of the same polyimide resin as that of the foregoing insulating film 403a.

To the upper surfaces of the insulating films 403a, there is bonded through an adhesive 406 a rectangular semiconductor chip 405 which is made of single crystal of silicon. The adhesive 406 is made of a silicon resin, for example.

The chip 405 is constructed to have a slightly smaller area than that of the insulating films 403a. The chip 405 has its upper surface providing an integrated circuit forming surface, which is covered with a passivation film 407 of a polyimide resin so that it may be flattend.

The integrated circuit forming surface of the chip 405 is formed with a MOS DRAM of 4 mega bits, for example.

As shown in FIG. 75, the chip 405 is arranged at its center with a memory cell array M of the MOS DRAM of 4 mega bits and at its two sides with peripheral circuits P. Between the shorter sides of the chip 405 and the peripheral circuits P, there are arranged a plurality of bonding pads 408, which are electrically connected with the leads 402 through wires 409 made of Au, Cu or Al.

In the resin-sealed semiconductor device, parasitic capacities are usually established between the chip 405 and the leads 402. These parasitic capacities will increase inversely proportinally to the distance between the chip 405 and the leads 402 and proportionally to their opposed areas. In the package structure in which most of the leads 402 buried in the package body 401 are positioned below the chip 405, the opposed areas between the chip 405 and the leads 402 are enlarged to increase the parasitic capacities.

In the present Embodiment XII, however, the leads 402 below the chip 405 are folded midway downward to enlarge the distance between the chip 405 and the leads 402. As a result, the parasitic capacities to be established between the chip 405 and the leads 402 can be reduced more than the prior art in which the leads 402 are not folded midway downward.

As a result, the capacity of the leads 402 constituting the input/output pins is reduced to speed up the access to the MOS DRAM of 4 mega bits formed in the chip 405.

In the present Embodiment XII, the second insulating films 403b made of the same material as that of the insulating film 403a are adhered to the gaps between the leads 402 and the insulating film 403a. However, the insulating films 403a and 403b may be molded in an integral manner or made of different materials.

FIG. 76 is a section showing a semiconductor device according to another embodiment of the present invention and taken along line XIV--XIV of FIG. 77; FIG. 77 is a general top plan view showing the semiconductor device; and FIG. 78 is a general top plan view showing the semiconductor chip of the circuit block of the semiconductor device.

The package structure of the present Embodiment XIII is the same DIP of the tabless lead frame type at that of the foregoing Embodiment XII. Although this Embodiment XII uses the so-called "Chip On Lead" type in which the leads 402 are arranged on the lower side of the chip 405, the present Embodiment XIII adopts the so-called Lead On Chip type in which the chip 405 is arranged on the lower side of the leads 402.

Specifically, the chip 405 sealed in the package body 401 made of a resin similar to that of the foregoing Embodiment XII has its upper surface providing an integrated circuit forming surface. This integrated circuit forming surface is formed with a MOS DRAM of 4 mega bits, for example.

As shown in FIG. 78, the chip 405 is arranged at its central portion with the peripheral circuit P extending in the longitudinal direction of the chip and at its two sides with the memory cell arrays M. Since the peripheral circuit P is arranged at the center of the chip 405, the wiring length can be made less in the longitudinal direction of the chip 405 than that of the MOS DRAM of 4 mega bits of the Embodiment XII, in which the peripheral circuits P are arranged at the shorter sides of the chip 405, so that the wiring delay can be more reduced.

At the central portion of the chip 405, the bonding pads 408 are concentrated between the peripheral circuit P and the memory cell arrays M.

To the upper surface of the chip 405, as shown in FIG. 76, there is bonded through the adhesive 406 the rectangular insulating film 403a which is made of a polyimide resin, for example. This insulating film 403a has a slightly larger area than that of the chip 405 and is formed at its center with an opening 410.

To the upper surface of the insulating film 403a, there are bonded through the adhesive 404 a plurality of leads 402. These leads 402 are folded horizontally over the insulating film 403a, as shown in FIG. 77, to have their leading end portions arranged in the vicinity of the bonding pads 408. Moreover, the leads 402 and the bonding pads 408 are electrically connected through the wires 409.

As shown in FIG. 76, the leads 402 are folded midway upward over the insulating film 403a. To the resultant gaps between the leads 402 and the insulating film 403a, there are adhered the insulating films 403b which have substantially the same thickness as that of the gaps.

Thus, in the present Embodiment XIII, the leads 402 over the chip 405 are folded midway upward to increase the distance between the chip 405 and the leads 402 accordingly. As a result, the parasitic capacity to be formed between the chip 405 and the leads 402 can be reduced more than the prior art in which the leads 402 are not folded midway upward.

As a result, the capacity of the leads 402 constituting the input/output pins can be reduced To speed up the access to the MOS DRAM of 4 mega bits formed on the chip 405.

Although the invention has been specifically described in connection with the embodiments thereof, it should not be limited to the Embodiments XII and XIII but can naturally be modified in various manners within the gist thereof.

As shown in FIG. 79, for example, the present invention can be applied to the package structure in which a predetermined integrated circuit formed on the chip 405 and the leads 402 are electrically connected through solder bumps 411. In case, as shown, most of the leads 402 buried in the package body 401 are arranged along the lower side of the chip 405, the parasitic capacity to be established between the leads 402 and the chip 405 can be reduced by folding the intermediate portions of the leads 402 connecting the solder bumps 411 downward.

Although the packages of the foregoing Embodiments XII and XIII are of the DIP type, they should not be limited thereto but may be exemplified by the SOJ (Small Outline J-lead Package) or the PLCC (Plastic Leaded Chip Carrier).

Moreover, the present invention should not be limited to the semiconductor device using the tabless lead frame type but can also be applied to the semiconductor device of the type in which the leads are arranged on the upper surface of the chip packed on the tabs.

Although the description thus far made is directed to the case in which the invention is applied to the MOS RAM or the background of its application, the invention should not be limited thereto but can be applied to another semiconductor memory such as an EPROM or a logical LSI such as a microcomputer.

The effects to be attained by the representative of the invention disclosed herein will be briefly described in the following:

Specifically, the parasitic capacity to be established between the chip and the leads can be reduced by folding a portion of the leads, which are arranged over or below the chip packed in the package, outward with respect to the upper or lower sides of the chip.

Since, moreover, the insulating films are sandwiched between the chip and the leads, the distance between the chip and the leads can be so sufficiently enlarged to reduce the parasitic capacity to be established between the chip and the leads.

By arranging the peripheral circuit at the central portion of the chip, moreover, the wiring length taken in the longitudinal direction of the chip can be shortened to reduce the wiring delay.