Bidimensional FIR Filter

The present invention relates to bidimensional filters of the finite impulse response (FIR) type such as used especially for encoding TV pictures, for example for achieving a so-called "subband" encoding. In this application, the invention will be described in relation to the processing of a TV picture in which a memory contains the successive pixels of a picture. However, it is clear that the invention applies generally to the filtering of data arranged according to a bidimensional matrix.

Given a picture constituted by pixels Pij, as represented in FIG. 1, where i is a line index included between 1 and M, and j is a column index included between 1 and N, bidimensional FIR filtering comprises performing operations of linear combination on sequences of one-line pixels and on sequences of one-column pixels. It is said that the filtering is of rank 2p+1 if the considered sequence is a sequence associating 2p+1 successive pixels.

Thus, vertical filtering is defined by the following relation (1): ##EQU1## where Ck designates a coefficient, and horizontal filtering is defined by the following relation (2): ##EQU2## where Dk designates a coefficient.

These operations being linear, it will be noticed that the order of the horizontal and vertical filtering operations is of no consequence.

FIG. 2 is a diagram of a conventional FIR filter, used as a basis for the construction of a horizontal or vertical filter. This filter includes a series of identical modules M.sub.1 to M.sub.2p+1. In the figure, module M.sub.2 only is identified by a frame drawn in dotted lines. This module comprises a data input terminal e2 of a multiplier 1-2 where the input datum is multiplied by a coefficient C2. The figure shows the datum arriving on a single line. In fact, this datum is generally a binary word of several bits and input e2 corresponds to a bus comprising as many lines as bits included in the word. The output of multiplier 1-2 is sent to the first input of an adder 2-2, the second input of which receives the output of the preceding module. The adder output is connected to the input of a sampling register 3-2 which corresponds to a clock edge. The output of sampling register 3-2 is connected to the second input of the adder of the next module. All these registers are controlled by a clock CK which enables, at the introduction rate of the data, reading the datum present at the output of the preceding adder and sending the previously stored datum to the next adder.

It will be clear that such a filter, all the inputs of which are interconnected, enables performance of the operation indicated by formula (1). Indeed, considering the case where p=2 (5 modules), and assuming that data p1 . . . pn are successively introduced, output S provides at the sixth clock time:

at the seventh clock time:

and so forth.

Various correction techniques are known by those skilled in the art to provide, if necessary, data Q11, Q12 which are available with the elementary circuit described above. Thus, in the conventional case where the data matrix, namely a TV pixel image is scanned by horizontal lines, the row data sequentially arrive and the filter easily lends itself to horizontal filtering.

But, for vertical filtering, pixels P11, P21, P31 . . . PM1 are to be sequentially provided to the filter before processing pixels P12, P22 . . . PM2. This implies, still in the case of conventional horizontal scanning, to provide upstream of the filter delay lines having substantially the duration of a line. For a filter of rank 2p+1, 2p delay lines are to be provided. Such an architecture is for example described in the Article by Rao et al., Proceedings of IEEE International Symposium on Circuits and Systems, New Orleans, La., May 1990, pages 3050-3052. The delay lines are conventionally achieved by memories and, for example, for a filter of rank 17 and pixels defined on 8 bits, 16 memories connected to the filter through 16 buses of 8 bits are to be provided. If the filter and the delay lines are achieved in various chips, this requires, for the filter chip, the provision of an extremely high number of pads, with a resulting very expensive casing (the cost of an integrated circuit casing increasing very quickly with the number of pins of this casing) and a limited efficiency. Consequently, it has been proposed to include the memories serving as delay lines in the filter chip. But then, the chip has a very large silicon surface. In addition, the optimized technologies for manufacturing memories are generally not the same as those used for manufacturing filter cells. As a result, the chip of the assembly is not optimized. Anyhow, this integration of filters and memories on a single chip becomes impossible when the rank of the filter becomes too high, for example 65, or when the data words to be processed contain too many bits, for example 16 or 32.

This problem is all the more crucial as, in some TV circuits, for example those provided for high definition TV, in which it is desired to use a subband encoding technique, several filters are provided in a single TV set.

Thus, an object of the invention is to provide a new architecture for a FIR bidimensional filter enabling to optimize the implementation of the vertical filter without adversely affecting the implementation of the associated horizontal filter.

A further object of the invention is to provide a bidimensional FIR filter in which the memory portion and the filter portion itself are achieved in separated chips with a limited number of links between both chips.

To achieve these objects and others, the invention generally provides a digital bidimensional filter of rank 2p+1 for processing matrix data, sequentially comprising a "vertical" filter and a "horizontal" filter. The matrix data are applied to the vertical filter by a vertical scanning circuit having horizontal bands of a height of p data of the data matrix, the horizontal filter receiving the output data of the vertical filter according to the same scanning mode.

More particularly, the invention provides a FIR bidimensional filter of rank 2p+1 for data processing associating a "vertical" filter and a "horizontal" filter, each filter comprising 2p+1 cells. Each cell comprises a multiplier having a data input for receiving data and a coefficient input for receiving a predetermined coefficient, the multiplier output being connected to the first input of an adder, the output of which is connected to a register, the register output being connected to the second input of the adder of the next cell. The registers are controlled at the rate of the data introduction. The vertical filter comprises means for vertically scanning the data along stripes having a height of p data; means for simultaneously providing on a first line a stripe datum, on a second line a datum of the preceding stripe shifted by p data, on a third line, a datum of the penultimate preceding stripe again shifted by p data; and means for, at each clock time, connecting each cell input to one of the three lines. According to an embodiment of the invention, the horizontal filter comprises means for simultaneously providing to the inputs of the horizontal filter the output data of the vertical filter mutually shifted by p+1 data. According to an embodiment of the invention, the inputs on lines 1, p+1 and 2p+1 of the vertical filter are direct and the other inputs are equipped with two-channel multiplexers controlled so that the connection sequence of inputs to the line is as follows:

input 1: always connected to the first line;

input l (1<1<p+1): l-1 times to the second line, then p-l+1 times to the first line;

input p+1: always connected to the second line;

input m(p<m<2p+1): m-p-1 times to the third line, then 2p+1-m times to the second line;

input 2p+1: always connected to the third line;

a sequencer indicating the first datum of a column by which this sequence starts.

The foregoing and other objects, features and advantages of the invention will be apparent from the following detailed description of preferred embodiments as illustrated in the accompanying figures wherein:

FIG. 1, above described, shows a picture memory;

FIG. 2, above described, shows a conventional cell of a FIR filter;

FIG. 3 shows a scanning mode used according to the invention;

FIG. 4 shows the general architecture of a filter according to the invention;

FIG. 5 shows the filter portion itself of a vertical filter according to the invention; and

FIG. 6 shows the filter portion itself of a horizontal filter according to the invention.

In order to facilitate and simplify the practical implementation of a FIR bidimensional filter, the invention uses a stripe-type vertical scanning rather than a conventional raster horizontal scanning.

FIG. 3 illustrates the scanning mode used and the notations that will be used in the description that follows.

Hereafter, to simplify the description, the specific case of a recursive filter of rank 9 will be considered, that is, p=4 and 2p+1=9. In that case, the invention uses a vertical scanning through stripes having a height of p=4 pixels. FIG. 3 illustrates three successive scanning stripes, the elements of the first stripe being designated vertically by 1A, 2A, 3A, 4A; 5A, 6A, 7A, 8A; 9A, 10A, 11A, 12A; 13A . . . , the corresponding elements of the next two stripes being designated by the same number and respectively by letters B and C.

FIG. 4 shows the general architecture of a bidirectional, vertical and horizontal filtering system, according to the invention.

This system comprises a scanning conversion circuit 10 providing a vertical stripe scanning of the type illustrated in FIG. 3 at an output 11. This circuit is followed by two delay memories of p lines+p data (here, p=4). C, B and A designate buses carrying the output of the scanning conversion circuit 10, of the first delay memory 12, and of the second delay memory 14, respectively. These outputs C, B and A are sent to a vertical filter 16 and, if necessary, to other analog vertical filters (not shown). The vertical filter output is sent to a horizontal filter 18 and, if necessary, to other horizontal filters (not shown).

FIG. 5 shows an embodiment of the vertical filter and exemplifies its connections with buses A, B and C.

For reasons which will appear later on, input e.sub.1 of cell M.sub.1 is connected to bus A, input e.sub.p+1 of cell M.sub.p+1 is connected to bus B, and input e.sub.2p+1 of cell M.sub.2p+1 is connected to bus C. The cells included between the cell M.sub.1 and cell M.sub.p+1 have their input connected through a multiplexer MUX to either one of buses A and B, and the cells included between cell M.sub.p+1 and cell M.sub.2p+1 have their input connected through a multiplexer to either one buses B and C.

Referring to the notations of FIG. 3, it clearly appears that it is desired to sequentially provide to inputs e1-e9, when p=4, the following signals: ##EQU3##

The general rule to be followed is deduced from this table. Bus B must present the data of bus A shifted by p (=4) lines plus p (=4) clock periods and, similarly, bus C must present the data of bus B delayed by p lines+p clocks periods in order to, for example, simultaneously present to the filters pixels 9A, 5B and 1C; 10A, 6B and 2C; 11A, 7B and 3C . . . This result is obtained with the delay circuits adjusted in the way illustrated in FIG. 4. On the other hand, it can be seen that the control sequences of the multiplexers respectively choose each of the inputs as follows: ##EQU4##

This sequence is periodic with a period 4 (p) and starts at the same time as a pixel of the upper line is presented (1A, for example). A sequencer 20, triggered by a synchronization signal, provides this function. It can be seen from the above table that the inputs 1, 5 and 9 (1, p+1 and 2p+1) need not being associated with a multiplexer.

More generally, for a filter of rank 2p+1, each of the three buses A, B, C scans p video lines and the control sequence of the multiplexer, periodic with a period p, is as follows:

Referring back to FIG. 4, it is noted that the circuit according to the invention connects the assemblies of storage and scanning conversion circuits to a filter circuit with only three buses instead of 2p buses, as in the prior art. This is very significant when the filter is of a high rank (p=8, 16, or 32) and that the data to be filtered comprise a high number of bits (8, 16 or 32). Thus, it is possible to manufacture filtering circuits using processor-type technologies which are particularly well adapted for this fabrication. It is also possible to manufacture the circuit comprising the memories including adapted circuits as well, for example DRAM memory circuits, which permits integrating a very high number of cells on a relatively small surface.

It will be noted that, as compared to conventional circuits, the memory part itself according to the invention comprises two p-lines memories plus a scanning conversion memory including p lines too. Whereas, conventionally, only 2p memories of one line have been used. This drawback of the invention is only apparent, on the one hand, because of the major advantage brought by the decrease in the number of buses connecting the memories to the filter and, therefore, in the number of pads for the filtering circuit and, on the other hand, due to the fact that, according to the invention, the memories can be integrated in a separate chip made according to an adapted technology. In addition, it will be noted that the scanning conversion circuit is also often used in other parts of a system processing TV pictures.

On the other hand, as will be shown in connection with FIG. 6, the major simplification brought by the invention for achieving the vertical filter does not cause a significant complexity increase of the horizontal filter.

At the vertical filter output, data are scanned by stripes. Therefore, the horizontal filter must receive on its successive inputs data separated one from the other by p+1 clock pulses. This is easily achieved with the circuit illustrated in FIG. 6, where the same reference characters designate the same elements as in the preceding figures. It will be noted that, between each input, a delay memory 21, 22 . . . of p+1 data is provided, that is, a small-size memory as compared to one-line duration memories (it is to be remembered that usually, for conventional TV sets, a line comprises about 700 pixels and in high definition TV, about 2,000 pixels).

In subband encoding applications, a selected number of data of a sequence will conventionally be eliminated at the output of each filter and an appropriate scanning rate will be chosen.