Cyclic Redundancy Check Operating Method and a Head Error Checker Synchronizing Unit in an Asynchronous Transfer Mode Switching Process

The present invention relates to a CRC (Cyclic Redundancy Check) operating method for performing a CRC operation on an encoded word and to an HEC (Head Error Checker) synchronizing unit for detecting an error in a header of a cell and synchronizing a cell in an ATM switching method.

A typical method of detecting and correcting an error in data used in a data process or data communication, etc., is a cyclic redundancy check (hereinafter referred to as a CRC). This is a checking method based on the fact that an encoded polynomial containing a cyclic code (cyclic replacement of any encoded word results in another encoded word) can be divided by a generated polynomial.

For example, when data are encoded, they are segmented in predetermined length units. Next, a CRC code can be obtained as a polynomial code indicating a remainder of a division by dividing by mod (modulo) 2 and by an appropriately generated polynomial in the binary representation comprising predetermined length data to be processed. Then, the CRC code is applied to the original data to be processed. An encoded polynomial comprising an encoded word necessarily comprises a cyclic code divided by the above described generated polynomial.

When an encoded word formed by adding a CRC code is decoded, it is segmented in the same length units as in the encoding process. Then, a CRC operation is performed in which the encoded polynomial comprising encoded words of predetermined length is divided by the same generated polynomial as that used in the encoding process. If the remainder is "0", it means that no errors have arisen in the encoded word from the encoding process to the decoding process. However, a remainder other than "0" means an error has arisen.

An example of a circuit using a CRC operation is an HEC synchronizing circuit in an ATM switching method.

In an ATM (Asynchronous Transfer Mode) switching method, communication data are divided into fixed lengths of 53 bytes. Then, each cell is transmitted after being multiplexed to the time slots in the transmission line. A large-capacity, high-speed communication network can thus be realized by autonomously switching the cell with a hardware switch according to the destination information added at the header part of each cell.

FIG. 1 shows the general configuration of an ATM switching unit. Each cell is transmitted via a large capacity ATM transmission line (optical transmission line) 101 at a transmission speed of 600 Mbps (megabits/second), for example. Each transmission line 101 is terminated by a transmission line terminal unit 102, multiplexed by a multiplexer (MUX) 103 and then switched by an ATM switch 104.

In the transmission line 101, each cell is multiplexed as shown by (a) of FIG. 2 to a predetermined 53-byte time slot and transmitted in the direction indicated by the arrow shown by (a) of FIG. 2. Each cell comprises a header part containing its destination information, etc., and an information part containing communication information.

In a MUX 103 shown in FIG. 1, a multiplexed cell is re-multiplexed to a plurality of transmission lines after being inputted from each ATM transmission line 101. Therefore, the cell input timing through the ATM transmission line 101 must be exactly synchronized. The synchronizing operation is realized as an operation by a transmission line terminal unit 102 of detecting the head of a cell header applied through each of the ATM transmission lines 101.

FIG. 3 shows the general configuration of each of the transmission line terminal units 102 for realizing the above described synchronizing operation. An HEC (described later) synchronizing circuit 301 detects the input timing of the header part of a cell 304 inputted from the transmission line 101. A cell synchronization determining circuit 302 determines the stable input timing of a cell by detecting in the HEC synchronizing circuit 301 the repetition of the input timing of a header part of a plurality of cells 304. Then, the circuit 302 outputs a cell synchronizing pulse 305 as shown in FIG. 2. According to a cell synchronizing pulse 305, a cell 304 temporarily stored by a delay circuit 303 is outputted toward the MUX 103 shown in FIG. 1 according to the timing shown in (a) and (b) of FIG. 9. In the MUX 103 shown in FIG. 1, each of the cells 304 transmitted from each of the transmission line terminal units 102 is multiplexed according to the cell synchronizing pulse 305 provided by each of the transmission line terminal units 102.

A header part of a cell comprises 5-byte data, the last byte of which is called an HEC (Header Error Checker). The HEC is a CRC code added to 4-byte data transmitted as destination information on the sending side. That is, on the sending side, a one-byte CRC code can be obtained as a remainder of a division by dividing a polynomial in the binary representation comprising the above described 4-byte data to be transmitted by the generated polynomial x.sup.8 +x.sup.2 +x+1. The 5-byte data of a header part of a sending cell can be generated by adding the CRC code to the 4-byte data to be transmitted.

On the receiving side, in response to the generation of a sending header part, the HEC synchronizing circuit 301 (FIG. 3) sequentially retrieves 5-serial-byte data by moving each of their positions forward by one byte each. Then, a CRC operation is performed such that a binary polynomial comprising 5-byte-data to be received is divided by the generated polynomial used on the sending side. As indicated by the principle of the above described CRC operation, the remainder of the division in which a 5-byte coded-word polynomial is divided by a generated polynomial used on the sending side must be "0" if the 5-byte data of a header part are correctly extracted on the receiving side. The HEC synchronizing circuit 301 must detect as current input timing of an errorfree header part of a cell 304 (FIG. 3) the input timing of 5-byte data to be received when a remainder "0" is obtained in the above described CRC operation. That is, the HEC synchronizing circuit 301 detects the input timing of a header part and simultaneously detects errors therein.

FIG. 4 shows a configuration sample of the prior art technology of the HEC synchronizing circuit for realizing the detecting operation for a header part.

As described above, the HEC synchronizing circuit 301 must sequentially retrieve 5-serial-byte data by moving each of their positions forward by one byte each. Then, a CRC operation is performed such that a binary polynomial comprising 5-byte-data to be received is divided by the generated polynomial used on the sending side. In this case, the data is sequentially received in a byte unit, stored in a flip-flop (FF) 402.sub.0, sequentially shifted in a byte unit in FF402.sub.1 -FF402.sub.4, and 5-byte receiving data are retrieved as the output of FF402.sub.0 -402.sub.4. Each of the FFs stores data in a byte unit. Conventionally, five CRC operating circuits CRCCs 401.sub.1 -401.sub.5 for performing a byte-by-byte CRC operation are connected in serial. In each CRCC 401, a CRC operation is performed such that each byte in the 5-byte data is divided by a generated polynomial x.sup.8 +x.sup.2 +x+1. In this case, an operation result obtained by the operation in the previous CRCC 401 (the remainder after dividing each byte datum by a generated polynomial) is provided to the next CRCC 401. The all "0" data are applied as an initial value to the first CRCC 401.

FIG. 5 shows the circuit configurations of each of the CRCCs 401.sub.1 -401.sub.5 shown in FIG. 4. In FIG. 5, a.sub.0 -a.sub.7 are received data outputted from the FF 402, b.sub.0 -b.sub.7 are results of the CRC operation in the previous CRCC 401, and c.sub.0 -c.sub.7 are results of the CRC operation in the present CRCC 401. a.sub.7, b.sub.7, and c.sub.7 are MSBs, that is, the most significant bits, and a.sub.0, b.sub.0, and c.sub.0 are LSBs, that is, the least significant bits. The circuit configuration shown in FIG. 5 is well-known for performing a CRC operation and comprises a combination of exclusive logical sum (EOR) elements.

However, as indicated in FIG. 4, the conventional HEC synchronizing circuit requires five serially connected CRC operating circuits (CRCC) 401.sub.1 -401.sub.5, and the hardware is configured in a large scale. Specifically, in the ATM switching method, the hardware must be configured in the smallest possible scale because 1-byte data are processed at a very high clock speed of 18.75-75 MHz.

The above described problem is not limited to an HEC synchronizing circuit in an ATM switching method, but also occurs in a CRC operating unit for sequentially performing a CRC operation to detect the segmentation of data containing a CRC code and for detecting errors in the data.

The present invention has been developed based on the above described background, and an object of the present invention is to realize a CRC operation in small scale hardware.

In the prior art technology, the number of serially connected CRC operating circuits must correspond to the data length of a header part. By contrast, in the present invention, a CRC operation for conducting the HEC synchronization can be realized only by one CRC operating unit and one CRC operation result derivation unit. Taking a coset into account according to the CCITT (International Telegraph and Telephone Consultative Committee) recommendations, the hardware can be configured in a smaller scale than in the prior art technology.

Other objects and features of the present invention can be easily recognized by referring to the attached drawings and the description of the preferred embodiment of the present invention,

FIG. 1 (PRIOR ART) shows the configuration of the ATM switching unit comprising the HEC synchronizing circuit;

FIG. 2 (PRIOR ART) shows a view for explaining the cell synchronizing operation;

FIG. 3 (PRIOR ART) shows the configuration of the transmission terminal unit associated with the HEC synchronizing circuit;

FIG. 4 (PRIOR ART) shows the configuration of the HEC synchronizing circuit of the prior art technology; and

FIG. 5 (PRIOR ART) shows the circuit configuration of a CRCC.

FIG. 6 is a block diagram for explaining the principle of the present invention;

FIG. 7 shows a principle configuration for explaining the preferred embodiment of the HEC synchronizing circuit of the present invention;

FIG. 8 shows the first example of a circuit configuration of a CCR;

FIG. 9 is an operational timing chart for explaining the principle configuration of the preferred embodiment;

FIG. 10 shows the second example of a circuit configuration of a CCR;

FIG. 11 shows a practical configuration for explaining the preferred embodiment of the HEC synchronizing circuit associated with the present invention;

FIG. 12 is an operational timing chart for explaining an example of a practical configuration of the present invention;

FIG. 13 shows a view for showing for each initial value an operation result obtained in a CRC operation performed on a header part using an initial value having only one value "1" in its 8 bits.

FIG. 6 is a block diagram for explaining the principle of the present invention, and shows an HEC synchronizing unit for detecting errors in the header part of a cell in the asynchronous transfer mode (ATM) switching method and for performing a cell synchronizing operation.

A CRC operating unit 602 performs a cyclic redundancy check (CRC) in which received data 601 are divided by a predetermined generated polynomial with a CRC operation result actual value 603 obtained in the previous operation as an initial value in response to received data 601 applied in a byte unit. Then, it outputs the CRC operation result actual value 603 as a remainder.

A delay unit 604 delays the output of the CRC operation result actual value 603 by the time in which a header part of the received data 601 takes to be inputted.

A CRC operation result derivation unit 605 outputs a value as a CRC operation result derivation value 606 as if it were obtained as a result of a CRC operation performed for all the receiving data of a header part including a CRC code of the length of the above described header part using as an initial value the CRC operation result actual value 603 outputted by the delay unit 604. The unit 605 comprises a plurality of logical circuits for outputting a value as a CRC operation result derivation value 606 as if it were obtained as a result of a CRC operation performed for all the receiving data of a header part including a CRC code of the length of the above described header part using an initial value having one bit value different from the values of the other bits. Each logical circuit is provided for each initial value having a different value bit placed at a different position. Each of the logical circuits is connected such that the CRC operation result derivation value 606 can be obtained as an exclusive logical sum of output values of the logical circuits each corresponding to an initial value having a different value at a different bit position .

A coincidence detecting unit 607 compares the CRC operation result actual value 603 outputted by the CRC operating unit 602 with the CRC operation result derivation value 606 outputted by the CRC operation result derivation unit 605. It then detects the input timing of received data containing no errors in the header part provided with a CRC code.

The above described configuration of the present invention relates to an HEC synchronizing unit in the ATM switching method. However, the present invention is not limited to this application, but can be used to detect the segmentation of data containing a CRC code by sequentially performing a CRC operation for detecting errors in data.

In the present invention, when a CRC operation is performed for a header part containing a CRC code (the header part can comprise common data to be processed) and when an initial value does not comprise all "0s" but may have other bit configurations, the operation result of the CRC operation of the header part takes a unique value in response to the initial value. Thus, the CRC operation result derivation unit 605 (corresponding to the CCR) performs a deriving operation to derive as the CRC operation result derivation value 606 an operation result in response to any initial value.

Based on the above described condition, the CRC operating unit 602 performs a CRC operation for each piece of sequentially received data in a byte unit, and the CRC operation result actual value 603 obtained by each CRC operation is used as the initial value of the next CRC operation.

In the above described configuration, the CRC operation result actual value 603 obtained in the CRC operation performed on the 5th byte (in the HEC portion) of a 5-byte header part is equal to the CRC operation result derivation value 606 derived by the CRC operation result derivation unit 605 using the initial value used when a CRC operation is performed for the byte four bytes before the present one, that is, the first byte of the header part. The initial value is equal to the CRC operation result actual value 603 obtained in the CRC operation performed for the 5 bytes before the present byte.

In the present invention, the delay unit 604 delays the CRC operation result actual value 603 by 5 bytes corresponding to the data length of a header part, for example. Then, the CRC operation result derivation unit 605 derives the CRC operation result derivation value 606 as if it were obtained as a result of a CRC operation performed for the whole 5-byte header using as an initial value the CRC operation result actual value 603 for the data 5 bytes before the present received data 601 (data to be processed) in the present CRC operation. Thus obtained CRC operation result derivation value 606 is compared with the CRC operation result actual value 603, the input timing of receiving data containing no errors in a header part can be detected as the timing indicating "coincidence" between these values, thus establishing the HEC synchronization.

A preferred embodiment of the present invention is described below in association with the attached drawings.

The general configuration of the ATM switching unit related to the preferred embodiment of the present invention is the same as that shown in FIG. 1. The block configuration of a transmission line terminal unit 102 (FIG. 1) for realizing an HEC synchronizing operation is the same as that shown in FIG. 3. The feature of the preferred embodiment described below resides in a practical configuration of the HEC synchronizing circuit 301. Before explaining the configuration, the operational principle of the preferred embodiment is described.

In the prior art technology shown in FIG. 4, one-byte data comprising all "0s" are applied as an initial value to the first CRCC 401, and an operation result of a CRC operation in each of the CRCCs 401 is provided to the next CRCC 401. The input timing of a 5-byte header part is detected with the operation result in the 5th CRCC 4015 obtained as "0". Thus, in the prior art technology, since an initial value must be set as all "0s", five CRCCs for performing a CRC operation in a byte unit must be connected, and the hardware is thus configured in a large scale.

By contrast, in the present invention, a result of a CRC operation for a 5-byte header part (a remainder of a division in which the 5-byte data of a header part is divided by a generated polynomial using the above described initial value) is uniquely obtained in response to an initial value when a CRC operation is performed for a 5-byte header part and when an initial value in the operation does not comprise all "0s" but any other initial values.

FIG. 13 shows results of operations in which only one bit in an initial value comprising eight bits, that is, one byte, contains "1" when a CRC operation is performed for a 5-byte header part.

Using FIG. 13, a result of a CRC operation performed for a 5-byte header part can be derived when an initial value can be any value. That is, in any initial value comprising 8 bits, a bit indicating the value "1" is extracted, and an operation result of an initial value having the above described bit as the only bit containing the value "1" is extracted from FIG. 13. A result of a CRC operation performed on a 5-byte header part comprising the above described initial value can be derived as a value sequentially indicating exclusive OR for each bit in each operation result. For example, when an 8-bit initial value is "00100101", the 0-th, 2nd, and 5th bits indicate "1". Therefore, a result of a CRC operation for a 5-byte header part can be derived as the value "10001001" obtained by sequentially calculating an exclusive logical sum for each bit of the operation results "01100010", "10001111", and "01100100" obtained in (a), (c), and (f) in FIG. 13.

The present preferred embodiment is based on the above described fact. That is, a CRC operation is performed on each piece of sequentially received 1-byte data, and a result obtained in each CRC operation is used as the initial value of the next CRC operation. In this configuration, the result obtained in the CRC operation performed for the 5th byte of a 5-byte header part (an HEC portion) is equal to the operation result derived according to FIG. 13 for the initial value used when a CRC operation is performed on the byte four bytes before the present one, that is, the first byte of the header part. The initial value is equal to the result of the CRC operation for the byte 5 bytes before the present one. In the present preferred embodiment, a circuit is provided to derive a value as if it were obtained as a result of a CRC operation performed for a 5-byte header part using as an initial value the result of the CRC operation for the data which is 5 bytes before those to be processed in the present CRC operation. The input timing of the 5th byte of the header part, that is, the HEC portion, is detected as the timing at which the derivation result and the result of the CRC operation for the data being processed are equivalent. The synchronization of a header part can thus be established.

FIG. 7 shows the principle for explaining the present preferred embodiment for realizing the above described operations. Receiving data 705 sequentially applied in a byte unit from an ATM transmission line 101 (FIG. 1) are temporarily stored in the FF704.sub.0 and then applied to a CRC operating circuit (CRCC) 701.

The CRCC 701 performs for the receiving data 705 applied in a byte unit from the FF704.sub.0 a CRC operation in which the above described receiving data 705 are divided by the generated polynomial x.sup.8 +x.sup.2 +x+1 using as an initial value a CRC operation result actual value 706 obtained in the previous CRC operation, and then it outputs as a remainder an 8-bit CRC operation result actual value 706.

The CRC operation result actual value 706 is delayed by 5 input timings by the five serially connected FF 704.sub.1 -704.sub.5, and applied to a CRC code correcting circuit (CCR ) 702.

The CCR 702 outputs a value as an 8-bit CRC operation result derivation value 707 as if it were obtained as a result of a CRC operation performed for a 5-byte header part using as an initial value the CRC operation result actual value 706 outputted by the CRCC 701 5 input timings before the present process timing, that is, the initial value used in the CRCC 701 which is 4 input timings before the present process timing.

A coincidence detecting circuit 703 compares the 8-bit CRC operation result actual value 706 outputted by the CRCC 701 with an 8-bit CRC operation result derivation value 707 outputted by the CCR 702. If all corresponding bits of these values coincide, a determination output 708 indicating coincidence is outputted.

The FF 704.sub.0 -704.sub.5 operate according to a clock CLK synchronized with the input timing of the received data 705. In this case, if the transmission speed of the ATM transmission line 101 shown in FIG. 1 is 600 Mbps, for example, the input speed of a byte (8 bits) can be calculated as:

where 75 MHz indicates the clock frequency.

In FIG. 7, the actual circuit configuration of the CRCC 701 is the same as that shown in FIG. 5 and described above in the prior art technology.

Next, FIG. 8 shows the first typical configuration sample of a circuit. As shown in FIG. 8, the CCR 702 comprises a plurality of exclusive logical sum elements (EOR). Bit signals c.sub.0 -c.sub.7 (MSB on the side of c.sub.7) corresponds to each bit of the CRC operation result actual value 706 inputted to the FF 704.sub.5 shown in FIG. 7 and outputted from the CRCC 701 5 input timings before the present process timing, that is, each bit of the initial value in the CRCC 701 4 input timings before the present process timing. Bit signals D.sub.0 -D.sub.7 correspond to each bit of the CRC operation result actual value 706 shown in FIG. 7.

Each of 801.sub.0 -801.sub.7 enclosed in dotted lines performs a conversion process indicated by (a)-(h) shown in FIG. 13. For example, the 801.sub.0 is a circuit unit for outputting "01100010" when the 0-th bit c.sub.0 of an initial value indicates "1" and the 1st bit c.sub.1 to the 7th bit c.sub.7 indicate "0". An exclusive logical sum is sequentially obtained in a bit unit for each operation result shown in FIG. 13 by connecting each of the portions 801.sub.0 -801.sub.7 enclosed in dotted lines through an exclusive logical sum element as shown in FIG. 8. Basically, an exclusive logical sum element is applied to the bit position where "1" is outputted by a corresponding portion 801 enclosed in dotted lines according to FIG. 13. A byte data applied to the portion 8017 comprise all "0s" as shown in FIG. 8.

FIG. 9 shows an operational timing chart for explaining the principle configuration of the present preferred embodiment shown in FIGS. 5, 7, and 8. The receiving data 705 are entered in a byte unit as shown by (a) of FIG. 9 after synchronized with the clock CLK, having a frequency of 75 MHz, for example, as shown by (b) of FIG. 9. Then, the data are stored by the FF 704.sub.0 at the rise timing of the clock CLK, and the output is applied to the CRCC 701 at the timing shown by (c) of FIG. 9. At the same timing, the CRC operation result actual value 706 is outputted from the CRCC 701 to the coincidence detecting circuit 703. At the same timing again, the content of the CRC operation result derivation value 707 is outputted from the CCR 702, and it is a derivation value corresponding to the CRC operation result actual value 706 outputted from the CRCC 701 5 input timings before the present process timing as shown by (d) of FIG. 9. For example, by (c) of FIG. 9, the following values can be obtained at the timing at which the 5th byte of a header part, that is, the portion B.sub.HEC of the HEC, is applied to the CRCC 701. a.sub.53 shown by (d) of FIG. 9 can be obtained from the FF 704.sub.5 as the CRC operation result actual value 706 at 5 inputs timing before the present process timing corresponding to A.sub.53, that is, the 53rd byte (last byte) of the previous cell of the present cell. Also, the CRC operation result derivation value 707 corresponding to a53 can be obtained from the CCR 702. If there are no errors in the data of the header part, a determination output 708 indicating coincidence is outputted by the coincidence detecting circuit 703.

As described above, in FIG. 4, five CRCCs 401 must be serially connected, while, in FIG. 7, only two circuits comprising one CRCC 701 and another CCR 702 of the same scale are required, and the circuit scale can thus be reduced.

Next, FIG. 10 shows the second example of a circuit configuration. In the above described first example of the circuit configuration shown in FIG. 8, the portions 801.sub.0 -801.sub.7 enclosed in broken lines can be connected in any order according to the characteristics of an exclusive logical sum. In the portion 801.sub.7 enclosed in broken lines, each exclusive logical sum element is omitted. At its bit position, five exclusive logical sum elements can be omitted if an initial value c.sub.7 is directly applied to the next portion 801 enclosed in broken lines. Thus, as shown in FIG. 10, a CCR 702 can be configured with the smallest possible number of elements, and the circuit scale can thus be further reduced.

FIG. 11 shows a practical configuration for explaining the preferred embodiment of the HEC synchronizing circuit 301 shown in FIG. 3 of the present invention. The basic configuration and operation are the same as those of FIG. 7. In FIG. 11, the CCR 1102 corresponds to the CCR 702 shown in FIG. 7; the coincidence detecting circuit 1103 corresponds to the circuit 703 shown in FIG. 7; the FFs 1104.sub.0 -1104.sub.5 correspond to the FFs 704.sub.0 -704.sub.5 ; the receiving data 1105 correspond to the data 705 shown in FIG. 7; the CRC operation result actual value 1106 corresponds to the value 706 shown in FIG. 7; the CRC operation result derivation value 1107 corresponds to the value 707 shown in FIG. 7; and the determination output 1108 corresponds to the output 708 shown in FIG. 7. The configuration of FIG. 11 differs from that of FIG. 7 in that it comprises only two CRCCs 1101.sub.1 and 1101.sub.2, two additional FFs 1104.sub.7 and 1104.sub.8 for retaining each output, an AND element 610, and an exclusive logical element 611. The configuration of the preferred embodiment shown in FIG. 11 follows the circuit configuration according to the CCITT recommendations.

According to the CCITT recommendations related to the ATM switching method, an exclusive logical sum is calculated with each bit of a CRC code obtained as a CRC operation result and each bit of a code called "coset" indicating "01010101", and the operation result is stored as an HEC in the header part of a cell according to the recommendations when on a sending side of a cell a CRC operation is performed for 4-byte header data and a 1-byte HEC is added to the data. Therefore, on the receiving side, an exclusive logical sum is calculated again for the HEC portion with the receiving data 1105 outputted by the FF 1104.sub.0 and the above described coset "01010101" to decode the original CRC code, and then perform a CRC operation. The exclusive logical sum element 611 and CRCC 1101.sub.2 shown in FIG. 11 are provided to perform the necessary processes involved. The exclusive logical sum element 611 is used as an element to obtain an exclusive logical sum for each bit using 1-byte (8-bit) receiving data 1105 provided by the FF 1104.sub.0 and 8-bit coset "01010101".

FIG. 12 is an operational timing chart for explaining the practical configuration of the preferred embodiment shown in FIG. 11. For example, the 5th byte of a header part, that is, the HEC portion B.sub.HEC, is outputted at the timing shown by (e) of FIG. 12. The exclusive logical sum element 611 subtracts a coset from the HEC data, and they are inputted to the CRCC 1101.sub.2. At the next timing at which a b.sub.HEC shown by (f) of FIG. 12 is outputted as a CRC operation result true value 1109 by the FF 1104.sub.8, an a.sub.53 shown by (h) of FIG. 12 corresponding to A.sub.53, the 53rd byte (last byte) and the previous cell of the present input cell, is obtained as a CRC operation result actual value 1106. At the same timing, a CRC operation result derivation value 1107 corresponding to the above described a.sub.53 can be obtained by the CCR 1102. If no errors have arisen in the data of the header part, a determination output 1108 indicating a coincidence is outputted by the coincidence detecting circuit 1103.

As described above an appropriate process can be performed for an HEC provided with a coset.

The configuration shown in FIG. 11 differs from that shown in FIG. 7 in a clock for operating each FF 1104. In the preferred embodiment shown in FIG. 11, a transmission method called SONET is used in the ATM transmission line 101 shown in FIG. 1. Therefore, in the preferred embodiment shown in FIG. 11, a signal component of a pulse OH indicating overhead of the SONET is subtracted from an AND element 610. The resultant clock FF CLK operates each FF 1104. In this configuration, as shown in (a) of FIG. 12, no FF 1104 continues its operation if the receiving data 1105 equals the overhead of the SONET.

As described above, in the practical configuration of the preferred embodiment shown in FIG. 11, an HEC synchronizing circuit 301 (FIG. 3) can be realized in conformity with the CCITT recommendations related to the ATM switching method.