Cascade Sense Amplifier for Reading Out Data Stored in Semiconductor Memory Device

The present invention relates to a cascade sense amplifier for reading out data stored in a semiconductor memory device, and more particularly, to a cascade sense amplifier which includes a plurality of section separated sense amplifiers provided in each of a plurality of section cell array each storing data, a pair of cascade wires in which signals respectively showing different logic levels flow and its one end to which the section separated sense amplifiers are commonly connected, and a main sense amplifier provided at the other end of the pair cascade wires.

There are conventionally semiconductor memory devices which have cascade amplifiers constituted by bipolar transistors and metal oxide semiconductor (MOS) transistors, and sectional cell arrays storing data which are read by the cascade amplifiers.

FIG. 1 shows a circuitry with respect to such a kind of the conventional semiconductor memory devices.

In FIG. 1, at respective ends (not shown) of data line D.sub.IN and *D.sub.IN, there are provided a plurality of memory cell array (not shown in FIG. 1) each of in which a plurality of memory cells are arranged in a matrix. Here, in this specification, a symbol of "*" means an inverted signal line, and *D.sub.IN is a signal line in which an inverted signal of D.sub.IN flows. A cascade sense amplifier 1 shown in FIG. 1 comprises a plurality of section separated sense amplifiers 2 to which the other respective ends of the data lines D.sub.IN and *D.sub.IN are connected, a cascade wiring portion 3 including pair of cascade wires D.sub.1 and *D.sub.1 each having one respective ends to which the section separated sense amplifiers are commonly connected, and a main sense amplifier 4 which is connected to the other respective ends of the cascade wires D.sub.1 and *D.sub.1.

The section separated sense amplifier 2 includes a differential pair comprised of NPN-type transistors Tr.sub.D and Tr.sub.E, and a constant current source 2a constituted such by an N-channel metal oxide layer semiconductor (MOS) transistor or the like. Emitters of the transistors Tr.sub.D and Tr.sub.E are commonly connected to the constant current source 2a. A base of the transistor Tr.sub.D is connected to the data line *D.sub.IN, and a base of the transistor Tr.sub.E is connected to the data line D.sub.IN.

The cascade wiring portion 3 comprises the cascade wire D.sub.1 connected to a collector of the transistor Tr.sub.D, and the cascade wire *D.sub.1 connected to a collector of the transistor Tr.sub.E. Here, symbols C.sub.D1 and *C.sub.D1 show parasitic capacitance existing in the cascade wires D.sub.1 and *D.sub.1, respectively.

The main amplifier 4 comprises NPN-type bipolar transistors Tr.sub.A, Tr.sub.B and Tr.sub.C, collectors of which are connected to the power source V.sub.CC and outputs D.sub.1 and *D.sub.1, respectively, constant current sources 4a and 4b comprised of such as N-channel MOS transistors provided on emitter sides of transistors Tr.sub.B and Tr.sub.C, respectively, and a constant current source 4c provided on an emitter side of the transistor Tr.sub.A. The transistors Tr.sub.B and Tr.sub.C constitute a differential pair, two resistors, and the constant current sources 4a and 4b supply the constant current i.sub.0 for a bias respectively corresponding to the transistors Tr.sub.B and Tr.sub.C. The transistor Tr.sub.A is connected by a diode connection, and the transistor Tr.sub.A and the constant current source 4c are connected to bases of the transistors Tr.sub.B and Tr.sub.C through a node N.sub.O to bias these transistors Tr.sub.B and Tr.sub.C. A symbol C.sub.Base denotes a parasitic capacitance existing in the main amplifier.

In the above-mentioned semiconductor memory device, the section separated sense amplifier (SA.sub.sec) 2 senses a logical condition of data by an amplitude of scores mV, and the main sense amplifier (SA.sub.main) 4 amplifies a sensed condition of data to an amplitude of "I.sub.O.R" to output, thereby suppressing a potential change to be smaller on the cascade wires D.sub.1 and *D.sub.1, and preventing as smaller as the deterioration of the invert speed on the basis of the parasitic capacitance between the semiconductor substrate and metal wiring of the cascade wires D.sub.1 and *D.sub.1.

The above condition will now be described more detail by using a parasitic capacitance shown in FIG. 1.

As shown in FIG. 1, the cascade wires D.sub.1 and *D.sub.1 have parasitic capacitance C.sub.D1 and *C.sub.D1, respectively. Accordingly, inverted time of respective potentials V.sub.D1 and *V.sub.D1 of the cascade wires D.sub.1 and *D.sub.1 are represented as follows:

where t.sub.O is inverted time, .DELTA.V.sub.D1 is a potential change in the cascade wire D.sub.1 and *D.sub.1.

Accordingly, the smaller the potential change .DELTA.V.sub.D1 is, the shorter the inverted time is, thereby enabling a high-speed read-out for the data.

However, since the data read-out cycle shows a tendency to be shortened by the high-speed operation in the conventional semiconductor memory device, the power sources V.sub.CC and V.sub.SS change easily by circuit noises activated in the read-out cycle, thereby providing new troublesome for obstructing the high-speed read--out of the data.

Namely, if the source v.sub.CC does not change, the sense output of the main sense amplifier (SA.sub.main) 4 complies with an inversion of the cascade wire D.sub.1 or *D.sub.1 with high fidelity as shown in FIG. 2.

However, when the power source V.sub.CC drops at inverting potentials in the data lines D.sub.IN and *D.sub.In, there occurs a defective phenomenon shown in FIGS. 3 and 4. This phenomenon can be analyzed as follows:

The amplifier first has a parasitic capacitance C.sub.D1 and *C.sub.D1 in the cascade wires D.sub.1 and *D.sub.1 and has a parasitic capacitance C.sub.Base between the semiconductor substrate and the bases of the transistors Tr.sub.B and Tr.sub.C.

When the power source V.sub.CC changes, the potential of the cascade wires C.sub.D1 and *C.sub.D1 and the base potential of the transistors Tr.sub.B and Tr.sub.C comply with the change of V.sub.CC. The base potential change time t.sub.1 of the transistors Tr.sub.B and Tr.sub.C and the potential change time t.sub.2 of the cascade wires C.sub.D1 and *C.sub.D1 are represented by the followings:

Accordingly, since the potentials C.sub.Base and C.sub.D1 (or *C.sub.D1) are the large factors to determine the potential change times t.sub.1 and t.sub.2, the relationship for sizes between the capacitances C.sub.Base and C.sub.D1 (or *C.sub.D1) results to generate the problem.

Namely, the capacitance C.sub.D1 (or *C.sub.D1) in the cascade wires D.sub.1 and *D.sub.1 is schematically constituted from a wiring capacitance C.sub.1 necessary for wiring the cascade wire D.sub.1 (or *D.sub.1) and a collector capacitance C.sub.j of the bipolar transistors which are necessarily added with each section cell array. Since a number of the sense amplifiers (SA.sub.sec) 2 increase according to the enlargement of the memory capacity and the cascade wires D.sub.1 and *D.sub.1 are formed for a long distance on the chip, both of the wiring capacitance C.sub.1 and the collector capacitance C.sub.j increase. Accordingly, a relationship for an amount of the capacitance C.sub.Base and C.sub.D1 (or *C.sub.D1) is "C.sub.Base <C.sub.D1 (or *C.sub.D1)" as clearly understood from a number of the sense amplifier (SA.sub.sec) 2. In this connection, there is a large difference between the capacitance C.sub.Base and C.sub.D1 (or *C.sub.D1) because C.sub.Base is 0.1 pF while C.sub.D1 (or *C.sub.D1) is 2-3 pF.

The relationship for an amount between capacitance C.sub.Base and C.sub.D1 (or *C.sub.D1) cause a relationship between the potential change times t.sub.1 and t.sub.2 to generate the difference (t.sub.1 <t.sub.2), thereby resulting a shortage condition in a voltage V.sub.BE between a base and emitter of the transistor Tr.sub.B (or Tr.sub.C) by the differential .DELTA.t. Here, the voltage V.sub.BE between a base and emitter can be represented as follows:

Where .alpha. is scores mV. In order to maintain an On state of the transistor Tr.sub.B (or Tr.sub.C), the relationship of "V.sub.BE >V.sub.BI +.alpha." should be satisfied. On the contrary, as shown in FIG. 4, when the base potential of the transistor Tr.sub.B (or Tr.sub.C) drops faster than the potential drop of the cascade wires D.sub.1 and *D.sub.1, thereby resulting a condition of "V.sub.BE <V.sub.BI +.alpha." during .DELTA.t, and causing the transistor Tr.sub.B (or Tr.sub.C) to be a cut-off condition. Therefore, as shown in FIG. 4(c), the sense outputs V.sub.Dout and *V.sub.Dout become an unfixed condition during the period of .DELTA.t, thereby disabling the amplifier from reading out the data. Accordingly, the read-out of the data delays by At and requires an extra time.

In conclusion, in FIG. 1, when the voltage V.sub.CC changes (increases or drops), the node n.sub.O changes in accordance with the change of the voltage V.sub.CC. However, the potential of the cascade wires D.sub.1 and *D.sub.1 changes slowly in comparison with the potential change of the node N.sub.O. An original potential difference between the base and emitter of the transistors Tr.sub.B and Tr.sub.C should be near V.sub.BI, but discrepancy between the changes of the node N.sub.O and the cascade wires D.sub.1 and *D.sub.1 on the basis of the change of the voltage V.sub.CC causes the potential difference between the base and emitter of both transistors Tr.sub.B and Tr.sub.C to be smaller than V.sub.BI (in case of V.sub.CC drop), and to be larger than V.sub.BI (in case of v.sub.CC increase). As a result, respective collector current of the transistors Tr.sub.B and Tr.sub.C flows little (when V.sub.CC drops), and flows too much (when V.sub.CC increases), so that the amplitude of output is not correct.

In view of the above-mentioned problem included in the conventional cascade sense amplifier, an object of the present invention is to provide a cascade sense amplifier which does not generate an OFF-state of a differential pair of a main sense amplifier even when the power source V.sub.CC drops, thereby preventing the read-out speed from delay so as to keep a high-speed read--out of the data.

The cascade sense amplifier of the present invention comprises a plurality of section separated sense amplifiers provided corresponding to each of section array and for sensing data stored in the section array, a cascade wiring portion for commonly connecting entire outputs of the plurality of sense amplifiers, a main sense amplifier for amplifying a sensed output sensed by the sense amplifiers through the cascade wiring portion, and a capacitance regulation element for regulating a capacitance of a base potential of a bipolar transistor constituting a data input portion of the main sense amplifier.

The capacitance regulation element can constitute a configuration in the manner that a capacitance forms corresponding to a potential the same as that mainly formed by the cascade wiring portion.

Furthermore, the capacitance regulation element may constitute by using an N-channel MOS transistor.

Still furthermore, a size of the capacitance regulation element is required to be determined in the manner that a base potential drop time of the bipolar transistor in the main sense amplifier is equal to the potential drop time of the cascade wiring portion when the higher potential drops.

According to the present invention, since the regulation of the capacitance of the base potential of the bipolar transistor constituting the data input portion of the main sense amplifier by the capacitance regulation element, can set the potential drop time of the cascade wiring portion equal to the base potential drop time when the source potential of the higher potential side drops, even when the power source V.sub.CC drops, there is no cut-off condition in the differential pair of the main sense amplifier, thereby preventing the read-out speed from delaying so as to maintain a high-speed reading of the data.

Furthermore, since the capacitance regulation element is specially formed by the MOS transistor, an extremely thin gate insulation layer thereof can be used as a dielectric, thereby suppressing the increase of the chip size.

As described above, since the capacitance of the base potential of the bipolar transistor constituting the data input portion of the main sense amplifier is regulated by the capacitance regulation element, it is possible to set the potential drop time of the cascade wiring portion equal to the base potential drop time of the bipolar transistors when the potential drops at the side of the high source potential, thereby preventing the differential pair of the main sense amplifier from generating the cut-off condition even when the source V.sub.CC drops, so as to prevent the decrease of the reading speed and maintain a high-speed reading of the data.

Furthermore, since the capacitance regulation element is specifically formed by the MOS transistor, the extremely thin gate insulation layer thereof can be used as a dielectric, thereby suppressing the increase of the chip size.

In the accompanying drawings:

FIG. 1 is a circuit diagram showing a conventional cascade amplifier with its capacitive constitution, which is constituted by bipolar transistors and MOS transistors and reads out data stored in section cell array of a semiconductor memory device;

FIG. 2 is a timing chart showing a waveform complying condition of a potential of a cascade wiring portion and a sense output of the main sense amplifier at inverting the data line potential when the source potential does not drop in the amplifier shown in FIG. 1;

FIG. 3 is a timing chart showing a waveform complying condition of the potential of the cascade wiring portion and the sense output of the main sense amplifier at inverting the data line potential when the source potential drops in the amplifier shown in FIG. 1;

FIG. 4 is a timing chart showing a waveform complying condition of the base potential drop of the input transistor and the potential drop of the cascade wiring portion which constitute the main sense amplifier when the source potential drops in the amplifier shown in FIG. 1;

FIG. 5 is circuit diagram showing a cascade sense amplifier according to an embodiment of the present invention with its capacitive constitution;

FIG. 6 is a timing chart showing a basic operation of the cascade sense amplifier shown in FIG. 5;

FIG. 7 is a timing chart showing a waveform complying condition of the base potential drop of the input transistor and the potential drop of the cascade wiring portion which constitute the main sense amplifier when the source potential drops in the amplifier shown in FIG. 5; and

FIG. 8 is a timing chart showing a waveform complying condition of the potential of the cascade wiring portion and the sense output of the main sense amplifier at inverting the data line potential when the source potential drops in the amplifier shown in FIG. 5.

There will be described in detail preferred embodiments of the present invention in reference with the attached drawings.

FIG. 5 shows a circuitry of the cascade sense amplifier according to an embodiment of the present invention. In this figure, elements the same as those shown in FIG. 1 are attached by the same symbols in FIG. 1 and description of these elements are omitted.

In FIG. 5, symbol C'.sub.Base denotes a capacitance regulation element according to the present invention. The capacitance regulation element C'.sub.Base is provided between a ground (GND) potential V.sub.SS and bases of the differential pair bipolar transistors Tr.sub.B and Tr.sub.C which constitute a data input terminal of the main sense amplifier (SA.sub.min). Accordingly, the capacitance regulation element C'.sub.Base is connected in parallel with the parasitic capacitance c.sub.Base.

In FIG. 5, symbols Ca show section cell array and each of the array Ca opposes a section divided sense amplifier SA.sub.sec. The sense amplifier SA.sub.sec includes a differential pair comprised of npn-type transistors Tr.sub.D and Tr.sub.E, and a constant current source comprised of an N-channel MOS transistor Tr.sub.F.

Emitters of the transistors Tr.sub.D and Tr.sub.E are commonly connected to a drain of the transistor Tr.sub.F which has a gate receiving a section cell array selection signal. A base of the transistor Tr.sub.E is connected to a data line D.sub.IN from the cell array Ca, while a base of the transistor Tr.sub.D is connected to a data line *D.sub.IN from the cell array Ca. By this, when the data line D.sub.IN is logic "1" and the data line *D.sub.IN is logic "0", and at the same time when the selection signal to the transistor Tr.sub.F is logic "1", the transistor Tr.sub.E is turned on and the transistor Tr.sub.D is turned off, thereby supplying only to the transistor Tr.sub.E a current having a value which is determined by the constant current source of the transistor Tr.sub.F. Further, when the data line D.sub.IN is logic "0" and the data line *D.sub.IN is logic "1", and at the same time when the selection signal to the transistor Tr.sub.F is logic "1", the transistor Tr.sub.E is turned off and the transistor Tr.sub.D is turned on, thereby supplying only to the transistor Tr.sub.D a current having a value which is determined by the constant current source of the transistor Tr.sub.F. The collectors of the transistors Tr.sub.D are commonly connected to a shared cascade wire D.sub.1 which is commonly provided in entire section divided sense amplifiers SA.sub.SEC, and also, the collectors of the transistors Tr.sub.E are commonly connected to a shared cascade wire *D.sub.1 which is commonly provided in entire section divided sense amplifiers SA.sub.SEC. A main sense amplifier SA.sub.main is provided at ends of the cascade wires D.sub.1 and *D.sub.1. The main sense amplifier SA.sub.main comprises NPN-type transistors Tr.sub.B and Tr.sub.C forming a differential pair, an NPN-type transistor Tr.sub.A which is connected by a diode connection and provided for a bias, a constant current source iO for biases corresponding to each of the transistors Tr.sub.B and Tr.sub.C of the differential pair, a constant current source iO' for a bias corresponding to the transistor Tr.sub.A, and output resistors R.

The transistor Tr.sub.A is inserted between a power source V.sub.CC and bases of the transistors Tr.sub.B and Tr.sub.C for biasing these transistors Tr.sub.B and Tr.sub.C in cooperation with the constant current source iO'. The cascade wire D.sub.1 is connected to an emitter of the transistor Tr.sub.B, thereby supplying to a collector of the transistor Tr.sub.B a current having a value which is determined by a constant current source iO and a collector current of the transistor Tr.sub.D the sense amplifier SA.sub.sec. The cascade wire *D.sub.1 is connected to an emitter of the transistor Tr.sub.C, thereby supplying to a collector of the transistor Tr.sub.C a current having a value which is determined by a constant current source iO and a collector current of the transistor Tr.sub.E of the sense amplifier SA.sub.sec.

The resistors R are respectively inserted into the transistors Tr.sub.B and Tr.sub.C and the power sources V.sub.CC, and each of the collector currents thereof is converted by each resistor R. An output of the resistor R on the side of the transistor Tr.sub.B is supplied to an output line D.sub.out, and an output of the resistor R on the side of the transistor Tr.sub.C is supplied to an output line *D.sub.out.

There is shown in FIG. 6 a circuit operation when one of the section cell arrays constructed in such the device is selected.

A value of "V.sub.CC -2V.sub.BI " shows a logic "1" in the data lines D.sub.IN and *D.sub.IN from the cell arrays. Here, V.sub.B1 means a built-in voltage of the PN-junction. A logic "0" is set to "(V.sub.CC -2V.sub.BI)-scores mV" in the data line D.sub.IN and *D.sub.IN from the cell array Ca. In FIG. 6(a) showing the potential of respective data lines D.sub.IN and *D.sub.IN, the item of (V.sub.CC -2V.sub.BI) corresponds to the logic "1", and the level of the side scores mV lower than (V.sub.CC -2V.sub.BI) corresponds to the logic "0".

In the cascade wires D.sub.1 and *D.sub.1, the logic "1" corresponds to (V.sub.CC -2V.sub.BI) on the basis of the built-in voltage of the transistors TF.sub.A and Tr.sub.B (or Tr.sub.C), and the logic "0" corresponds to the level scores mV lower than (V.sub.CC -2V.sub.BI).

Furthermore, in the sense output lines D.sub.out and *D.sub.out, the logic "1" is represented by (V.sub.CC -R.i.sub.O) and the logic "0" is represented by {V.sub.CC -R(i.sub.O +I.sub.O)}.

When the data line D.sub.IN is the logic "1" and the data line *D.sub.IN is the logic "0", since the transistor Tr.sub.E is turned on and the transistor Tr.sub.D is turned off as described above, the current I.sub.O flows in the transistor Tr.sub.E and does not flow in the transistor Tr.sub.D as shown in FIG. 6(b). Accordingly, since the current I.sub.O flows to the cascade wire *D.sub.1 and does not flow to the cascade wire D.sub.1, as shown in FIG. 6(c), the potential V.sub.D1 of the cascade wire D.sub.1 is (V.sub.CC -2V.sub.BI), and the potential *V.sub.D1 of the cascade wire *D.sub.1 is (V.sub.CC -2V.sub.BI -scores mV). Therefore, as shown in FIG. 6(d), the current I.sub.O of the cascade wire *D.sub.1 and the current i.sub.O of the constant current source flow in the transistor Tr.sub.C, and only the current i.sub.O of the constant current source flows in the transistor Tr.sub.B. Accordingly, the voltage drop is (i.sub.O +I.sub.O) at the collector resistor R of the transistor Tr.sub.B, and the potential *V.sub.Dout of the output line *D.sub.out is {(V.sub.CC -R(i.sub.O +I.sub.O)}. On the other hand, the voltage drop is R(i.sub.O) at the collector resistor R of the transistor Tr.sub.B, and the potential V.sub.Dout of the output line D.sub.out becomes (V.sub.CC -R.i.sub.O).

In such a condition, when the potential of the data line D.sub.IN is inverted into the logic "0" and the potential *D.sub.IN is inverted into the logic "1", the current of the transistor Tr.sub.D changes from zero to I.sub.O and the current of the transistor Tr.sub.E changes from I.sub.O to zero. Since the transistor Tr.sub.E does not supply the current, the cascade wire *D.sub.1 charges the potential of scores mV by the transistor Tr.sub.C to be (V.sub.CC -2V.sub.BI). On the other hand, since the transistor Tr.sub.D starts to flow the current I.sub.O, the cascade wire D.sub.1 drops the potential of scores mV from (V.sub.CC -2V.sub.BI). Therefore, the transistor Tr.sub.C has the flowing current i.sub.O of the constant current source, and the transistor Tr.sub.B has the flowing current I.sub.O of the cascade wire D.sub.1 and the current i.sub.O of the constant current source. Accordingly, the voltage drop is "R.i.sub.O " at the collector resistor R of the transistor Tr.sub.C, and the potential *V.sub.Dout of the output line *D.sub.out is (V.sub.CC -R.i.sub.O). On the other hand, the voltage drop is "R.(i.sub.O +I.sub.O)" at the collector resistor R of the transistor Tr.sub.B, and the potential V.sub.Dout of the output line D.sub.out is {V.sub.CC -R(i.sub.O +I.sub.O)}.

The above-mentioned capacitance regulation element C'.sub.Base is comprised of an N-channel MOS transistor Tr.sub.C having a gate connected to the bases of the transistors Tr.sub.B and Tr.sub.C, and both a source and a drain connected to the ground (GND) potential. Accordingly, the dielectric of the element C'.sub.Base is comprised of the gate oxide layer of the transistor Tr.sub.G. The capacitance regulation element C'.sub.Base has a capacitive value which is set in the manner that the potential drop time of the bases in the transistors Tr.sub.B and Tr.sub.C is equal to the potential drop time of the cascade wires D.sub.1 and *D.sub.1 when the potential of the higher potential side drops.

Therefore, as shown in FIG. 7, in the cascade sense amplifier of this embodiment, even though the power source V.sub.CC drops, the drop time t.sub.1 of the base potential V.sub.B is equal to the potential drop time t.sub.2 of the cascade wires D.sub.1 and *D.sub.1 when the source V.sub.CC drops.

By this, even though the power source V.sub.CC drops, it is possible to satisfy the relationship of "V.sub.BE >V.sub.BI +.alpha." with respect to the voltages V.sub.BE between the bases and emitters of the transistors Tr.sub.B and Tr.sub.C, thereby maintaining an ON-condition of the transistors Tr.sub.B and Tr.sub.C.

Accordingly, as shown in FIG. 8, an output of the main sense amplifier is stable, and there is no cut-off condition in the transistors TF.sub.B and Tr.sub.C even though the power source V.sub.CC drops, so as to prevent the delay of the read-out speed, thereby enabling a high speed and high sense reading of the data.

Furthermore, since the capacitance regulation element is specifically comprised of the MOS transistor having a gate oxide layer constituted by a thin dielectric, the element occupies only a small area, thereby preventing the chip size from increasing.

Especially, since the MOS transistor is used as the capacitance regulation element, it is possible to realize a miniaturization of the capacitance regulation element according to a miniaturization of the MOS transistor. Accordingly, the capacitance regulation element contributes a further miniaturization and higher integration of the chip size in the future, thereby having an extreme promisingness and a higher usefulness.

Though there is described the embodiment of this invention, the present invention is not limited in the above embodiment.

For example, even though the amplifier of the above embodiment has the capacitance regulation element comprised of the N-channel MOS transistor, the element may be comprised of a P-channel MOS transistor. Furthermore, the element is not limited in the MOS, the element may adopt other transistors if they are at least metal insulation semiconductor (MIS) type transistors.

Furthermore, the element is not limited in the transistors, and the element may be constituted by a capacitor in which metal electrodes the same as the cascade wiring portion are formed on the substrate, or by a trench type capacitor. In conclusion, the capacitance regulation element may be formed by any kind of formations.

Still furthermore, even though the capacitance regulation element of the above-embodiment is constituted by setting a capacitance value in the manner that the drop time t.sub.1 of the base potential of the bipolar transistor in the main sense amplifier is equal to the potential drop time t.sub.2 of the cascade wiring portion, the capacitance value may be set to "t.sub.1 >t.sub.2 ".