Analog/Digital Converter With Digital Automatic Gain Control

This invention relates to an analog/digital converter and, more particularly, to an analog-digital converter ideal for applications where an AGC (Automatic Gain Control) circuit is realized by digital signal processing.

FIG. 1 illustrates an example in which an AGC circuit is constructed in a conventional digital signal processing unit in order to convert analog data into corresponding digital data.

The digital signal processing unit shown in FIG. 1 includes a variable-gain amplifier 101 for amplifying input analog data (an analog voltage) at a predetermined gain in accordance with control executed by a digital signal processor (hereinafter referred to as a "DSP") or microprocessor (hereinafter referred to as an "MPU") 103, an ordinary well-known analog/digital (hereinafter referred to as "A/D") converter 102, and the DSP or MPU 103.

The operation of an AGC circuit which includes the analog/digital converter in the conventional apparatus of this kind will be described.

First, the DSP or MPU 103 initializes (e.g., sets to "1") the gain of the variable-gain amplifier 101 and calculates the average value of the square of the output data from the A/D converter 102. If this value is less than the set value, control for raising the gain of the variable-gain amplifier 101 is performed and the average value of the square of the output data from the A/D converter 102 is calculated again. By repeating this operation, the average value of the square of the output data from the A/D converter 102 eventually becomes larger than the predetermined set value. When this occurs, the gain of the variable-gain amplifier 102 is fixed and AGC processing is performed in accordance with the processing executed by the DSP shown in FIG. 2.

In the operation of the circuit shown in FIG. 2, the average value of the square of the output signal is obtained by a squaring unit 205 and an averaging unit 206. The average value of the square and the set value are added by an adder 204. The constant of a multiplier 201 is controlled using a register 202 and an adder 203 in such a manner that the difference, namely the error, between the average value of the square and the set value becomes "0". Thus, the average value of the outputs attains a constant level.

If, in the digital signal processing unit described above, the number of bits corresponding to the dynamic range of the analog input voltage is greater than the number of bits corresponding to the operational precision of the DSP 103 that is necessary for signal processing, first the analog voltage is amplified to a level capable of being computed by the DSP 103 under coarse control performed by the variable-gain amplifier 101, and then AGC processing is performed under fine control based upon the processing of the DSP 103.

In general, the variable-gain amplifier 101 is capable of being set to any of a number of gains (e.g., 1.times., 2.times., 4.times., 8.times., . . . , etc. ).

A disadvantage encountered in the prior art described above is that an analog circuit such as the variable-gain amplifier 101 is required. This is disadvantageous because the circuit has a complicated construction and its performance is influenced by the characteristics of the various elements that construct it.

Accordingly, in order to widen the dynamic range of the input voltage level, an arrangement should be adopted in which the variable-gain amplifier is eliminated, the precision of the A/D 102 is raised to increase the number of output bits and all AGC processing is performed in accordance with the processing executed by the DSP 103. The foregoing problems can be solved by adopting such an arrangement. Since an A/D converter having a large number of output bits has recently become available at low cost, adopting the above-described arrangement is considered to be effective.

However, if there is an increase in the number of output bits of the A/D converter 102, the number of operational bits of the DSP 103 also must be increased. In addition, even if the AGC processing shown in FIG. 2 is performed upon increasing the number of operational bits, the time needed for the gain to converge is prolonged greatly in a case where the dynamic range of the input data has been widened. This represents another problem.

In order to solve this latter problem, AGC of the kind shown in FIG. 3 can be adopted. However, when AGC processing of this type is realized by a DSP, an enormous amount of processing is required to be performed by a divider 301 and a square-root unit 302. As a consequence, the time required for processing is great and this arrangement does not offer a truly practical solution.

An object of the present invention is to provide an analog/digital converter in which AGC based upon simple processing is capable of being performed without using an amplifier composed of complicated analog circuitry, and in which signal processing is carried out using an inexpensive processor.

According to the present invention, the foregoing object is attained by providing an analog/digital converting unit for converting analog data into corresponding digital data, an output unit for bit-shifting and outputting the digital data resulting from the conversion performed by the analog/digital converting unit, and a control unit for externally controlling the amount of bit shift performed by the output unit.

In the arrangement described above, the A/D converter used in digital signal processing is provided with the function for shifting and outputting the digital data resulting from the conversion, and the function for externally setting the number of bits shifted. This makes it possible to reduce the circuitry and amount of processing required in the AGC of the overall system.

Another object of the present invention is to provide an analog/digital converter which comprises analog/digital converting means for converting an analog input voltage into corresponding digital data, detecting means for detecting a maximum value of analog input voltage, amplifying means for amplifying voltage in dependence upon the maximum value detected by the detecting means, and output means for shifting and outputting, to an external system, the digital data from the analog/digital converting means in dependence upon the degree of amplification of the voltage amplified by the amplifying means.

Still another object of the present invention is to provide an analog/digital converter capable of increasing the apparent number of output bits of digital data, which results from A/D conversion, without diminishing processing speed.

A further object of the present invention is to provide an analog/digital converter capable of reducing the burden on a DSP through simple AGC processing and in a short processing time.

Yet another object of the present invention is to provide an analog/digital converter for use in a digital AGC circuit, wherein the converter is capable of calculating the average value of absolute values of a certain number of items of data contained in A/D-converted input data, and of performing AGC processing under coarse control based on simple shift processing of data conforming to the calculated average value.

Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.

FIG. 1 is a block diagram illustrating a digital signal processing unit according to the prior art;

FIG. 2 is a block diagram for describing processing executed by a DSP according to the prior art;

FIG. 3 is a block diagram for describing processing executed by a DSP according to another example of the prior art;

FIG. 4 is a block diagram illustrating a digital signal processing unit according to a first embodiment of the present invention;

FIG. 5 is a block diagram illustrating the construction of a second embodiment according to the present invention;

FIG. 6 is a timing chart associated with a latch circuit of the embodiment shown in FIG. 5;

FIG. 7 is a circuit diagram showing a third embodiment of the present invention;

FIG. 8 is a diagram showing an example of a bit shifter illustrated in FIG. 7; and

FIG. 9 is a block diagram showing the construction of a digital signal processing unit having the circuit of FIG. 7.

Embodiments according to the present invention will now be described in detail with reference to the drawings.

FIG. 4 is a diagram which best shows the characterizing features of an A/D converting unit according to the first embodiment of the present invention. In FIG. 4, numeral 400 denotes an A/D converting unit, and 410 a DSP. It should be noted that the device connected to the A/D converting unit 400 in this embodiment is not limited to the DSP 410. A microprocessor can be connected to the A/D converting 400 if desired.

The A/D 400 includes an A/D converter 401 for converting an analog input voltage into corresponding digital data, a bit shifting circuit 402 for bit-shifting and outputting the digital data resulting from the conversion performed by the A/D converter 401, this output serving as the output of the A/D converting unit 400, and a register 403 for setting the shift quantity of the bit shifting circuit 402, the number of bits shifted being set from outside (from the DSP 410). The bit shifting circuit 402 outputs the input data from the A/D converter 401 upon performing a bit shift by an amount set in the shift-quantity setting register 403.

In the operation of the A/D converting unit 400 constructed as set forth above, if the number of bits desired to be shifted in the bit shifting circuit 402 is set in the shift-quantity setting register 403 from the outside (from the DSP 410), the bit shifting circuit 402 will output the A/D-converted data from the A/D converter 401 upon shifting this data by the set number of bits.

More specifically, whereas the DSP 103 of FIG. 1 controls the gain of the variable-gain amplifier 101, the DSP 410 in FIG. 4 controls the amount of shift performed by the bit shifting circuit 402.

For example, if the DSP 410 sets "+1" in the shift-quantity setting register 403, the input data to the bit shifting circuit 402 from the A/D converter 401 is outputted upon being shifted by one bit toward the MSB side. Similarly, if the DSP 410 sets "+3" in the shift-quantity setting register 403, the input data to the bit shifting circuit 402 from the A/D converter 401 is outputted upon being shifted by three bits toward the MSB side. In either case, "0" enters the portion of the bit shifted on the LSB side in the shifting circuit 402 .

If "-2" has been set in the shift-quantity setting register 403, the input data to the bit shifting circuit 402 is outputted upon being shifted by two bits toward the LSB side. At this time, "0"s enter the two bits on the MSB side.

AS a result of these operations, it is possible to output the A/D-converted data upon multiplying it by two (+1 bit), by eight (+3 bits) and by one quarter (-2 bits).

Thus, if the A/D converting unit of the present embodiment is employed, AGC control of the DSP 410 can be carried out digitally. Moreover, variable control of the outputted digital quantity can be performed by the A/D converting unit 400.

Therefore, in accordance with this embodiment, an operation equivalent to that of the digital signal processing unit having the construction of FIG. 1 can be realized by relying upon the DSP 410 and A/D converting unit 400.

More specifically, in the present embodiment, control of the gain of the variable-gain amplifier 101 shown in FIG. 1 is capable of being performed merely by controlling the amount of shift with regard to the output of the A/D converter, as shown in FIG. 4.

First, the DSP 410 initializes (e.g., sets to "1") the shift-quantity of the shift-quantity setting register 403 and calculates the average value of the square of the output data from the bit shifting circuit 402. If this value is less than the set value, the DSP 410 controls for raising the shift-quantity of the shift-quantity setting register 403 and calculates the average value of the square of the output data from the bit shifting circuit 402 again. By repeating this operation, the average value of the square of the output data from the bit shifting circuit 402 eventually becomes larger than the predetermined set value. When this occurs, the shift-quantity of the shift-quantity setting register 403 is fixed and detailed AGC processing is performed in accordance with the processing executed by the DSP 410 in FIG. 2.

As a result of the foregoing, it is no longer necessary to provide the circuitry of the portion corresponding to the variable-gain amplifier for the analog voltage, unlike the prior art.

As described above, a digital signal processing unit is constructed using an A/D converter having a simple bit-shift control circuit. As a result, outstanding actions and effects can be obtained, namely the fact that AGC implemented by simple processing is capable of being performed without using an amplifier composed of complicated analog circuitry.

In addition, since AGC relying upon simple processing is possible without using an amplifier composed of complicated analog circuitry, signal processing can be carried out using a less costly processor.

FIG. 5 is a diagram illustrating the construction of a second embodiment according to the present invention.

The circuitry shown in FIG. 5 includes resistors 501, 502 having equal resistance values, a resistor 503 having a resistance value twice that of resistor 501, and a resistor 504 having a resistance value four times that of resistor 501. One end of resistor 504 is connected to a maximum voltage Vref capable of being A/D-converted by an A/D converter 526. Also included in the circuitry are comparators 505, 506 and 507, flip-flops (hereinafter referred to as "FF"s) 508-513, 521 and 522, inverters 514-516, AND gates 517-520, a frequency-divider circuit 523, an oscillator 524 for generating a reference clock, a variable-gain amplifier 525, an A/D converter 526 for converting analog data into the corresponding digital data, and a bit shifting circuit 527.

The analog input voltage to be A/D-converted enters the variable-gain amplifier 525 as well as one input terminal of each of the comparators 505, 506 and 507. Since one end of the resistor 504 is connected to the maximum voltage Vref capable of being A/D-converted, 1/2 Vref, 1/4 Vref and 1/8 Vref enter the other input terminal of comparators 507, 506 and 505, respectively. When the analog input voltage exceeds 1/2 Vref, the outputs of the comparators 507, 506 and 505 all rise.

If the analog input voltage is greater than 1/4 Vref and less than 1/2 Vref, the outputs of comparators 505 and 506 rise but the output of the comparator 507 does not. If the analog input voltage is greater than 1/8 Vref and less than 1/4 Vref, the output solely of comparator 505 rises and the outputs of the comparators 506, 507 do not. If the peak value of the analog input voltage is less than 1/8 Vref, none of the outputs of the comparators rise. The outputs of the comparators 505, 506 and 507 are connected to the clock terminals of respective FFs 508, 509 and 510. The D terminals of the FFs 508-510 are all set to the high level. As a consequence, the FFs 508-510 are set by the leading edges of the outputs from the comparators 505-507, respectively.

The oscillator 524 constantly generates a reference clock shown at F in FIG. 6. The reference clock is frequency-divided by the frequency-divider circuit 523 so that a latch clock signal for the FFs 511-513 is produced as shown at A in FIG. 6. The latch clock signal is supplied to the D terminal of FF 522, whereby the FF 522 outputs a signal, shown at B in FIG. 6, that lags one reference clock pulse behind the latch clock signal. Furthermore, the output signal from the FF 522 is supplied to the D terminal of the FF 521, whereby the FF 521 Outputs a signal, shown at C in FIG. 6, that lags one reference clock pulse behind the output signal from FF 522 (two reference clock pulses behind the latch clock signal). The Q output from the FF 522 as shown at D in FIG. 6 and the Q output from the FF 521 enter the AND gate 520, the output whereof constitutes a reset signal for the FFs 508-510. The reset signal, which is shown at E in FIG. 6, has a pulse width equivalent to one clock of the reference clock pulse.

As a result, after the FFs 508-510 have been reset by the leading edge of the reset signal E, they attain the set state when the leading edges of the outputs from the comparators 505-507 arrive before the latch clock A rises. Thereafter, when the latch clock signal A, which is the output of the frequency divider 523, rises, the states of the FFs 505-507 are latched in the FFs 511-513, respectively.

The outputs of the FFs 511-513 are connected to the respective inverters 514-516 and respective AND gates 517-519 to be converted into bit-shift designating signals for the bit shifting circuit 527 and amplification designating signals for the variable-gain amplifier 525.

More specifically, if the FFs 511-513 have been set, the AND gates 517-519 are disabled so that a 0 bit-shift designating signal is delivered to the bit shifting circuit 527 and a "1.times." amplification designating signal to the variable-gain amplifier 525. When only FFs 511 and 512 have been set, the AND gate 519 is enabled so that a 1 bit-shift designating signal is delivered to the bit shifting circuit 527 and a "2.times." (twofold) amplification designating signal to the variable-gain amplifier 525. When only the FF 511 has been set, the AND gate 518 is enabled so that a 2 bit-shift designating signal is delivered to the bit shifting circuit 527 and a "4.times." (fourfold) amplification designating signal to the variable-gain amplifier 525. When none of the FFs 511-513 has been set, the AND gate 517 is enabled so that a 3 bit-shift designating signal is delivered to the bit shifting circuit 527 and an "8.times." (eightfold) amplification designating signal to the variable-gain amplifier 525.

It is assumed that the output of the frequency divider 523 is such that the time from the leading edge of the reset signal E to the leading edge of the latch clock signal A is suitably selected to be several times to several hundred times the conversion period of the A/D converter.

The operation of the embodiment constructed as set forth above will now be described.

If the maximum value of the analog input voltage to be A/D-converted exceeds 1/2 Vref in the interval from the leading edge of the reset signal E to the leading edge of the latch clock signal A in FIG. 6, all of the outputs of comparators 507, 506, 505 rise, all of the FFs 508-510 are set, and all of the FFs 511-513 are set at this time. As a result, the gain input of the variable-gain amplifier 525 is 1.times., the output of the variable-gain amplifier 525 remains at the analog input voltage, this value is A/D-converted and the resulting digital value is inputted to the bit shifting circuit 527.

The shift input of the bit shifting circuit 527 is only a 0 bit-shift input corresponding to the gain input 1 of the variable-gain amplifier 525, and therefore the output of the A/D amplifier 526 is delivered intact to the outside as digital data.

If the maximum value of the analog input voltage to be A/D-converted is less than 1/2 Vref but exceeds 1/4 Vref in the interval from the leading edge of the reset signal E to the leading edge of the latch clock signal A in FIG. 6, the outputs of comparators 505, 506 rise, the FFs 508, 509 are set, and the FFs 511, 512 are set at this time. As a result, the gain input of the variable-gain amplifier 525 becomes 2.times., the output of the variable-gain amplifier 525 becomes double the analog input voltage, this value is A/D-converted and the resulting digital value is inputted to the bit shifting circuit 527.

The shift input of the bit shifting circuit 527 is only a 1 bit-shift input, and therefore the output of the A/D amplifier 526 is delivered to the outside as digital data upon being shifted by one bit to the LSB side.

Similarly, if the maximum value of the analog input voltage to be A/D-converted is greater than 1/8 Vref and less than 1/4 Vref in the interval from the leading edge of the reset signal E to the leading edge of the latch clock signal A in FIG. 6, solely the output of comparator 505 rises, the output of FF 508 attains the high level, and the FF 511 is set at this time. As a result, the gain input of the variable-gain amplifier 525 becomes 4.thrfore., the output of the variable-gain amplifier 525 becomes four times the analog input voltage, this value is A/D-converted and the resulting digital value is inputted to the bit shifting circuit 527.

The shift input of the bit shifting circuit 527 is only a 2 bit-shift input, and therefore the output of the A/D amplifier 526 is delivered to the outside as digital data upon being shifted by two bits to the MSB side.

Further, if the peak value of the analog input voltage to be A/D-converted is less than 1/8 Vref in the interval from the leading edge of the reset signal E to the leading edge of the latch clock signal A in FIG. 6, the gain input of the variable-gain amplifier 525 becomes 8.times., and therefore the bit shifting circuit shifts the A/D-converted digital data three bits to the MSB side before outputting this data.

By virtue of this arrangement, the analog voltage which enters the A/D converter is scaled optimally at all times, the accuracy of the outputs bits is maintained and the number of bits in the output digital data can be enlarged.

It should be noted that the code bits enter as is on the MSB side shifted by the bit shifting circuit.

The present invention is not limited to the example described above. For example, by increasing the circuitry of the peak detecting section, the number of bits can be increased at will.

FIG. 7 is a circuit diagram showing the construction of a digital AGC circuit according to the third embodiment. In FIG. 7, numeral 701 denotes a register for temporarily storing the input data converted into a digital signal. The output data from the A/D converter is written in the register 701 in the form of a two's-complement, by way of example. With the exception of the MSB, the output bits of the register 701 are connected to the respective bits on the input side of a bit shifter 713. The MSB on the output side of the register 701 is connected to one input terminal of each of exclusive-OR gates 21-24 and to the MSB on the input side of the data input unit of the DSP. The four bits following the MSB on the output side of the register 701 are connected to the other input terminal of each of the exclusive-OR gates 21-24, respectively. The outputs of the exclusive-OR gates 21-24 enter the respective 3rd through 0th (LSB) bits of a cumulative adder 703. The 7th bit on the output side of the cumulative adder 703 is connected to one input terminal of an OR gate 710 and to the input side of an inverter 704. The 8th bit on the output side of the cumulative adder 703 is connected to the input side of the DSP and to the other input terminal of the OR gate 710. The 6th bit on the output side of the cumulative adder 703 is connected to one input terminal of an AND gate 707 and to the input side of an inverter 705. The 5th bit on the output side of the cumulative adder 703 is connected to one input terminal of an AND gate 708 and to the input side of an inverter 706. The output side of the OR gate 710 is connected to the 0th bit input side on the of a latch 711, the 1st bit of the latch 711 on its input side is connected to the output side of the AND gate 707, the 2nd bit of the latch 711 on its input side is connected to the output side of the AND gate 708, and the 3rd bit of the latch 711 on its input side is connected to the output side of the AND gate 709. The four bits output from the latch 711 is connected to the shift-quantity control input of the bit shifter 713 and, at the same time, to the input side of the DSP. The output side of the bit shifter 713 is connected to the input side of the DSP. A data-write pulse from the A/D converter 401 enters the register 701 from an input port (W) for the data-write pulse, and enters the cumulative adder 703 from an input port (A) for an adding pulse. The data-write pulse is inputted also to a clock input port of a variable frequency divider 712. The frequency-dividing ratio of the variable frequency divider 712 is set by the data output of the DSP, which is inputted to the frequency divider. The output of the frequency divider 712 enters the latch 711 as a latch pulse and is inputted also to a pulse generator 714. The output of the pulse generator 714 is connected to a clear input port (C) of the cumulative adder. A logic circuit 702 comprising the gates 21-24, the cumulative adder 703, and a logic circuit 715 comprising the inverters 704-706 and the gates 707-710 construct arithmetic means for calculating the average value of absolute values possessed by data composed of a set number of samplings from the input data stored in the register 701. The bit shifter 713 acts as shifting means for outputting the data, which has been stored in the register 701, upon shifting this data in dependence upon the calculated average value.

In the circuit constructed as set forth above, first the frequency dividing ratio of the variable frequency divider 712 is set (to 32, for example) by the DSP. Next, at the leading edge of the data-write pulse from the A/D converter 401, the A/D-converted data represented by the two's-complement is written in the register 701. The four-bit data following the MSB of this data is inverted by the logic circuit 702 when the MSB of the register 701 is 1, namely when the A/D-converted data is a negative number. When the A/D-converted data is a positive number, the aforementioned four-bit data enters the cumulative adder 703 intact. In other words, the absolute value of the high-order bit of the output data from the register 701 is obtained. This value is added to the data in the cumulative adder 703 at the leading edge of the write pulse. This adding operation is repeated a number of times set in the variable frequency divider 712. If the contents of the 8th through 0th bits of the cumulative adder 703 are, say, "001111111" as a result of the cumulative addition, only the output of AND gate 707 becomes logical "1"; the outputs of OR gate 710 and AND gates 708, 709 become logical "0". If the 7th and 8th bits of the results of addition performed by the cumulative adder 703 become logical "1", then only the output of the OR gate 710 rises to logical "1" and the outputs of AND gates 707, 708 and 709 go to logical "0". In other words, in accordance with the magnitude of the results of addition performed by the cumulative adder 703, only one of the outputs from the gates 707, 708, 709, 710 goes to logical "1". The values of these four bits are latched in the latch 711 when the cumulative addition has been performed the number of times set in the variable frequency divider 712. Thereafter, a clear pulse is generated by the pulse generator 714 to clear the contents of cumulative adder 703 to zero, after which addition starts again. Thus, operation is such that an average value of 32 cycles of the data inputted from the A/D converter 401 is calculated and one bit from among the output bits of the latch 711 becomes logical "1" in dependence upon the average value. Then, in dependence upon the bit that has gone to logical "1", the bit shifter 713 shifts the data of register 701 to the MSB side and then outputs the result to the DSP. In accordance with this embodiment, the operation is such that no shift is performed when the 0th bit of latch 711 is "1"; a one-bit shift is performed when the 1st bit of latch 711 is "1"; a two-bit shift is performed when the 2nd bit of latch 711 is "1"; and a three-bit shift is performed when the 3rd bit of latch 711 is "1".

By employing the circuit of FIG. 7, as described above, gains of 1.times., 2.times., 4.times. and 8.times. can be obtained with regard to A/D-converted digital data, without using large-scale circuitry such as a multiplier, in dependence upon the average value of absolute values possessed by data composed of a set number of samplings from the digital data.

FIG. 8 illustrates an example of the construction of the bit shifter 713. Each of the bit shifting circuit 402 in FIG. 4 and the bit shifting circuit 527 have the same constitution as the bit shifting circuit 713 has. The operation regarding a 0.sub.0 output will be described first. In FIG. 8, 801 through 804 denote tri-state output buffers, the outputs of which are all supplied to a 0.sub.0 bit on the output side. An I.sub.0 bit on the input side enters the buffer 801, and an I.sub.1 bit that is one bit lower in order than the I.sub.0 bit enters the buffer 802. An 12 bit that is two bits lower in order than the I.sub.2 bit enters the buffer 803, and an 13 bit that is three bits lower in order than the I.sub.0 bit enters the buffer 804. Unshifted data enters a control input terminal of the buffer 801, and one-bit shift data, two-bit shift data and three-bit shift data enters control input terminals of the buffers 802, 803 and 804, respectively. The wiring and connections of these inputs and outputs is performed similarly for each and every bit, as illustrated. If the signals are applied in such a manner that any one of the four shift-control signals in this circuit becomes logical "1" and the others logical "0", the input data can be outputted upon being shifted by the corresponding number of bits among bits 0, 1, 2 and 3. The circuitry need not be made large in scale.

FIG. 9 is a block diagram illustrating the construction of a digital signal processing system equipped with AGC circuit shown in FIG. 7. Here a digital AGC circuit 903 shown in FIG. 7 is interposed between an A/D converter 901 and a DSP 902.

In a case where the DSP 902 uses the digital AGC circuit 903 according to this embodiment, data subjected to digital AGC processing by coarse control can be obtained by setting the frequency dividing ratio of the variable frequency divider 712 shown in FIG. 7. This makes it possible for gain to converge at high speed through a simple method requiring only a small amount of calculation in the AGC processing which carries out fine control by the DSP 902. As a result, the burden on the DSP 902 is reduced as well.

In a case where it is desired that the DSP 902 measure the actual value of input data, it will suffice to read in the four output bits, i.e., the shift control bits, of the latch 711 shown in FIG. 7, and subject the output of the bit shifter 713 to a reverse shift.

Though the bits which add the absolute values are the four bits following the MSB, any number of bits may be used.

In addition, the number of bits of the cumulative adder 703 may be freely selected in dependence upon the number of samplings for which averaging is desired and the value of the input data.

Furthermore, the number of bits of the circuit which decides the amount of shift may be changed in dependence upon the amount of shift desired. Shift control may be changed every two bits or more, not every bit. This can readily be realized if the circuit of FIG. 8 is modified.

As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.