Method of Making Memory Cell Capacitor

The present invention relates to memory cell capacitors and fabrication methods thereof, and in particular to a capacitor of large capacitance and improved uniformity.

In dynamic random access memory (DRAM) fabrication technology, continuous efforts are being made to build a capacitor of larger capacitance in a smaller space.

FIGS. 1(A)-(C) illustrate one of the conventional techniques for forming a DRAM capacitor. The fabrication process of such a DRAM capacitor will be explained briefly below.

As shown in FIG. 1(A), after forming necessary elements on semiconductor substrate 1, the overall surface is coated with insulation layer 2. A contact hole for making contact between a source/drain region in semiconductor substrate 1 (not explicitly shown) and a capacitor electrode is formed by application of a photolithographic or photo-etching process to predetermined portions of insulating layer 2. Continually, doped polysilicon is deposited by a low pressure chemical vapor deposition (LPCVD) process at a temperature of about 600.degree. C., and a portion of a capacitor storage node is patterned.

Thereafter, as shown in FIG. 1(B), hemispherical polysilicon layer 4 (which has many hemispherical domes on the surface) is deposited under the conditions of pressure of about 1.0 torr, at a temperature of about 550.degree. C., and an ambience of SiH.sub.4 (20%) gas diluted with "He" or helium gas.

A capacitor node is formed by etching back hemispherical polysilicon layer 4, such as by application of a reactive ion etching (dry type of etching) in an atmosphere of "HBr" gas, as illustrated in FIG. 1(C).

Thereafter, the capacitor is fabricated by forming a dielectric layer and a plate electrode of polysilicon.

This conventional method of increasing the surface of the capacitor node by using a hemispherical polysilicon layer typically is insufficient. That is, in the case of a hemispherical polysilicon node compared with a planar node, the increase of the surface area of the node is 2.pi.r.sup.2 /.pi.r.sup.2 =2; it is up to about 2 at best, and it is impossible to be more.

The present invention is intended to overcome the above described limit in increasing the surface area of a capacitor electrode.

Accordingly, it is an object of the present invention to provide a method for making a memory cell capacitor which comprises the steps of: (1) forming a capacitor node contact hole after making necessary elements in semiconductor substrate 1, by depositing an insulation layer 2 on the whole surface of the wafer (semiconductor substrate 1), and etching a predetermined portion of insulating layer 2 by a photolithographic process; (2) depositing doped polysilicon layer 3, thereby making a contact for connecting the capacitor electrode and a source/drain region; (3) depositing silicon nitride layer 5 and silicon oxide layer 6, and opening window 55 by a photolithographic process on portions thereof where a capacitor storage electrode is to be formed; (4) depositing hemispherical polysilicon layer 4 having many peaks 44 and valleys 42 on exposed surfaces of polysilicon layer 3, silicon nitride layer 5, and silicon oxide layer 6; (5) depositing silicon oxide layer 62 and etching back silicon oxide layer 62 so that it remains selectively in valleys 42 of hemispherical polysilicon layer 4; (6) forming a plurality of polysilicon projections 32 from polysilicon layer 3 by dry etching hemispherical polysilicon layer 4 and polysilicon layer 3, using the remaining portions of silicon oxide layer 62 as a mask; (7) removing silicon oxide layers 6 and 62 by a wet etching process; (8) depositing polyimide layer 7 and etching back polyimide layer 7 so as to expose the surface of silicon nitride layer 5; and (9) forming capacitor storage electrode 36 by removing silicon nitride layer 5 by a wet etching process, etching polysilicon layer 3 using polyimide layer 7 as a mask, and removing polyimide layer 7. In step (2), doped polysilicon layer 3 is deposited to a thickness of about 2000 .ANG. or more, by applying a LPCVD process at a temperature of about 500.degree. C. or more. In step (4), the hemispherical polysilicon deposition process is carried out under conditions of an atmosphere of SiH.sub.4 gas, and a pressure of about 0.1-10 torr at a temperature of about 560.degree.-600.degree. C., and the thickness of hemispherical polysilicon layer 4 is about 1000 .ANG., or, alternatively, the hemispherical polysilicon deposition process is carried out under conditions of an atmosphere of Si.sub.2 H.sub.6 gas, and a pressure of about 0.1-1 torr at a temperature of about 570.degree.-610.degree. C., and the thickness of hemispherical polysilicon layer 4 is about 1000 .ANG..

Another object of the present invention is to provide a memory cell capacitor comprising a cylindrical capacitor storage node which is located above a capacitor node contacted with a source/drain region, the cylindrical capacitor storage node having a plurality of projections standing vertically upward from the substrate.

The above object and other advantages of the present invention will become more apparent by describing in detail the preferred embodiments of the present invention with reference to the attached drawings in which:

FIGS. 1(A) to (C) are sectional views of a memory cell portion of a wafer for illustrating the steps of a conventional fabrication method; and

FIGS. 2(A) to (I) are sectional views of a memory cell portion of a wafer for illustrating the steps of a fabrication method in accordance with the present invention.

As shown in FIG. 2(A), after making necessary elements such as source/drain regions in semiconductor substrate 1, the overall surface is coated with insulation layer 2, and contact hole 31 for making contact between a source/drain region (not explicitly shown) and a capacitor electrode is formed by application of a photolithographic or photo-etching process to predetermined portions of insulating layer 2.

Next, doped polysilicon layer 3 is deposited to a thickness of about 2000 .ANG. or more, by application of a LPCVD process at a temperature of about 500.degree. C. or more.

Thereafter, as shown in FIG. 2(B), silicon nitride layer 5 and silicon oxide layer 6 are deposited, and window 55 is opened by a conventional photolithographic process in portions of silicon nitride layer 5 and silicon oxide layer 6 where a capacitor storage electrode (or node) is to be formed.

Next, hemispherical polysilicon layer 4 having many peaks 44 and valleys 42 is deposited on the exposed surfaces of polysilicon layer 3, silicon nitride layer 6, and silicon oxide layer 5, to a thickness of about 1000 .ANG..

In accordance with preferred embodiments of the present invention, the hemispherical polysilicon deposition process is carried out under conditions of either:

(i) in an atmosphere of SiH.sub.4, a pressure of about 0.1-10 torr, at a temperature of about 560.degree.-600.degree. C.; or

(ii) in an atmosphere of Si.sub.2 H.sub.6, a pressure of about 0.1-1 torr, at a temperature of about 570.degree.-610.degree. C.

Thereafter, CVD oxide layer 62 is deposited to a thickness of about 200-1000 .ANG. and etched back so as to remain selectively in valleys 42 of hemispherical polysilicon layer 4 as shown in FIG. 2(D).

Next, as shown in FIG. 2(E), a plurality of cylindrical polysilicon projections 32 are formed by applying a dry etching process on hemispherical polysilicon layer 4 and polysilicon layer 3, using the remaining portions of silicon oxide layer 62 as a mask. Cylindrical polysilicon projections 32 are located above the capacitor node contact with a source/drain region (not explicitly shown), and comprise a plurality of projections projecting vertically upward from the plane of polysilicon layer 3 as illustrated in FIG. 2(E).

In succession, as shown in FIG. 2(F), after removing the remaining portions of silicon oxide layers 6 and 62 by a wet etching process, polyimide layer 7 is deposited and etched back so as to expose the surface of silicon nitride layer 5. Polyimide layer 7 has a large etching selectivity, which means a large etch rate difference as compared with silicon nitride layer 5 and polysilicon layer 3.

Thereafter, as shown in FIG. 2(G), the silicon nitride layer 5 is removed by a wet etching process.

Next, as shown in FIG. 2(H), polysilicon layer 3 is etched using polyimide layer 7 as a mask so as to form a capacitor storage electrode, and polyimide layer 7 is removed. As a result, capacitor storage node 36 is formed as illustrated in FIG. 2(H).

Thereafter a capacitor is fabricated by forming a dielectric layer and a plate electrode of polysilicon (not shown) in a conventional manner.

FIG. 2 (I) illustrates an example of a capacitor layout made by a process in accordance with the present invention. The cylindrical capacitor storage node of this invention is located above a capacitor node contact with a source/drain region in the substrate, and the cylindrical capacitor storage node has a plurality of cylindrical projections projecting vertically upward from the substrate.

With a structure of a capacitor node in accordance with present invention, the capacitor node is of a cylindrical shape having many cylindrical projections formed on the upper side of the node contact. Therefore, the surface area of the capacitor node typically should be much increased over prior techniques.

Although various preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and/or substitutions are possible without departing from the scope and spirit of the present invention as disclosed in the claims.