Self-Routing Network Using Optical Gate Array Driven by Control Voltages Coincidental With Packet Header Pulses

This application is related to co-pending U.S. patent application Ser. No. 07/692,850, filed Apr. 29, 1991 and assigned to the same assignee as the present application.

The present invention relates generally to optical self-routing networks for routing optical packets according to the information contained in the header of the packets.

In a prior art optical self-routing network, as described in "Springer Series in Electronics and Photonics", Vol, 25, pages 193-195, an optical packet is fed into a splitter, in which it is split into two replicas of the input signal, one being applied to an optical switch having two outlet terminals, and the other to an optical correlator. The optical correlator generates an optical output if the header of the incoming packet contains a predetermined bit sequence. The output of the correlator is converted to an electrical signal, amplified and applied to the control electrode of the optical switch to direct the incident light to one of its outlet terminals.

However, a serious disadvantage of the prior art system is that the circuit complexity and practical implementation require a vast amount of optical, electro-optical and electronic components.

It is therefore an object of the present invention to provide an optical self-routing network which allows implementation with a smaller number of components.

According to the present invention, the optical self-routing network comprises N optical splitters associated respectively with N inlet terminals. Each of the splitters splits an optical signal from the associated inlet terminal into M replicas of the optical signal. M optical combiners are associated respectively with M outlet terminals, each of the optical combiners combining N optical signals incident thereon into a combined optical signal and coupling the combined optical signal to the associated outlet terminal. M sets of N optical gates are connected between the N optical splitters and the M optical combiners. Each of the optical gates allows passage of an optical signal incident thereon when it timely coincides with an electrical signal applied thereto. Gate control means are provided for supplying a gate control electrical signal to the optical gates of each set during M successive intervals. Priority selection is provided by the gate control means for selecting one of the optical packets which are simultaneously made to be incident on the optical gates of each set when contention or competition arises among the optical packets.

According to a first aspect of the priority selection, the gate control means supplies successively shifted gate control electrical signals respectively to the optical gates of each set. Thus, one of the optical gates of a given set exclusively allows passage of an optical signal incident thereon when the gate control electrical signal applied thereto is the earliest of the gate control electrical signals which are successively applied to the optical gates of the given set.

According to a second aspect of the priority selection, the optical gates of each set are commonly assigned a unique time interval, and those of the optical signals which are supplied to the optical gates of each set are successively shifted during the unique time interval. The gate control means exclusively causes one of the optical gates of each set to allow passage of an optical signal incident thereon when the incident optical signal is the earliest of the optical signals incident on the optical gates of the set.

According to a third specific aspect of the priority selection, the gate control means simultaneously supplies gate control electrical signals of different amplitudes respectively to the optical gates of each set so that one of the optical gates of a given set exclusively allows passage of an optical signal incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the signals applied to the optical gates of the given set.

According to a fourth aspect of the priority selection, the gate control means simultaneously supplies gate control electrical signals of different amplitudes respectively to the optical gates of each set so that one of the optical gates of a given set exclusively allows passage of an optical signal incident thereon when the light intensity of the incident optical signal is the highest of the optical signals incident on the optical gates of the given set.

In a preferred embodiment of this invention, the optical signals are respectively carried on a plurality of wavelengths, and each of the optical gates is selectively transmissive of an optical signal of one of the wavelengths.

The present invention will be described in further detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of the optical self-routing network according to a first embodiment of the present invention;

FIG. 2 is a timing diagram associated with the first embodiment;

FIG. 3 is a block diagram of a modified form of the first embodiment of this invention, FIG. 3a being a side view of each optical gate;

FIG. 4 is a block diagram of a second embodiment of the present invention;

FIG. 5 is a timing diagram associated with FIG. 4;

FIG. 6 is a block diagram of a modified form of the second embodiment of this invention;

FIG. 7 is a timing diagram associated with FIG. 6;

FIG. 8 is a block diagram of a third embodiment of the present invention;

FIG. 9 is a timing diagram associated with FIG. 8;

FIG. 10 is a block diagram of a modified form of the third embodiment;

FIG. 11 is a timing diagram associated with FIG. 10;

FIG. 12 is a block diagram of a fourth embodiment of this invention;

FIG. 13 is a timing diagram associated with FIG. 12;

FIG. 14 is a block diagram of a modified form of the fourth embodiment;

FIG. 15 is a timing diagram associated with FIG. 14;

FIG. 16 is a block diagram of a fifth embodiment of this invention;

FIG. 17 is a timing diagram associated with FIG. 16;

FIG. 18 is a block diagram of a modified form of the fifth embodiment;

FIG. 19 is a timing diagram associated with FIG. 18;

FIG. 20 is a block diagram of a sixth embodiment of the present invention, FIG. 20A showing details of the optical gates of FIG. 20;

FIG. 21 is a timing diagram associated with FIG. 20;

FIG. 22 is a block diagram of a modification of the sixth embodiment of the present invention; and

FIGS. 23A and 23B are timing diagrams associated with FIG. 22.

Referring now to FIG. 1, there is shown an optical self-routing network according to a first embodiment of the present invention. For purposes of disclosure, the self-routing network is shown as a 3.times.4 switch configuration. The network has three inlet terminals 2.sub.1, 2.sub.2 and 2.sub.3, three optical splitters 3.sub.1, 3.sub.2, 3.sub.3 respectively coupled to the inlet terminals for splitting a respective optical input into four replicas of the optical input. A 3.times.4 array of optical gates 4.sub.11 -4.sub.34 are provided, the gates being horizontally arranged to form three groups of four gates 4.sub.i1, 4.sub.i2, 4.sub.i3 and 4.sub.i4 (where i=1, 2 and 3) and vertically arranged to form four sets of three gates 4.sub.1j, 4.sub.2j and 4.sub.3j (where j=1, 2, 3 and 4). Different groups of optical gates are associated respectively with optical splitters 3.sub.1, 3.sub.2, 3.sub.3, and different sets of the optical gates are associated respectively with optical combiners 5.sub.1, 5.sub.2, 5.sub.3 and 5.sub.4, each of which provides a combined signal of the respective optical inputs. The outputs of combiners 5.sub.1, 5.sub.2, 5.sub.3 and 5.sub.4 are coupled respectively to outlet terminals 6.sub.1, 6.sub.2 , 6.sub.3 and 6.sub.4 of the network.

All optical gates are driven by electrical pulses that are supplied from a gate controller 10. The driving pulses have a particular timing and amplitude pattern determined in a manner to be described in detail later.

From user stations, electrical signals in the form of packets are transmitted on access lines L.sub.1, L.sub.2 and L.sub.3 to respective line interface circuits 1.sub.1, 1.sub.2, and 1.sub.3. Overall control of the network is provided by a routing controller 11 which is coupled to line interface circuits 1.sub.1, 1.sub.2, 1.sub.3. Each packet from user stations contains a header followed by a sequence of data bits. Routing controller 11 reads the header information of each incoming packet, assigns one or more pulse positions, or time slots in the header of that packet using amplitude and timing information from gate controller 10, and instructs the associated interface circuit to insert one or more header pulses into the assigned time slots of the packet for routing it to a desired outlet terminal. As will be described, the assignment of time slots is determined in relation to the timing and amplitude patterns of the driving pulses generated by the gate controller 10.

Each of the line interface circuits 1.sub.1, 1.sub.2, 1.sub.3 includes an electro-optical converter. After header pulse insertion, the incoming packets are converted to optical signals to form the inputs to the network and supplied to optical splitters 3.sub.1, 3.sub.2, 3.sub.3 via inlet terminals 2.sub.1, 2.sub.2, 2.sub.3 respectively.

As described in the aforesaid Co-pending U.S. patent application and in a paper by I. Ogura et al. titled "A Novel Switch with Surface Transmission Electro-photonic Device" (The 22nd International Conference On Solid-State Devices and Materials, 1990), each of the optical gates 4 is a gate-controlled, heterojunction semiconductor device which is excited when optical energy incident thereon timely coincides with a short-duration, high triggering potential at the gate and remains excited by a long-duration, low bias potential that follows. Du ring this excited state, the incident optical energy is allowed to pass through the device.

As shown in FIG. 2, gate controller 10 generates control voltage pulses C1, C2, C3 and C4, each having a high triggering voltage V.sub.H of duration T that exists anywhere between times t.sub.1 and t.sub.5 and a trailing, low bias voltage V.sub.L that exists until time t.sub.8. Control pulses C1, C2, C3 and C4 are respectively applied to conductors 7.sub.1, 7.sub.2, 7.sub.3 and 7.sub.4 that lead to the optical gates 4.sub.i1, 4.sub.i2, 4.sub.i3 and 4.sub.i4, where i=1, 2 and 3 respectively, as shown in FIG. 1. It is assumed that incoming optical packets P1, P2 and P3 appear at inlet terminals 2.sub.1, 2.sub.2 and 2.sub.3, respectively. If the destinations of packets P1, P2 and P3 are such that they should be routed to outlet terminals 6.sub.1, 6.sub.2 and 6.sub.3, respectively, then header pulses P1a, P2a and P3a are respectively inserted by interface circuits 1.sub.1, 1.sub.2 and 1.sub.3 into time slots (or header slots) t.sub.1 -t.sub.2, t.sub.2 -t.sub.3 and t.sub.3 -t.sub.4 of optical packets P1, P2 and P3. In this way, header pulses P1a, P2a and P3a respectively coincide with the triggering voltages V.sub.H of control pulses C1, C2 and C3. Note that data bits of each optical packet occupy the same interval between times t.sub.6 and t.sub.7.

In response to the coincidence between the triggering voltage V.sub.H of pulse C1 and header pulse P1a, optical gate 4.sub.11 changes to an excited state and maintains it under the influence of the trailing bias voltage V.sub.L. Thus, optical packet P1 is allowed to pass through gate 4.sub.11 to optical combiner 5.sub.1 and appears at outlet terminal 6.sub.1. Likewise, the coincidence between the triggering voltage V.sub.H of pulse C2 and header pulse P2a causes optical gate 4.sub.22 to be excited, allowing optical packet P2 to be routed to outlet terminal 6.sub.2 and the coincidence between the triggering voltage V.sub.H of pulse C3 and header pulse P3a causes optical gate 4.sub.33 to be excited, allowing packet P3 to be routed to outlet terminal 6.sub.3. It is seen that if any of these packets is destined to outlet terminal 6.sub.4, a header pulse will be inserted in time slot t.sub.4 -t.sub.5 of the packet. In this way, an optical input to any one of splitters 3.sub.1, 3.sub.2, 3.sub.3 can be routed through the network to any one of outlet terminals 6.sub.1, 6.sub.2, 6.sub.3 and 6.sub.4 by controlling the position of header pulses.

A flexible arrangement of the self-routing network can be implemented by a modified form of the invention as shown in FIG. 3. In this modification, half-silvered mirrors 30 are positioned between optical splitters 3.sub.1, 3.sub.2, 3.sub.3 and the optical gate array, and an array of optical lenses 31 are disposed on the outputs of splitters 3.sub.1, 3.sub.2 and 3.sub.3 to direct their output light beams through the half-silvered mirrors to the associated optical gates. Optical lenses 32 are disposed on the input ends of combiners 5.sub.1, 5.sub.2, 5.sub.3 and 5.sub.4 to focus incident light beams to the combiners. Each optical gate 4.sub.ij is provided with a reflecting mirror 33 at one end of the device remote from the associated optical splitters as shown in FIG. 3a. When each of the optical gates is excited, the light incident thereon is reflected off the wall 33 to the half-silvered mirror through which it has passed and where it bends its course at right angles to a corresponding one of lenses 32.

Due to possible timing inaccuracies, two or more header pulses may occur during the period of the same triggering voltage. In such situations, collision occurs at the inputs of an optical combiner to which the packets are destined. The following embodiments overcome this data collision problem.

A second embodiment of this invention is shown in FIG. 4 which differs from the Fig. 1 embodiment by the inclusion of a series-connected resistor-delay circuit in each of the gate control lines 7.sub.j (where j=1, 2, 3 and 4) that extend from gate controller 10a to optical gates 4.sub.ij. Each control line 7.sub.j, includes a resistor 8.sub.j and delay elements 9.sub.1j and 9.sub.2j, with the circuit junction between resistor 8.sub.1 and delay element 9.sub.2j being connected to optical gate 4.sub.3j and the junction between delay elements 9.sub.2j and 9.sub.1j being connected to optical gate 4.sub.2j. Gate control pulses C.sub.j are successively generated at intervals T equal to the duration of the header pulse, and delayed by delay elements 9.sub.2j and 9.sub.1j to successively produce delayed control pulses C.sub.ij.

As shown in FIG. 5, each of the delay elements 9 introduces a delay time that is one-third of the duration T of the header pulse, and the triggering voltage of each control pulse is equal to the delay time T/3. In this way, optical gates 4.sub.3j, 4.sub.2j and 4.sub.1j are supplied with successively shifted control pulses C.sub.3j, C.sub.2j and C.sub.1j, respectively. Therefore, each optical gate of the network of FIG. 4 has a unique triggering instant, and the header pulse of each packet successively coincides with the triggering voltage of a sequence of three control pulses. Due to the provision of the resistor 8j in each column "j" of the gate array, excitation of one of the optical gates of a given column causes a voltage drop to occur across the resistor. As a result, when one of the gates of a given column is excited, the voltage applied to the other gates of the column located downstream of the excited gate are not excited even if their triggering voltages coincide with a header pulse.

Assume that packets P1 and P2 on inlet terminals 2.sub.1 and 2.sub.2 are destined to outlet terminal 6.sub.1 and packet P3 is destined to outlet terminal 6.sub.2. In order for packets P1 and P2 to arrive at outlet terminal 6.sub.1 and for packet P3 to arrive at terminal 6.sub.2, it is necessary that header pulses P1a and P2a should coincide with control pulses C.sub.11 and C.sub.21, respectively, and header pulse P3a should coincide with control pulse C.sub.32 as seen from FIG. 4. Therefore, header pulses P1a and P2a are inserted to the same interval t.sub.1 -t.sub.4, and header pulse P3a is inserted in the interval t.sub.4 -t.sub.7 as shown in FIG. 5. If this condition occurs, a coincidence occurs in gate 4.sub.21 between header pulse P2a and the triggering voltage of pulse C.sub.21 earlier than a coincidence that occurs in gate 4.sub.11 between header pulse P2a and the triggering voltage of pulse C.sub.11, generating a voltage drop across resistor 8.sub.1 immediately following the excitation of gate 4.sub.21. Because of the voltage drop, the voltage at the gate 4.sub.11 is too low for it to be excited, while gate 4.sub.21 remains in the excited state. Packet P2 is thus allowed to pass through gate 4.sub.21 to outlet terminal 6.sub.1, while packet P1 is prevented from passing through gate 4.sub.11. On the other hand, header pulse P3a coincides with the triggering voltage of pulse C.sub.32, allowing gate 4.sub.32 to transmit packet P3 to outlet terminal 6.sub.2. Although not shown in the drawing, some provision will be made in the network so that the fact that packet P1 corrupted as a result of a collision or contention is communicated to the originating user for retransmission of a copy of the packet. It is seen that to avoid collision between packets P1, P2 and P3 it is necessary that the header pulse of each packet exist in one of four discrete time intervals t.sub.1 -t.sub.4, t.sub.4 -t.sub.7, t.sub.7 -t.sub.10 and t.sub.10 -t.sub.13.

Returning briefly to FIG. 2, if the triggering voltage of control pulse C.sub.1 is delayed slightly with respect to its correct position, the successive header pulses P1a and P2a would sequentially coincide with it. This would result in a collision between packets P1 and P2 at optical gates 4.sub.11 and 4.sub.21. Such a collision is avoided by an embodiment shown in FIG. 6. The embodiment of FIG. 6 is implemented by modifying the embodiment of FIG. 4 in which all delay elements of FIG. 4 are removed from the gate array, directly coupling the voltage-dropping resistors to the associated optical gates. As shown in FIG. 7, this embodiment differs from the FIG. 4 embodiment in that the triggering voltage of each control pulse C.sub.j has a duration T, applying the same control pulse to the gates of the same column, and the header pulse of each optical packet has one-third of the duration T. Control pulses C.sub.1, C.sub.2, C.sub.3 and C.sub.4 are successively generated at T-intervals.

Assume that control pulse C.sub.1 is delayed so that its triggering high voltage portion successively coincides with headers P1a and P2a (FIG. 2). However, due to the fact that the earlier occurrence of header pulse P1a generates a voltage drop across resistor 8.sub.1 and the voltage at the gate 4.sub.21 is lowered to a level not sufficient to cause it to excite in response to header pulse P2a. Therefore, packet P1 is passed through gate 4.sub.11, while packet P2 is blocked at gate 4.sub.21. Header pulse P3a is assumed to be assigned a position that coincides with the triggering voltage of control pulse C.sub.2. Gate 4.sub.32 is thus excited, allowing packet P3 to be routed to combiner 5.sub.2.

A third embodiment of the present invention is shown in FIG. 8. This embodiment differs from the FIG. 1 embodiment by the inclusion of a fourth group of optical gates 4.sub.15 .about.4.sub.18, a fifth group of optical gates 4.sub.25 .about.4.sub.28, and a sixth group of optical gates 4.sub.35 .about.4.sub.38, with the optical gates of the fourth, fifth and sixth groups being respectively connected to the outputs of the optical gates of the first, second and third groups. Controller 10c drives the optical gates of the fourth, fifth and sixth groups through control lines 7.sub.5 .about.7.sub.8 (=7.sub.j+4, where j=1, 2, 3 and 4) extending to optical gates 4.sub.15 -4.sub.18. Each of control lines 7.sub.4+j includes series-connected resistors 10.sub.1j, 10.sub.2j and 10.sub.3j with the junction between resistors 10.sub.1j and 10.sub.2j being connected to optical gates 4.sub.2 (j+4) and the junction between resistors 10.sub.2j and 10.sub.3j being connected to optical gates 4.sub.3(j+4). The outputs of optical gates 4.sub.i(j+4) are connected to the ith inputs of combiners 5.sub.j.

Controller 10c successively applies control pulses C.sub.1a, C.sub.2a, C.sub.3a and C.sub.4a to lines 7.sub.1 .about.7.sub.4, respectively, during a first interval between times t.sub.1 and t.sub.13, and successively applies additional control pulses to lines 7.sub.5 .about.7.sub.8 during a second interval between times t.sub.13 and t.sub.25. These additional pulses are indicated by waveforms C.sub.1b, C.sub.2b, C.sub.3b and C.sub.4b in FIG. 9 after experiencing a voltage drop by resisters 10.sub.31, 10.sub.32, 10.sub.33 and 10.sub.34. The triggering voltage of each of these control pulses has a duration T and the header pulse of each packet has one-third of the duration T, as in the FIG. 7 embodiment. The triggering voltages of pulses C.sub.1b, C.sub.2b, C.sub.3b and C.sub.4b on control lines 7.sub.5 .about.7.sub.6 has a voltage level V.sub.1 after experiencing a voltage drop by resisters 10.sub.31, 10.sub.32, 10.sub.33 and 10.sub.34. When one of the optical gates connected to the same control line is excited, the voltage at the junction of resisters 10.sub.3j and 10.sub.2j drops to a lower level V.sub.2 and the voltage at the junction of resisters 10.sub.2j and 10.sub.1j drops to a lowest level V.sub.3. The optical gate whose triggering voltage is higher than any of the other gates of the same control line is given priority. Thus, if a contention arises in any of the fourth, fifth and sixth groups of optical gates, only one packet is selected by the gate having priority. To achieve the priority selection, each optical packet has a second header pulse "b" which is spaced from the first header pulse "a" by an interval equal to 4T. Assume that the header pulses P1a and P1b of optical packet P1 are inserted respectively to time slots t.sub.1 .about.t.sub.2 and t.sub.14 -t.sub.14 and the header pulses P2a and P3a of packet P2 occur in the same time slots. The header pulses P3a, P3b of packet P3 are assumed to be inserted to positions t.sub.4 .about.t.sub.5 and t.sub.16 -t.sub.17. Since header pulses P1a and P2a coincide with the triggering voltage of control pulse C.sub.1a, optical gates 4.sub.11 and 4.sub.21 are simultaneously excited, allowing packets P1 and P2 to be forwarded to optical gates 4.sub.15 and 4.sub.25, respectively, while header pulse P3a excites gate 4.sub.32 upon coincidence with the triggering voltage of control pulse C.sub.2a, thus applying packet P3 to gate 4.sub.36. Header pulse P1b coincides with the triggering voltage of control pulse C".sub.1b that is applied to gate 4.sub.15, and the header pulse P26 coincides with the triggering voltage of control pulse C'.sub.1b that is applied to gate 4.sub.25. Therefore, the triggering voltage at gate 4.sub.25 reduces to lower level V.sub.2, while the voltage at gate 4.sub.15 reduces lowest level V.sub.3 as indicated in FIG. 9, giving priority to gate 4.sub.25 in passing packet P2 to combiner 5.sub.1. Header pulse P3b then coincides with the triggering voltage of control pulse C.sub.2b at gate 4.sub.36, and packet P3 is passed through it to combiner 5.sub.2.

A modified embodiment of FIG. 8 is shown in FIG. 10 which differs from it by the exclusion of resistors 10.sub.1j and 10.sub.2j from the control lines 7.sub.(j+4) and by the use of second header pulses having different light intensities S.sub.1, S.sub.2 and S.sub.3 as shown in FIG. 11, with the light intensities having a relationship S.sub.1 >S.sub.2 >S.sub.3. Assume that all header pulses of packets P1, P2 and P3 are inserted to the same time slots as in the FIG. 8 embodiment, and that their second header pulses P1b, P2b and P3b have light intensities S.sub.1, S.sub.2 and S.sub.3, respectively. In the same manner as described in the previous embodiment, packets P1, P2 and P3 are passed through optical gates 4.sub.11, 4.sub.21 and 4.sub.32, respectively, when their first header pulses P1a, P2a, P3a coincide with control pulses C.sub.1a and C.sub.2a and are directed to optical gates 4.sub.15, 4.sub.25 , and 4.sub.36, respectively. Because of the highest light intensity of header pulse P1b, coincidence between header pulse P1a and control pulse C.sub.1b causes gate 4.sub.15 to draw a greater current for excitation than the current drawn by gate 4.sub.25. A sharp voltage drop thus develops across resistor 10.sub.31, preventing gate 4.sub.25 from being excited. Thus, packet P1 is given priority over contending packet P2, while packet P3 is allowed to pass through gate 4.sub.36 to combiner 5.sub.2 without contention in response to its second header pulse coinciding with control pulse C.sub.2b.

A fourth embodiment of this invention is shown in FIG. 12 as a 4.times.2 switch configuration. Four optical splitters 3.sub.1 .about.3.sub.4, each having two outputs, are provided to receive incoming optical packets P1, P2, P3 and P4, respectively. Optical gates 40.sub.1n (where n=1 and 2) have their inputs coupled respectively to the first (upper) outputs of splitters 30.sub.1 and 30.sub.2, and optical gates 40.sub.2n have their inputs coupled respectively to the first outputs of splitters 30.sub.3 and 30.sub.4. Similarly, optical gates 40.sub.3n have their inputs coupled respectively to the second (lower) outputs of splitters 30.sub.1 and 30.sub.2, and optical gates 40.sub.4n have their inputs coupled respectively to the second outputs of splitters 30.sub.3 and 30.sub.4. Optical combiners 50.sub.m (where m=1, 2, 3 and 4) are associated respectively with optical gates 40.sub.mm. Each combiner 50.sub.m has two inputs which are connected to the outputs of the associated optical gates 4.sub.mm. The outputs of combiners 50.sub.m are connected respectively to optical gates 41.sub.m. The outputs of gates 41.sub.1 and 41.sub.2 are respectively coupled by optical combiner 50.sub.5 to outlet terminal 60.sub.1, those of gates 41.sub.3 and 41.sub.4 being coupled by combiner 50.sub.6 to outlet terminal 60.sub.2.

Gate controller 10d generates four control pulses C.sub.1, C.sub.2, C.sub.3 and C.sub.4. Control pulse C.sub.1 is supplied to gate 40.sub.11 through resistors 11.sub.2 and 11.sub.1 and to gate 40.sub.12 through resistor 11.sub.2, the same pulse being applied to gate 40.sub.21 through resistors 12.sub.2 and 12.sub.1 and to gate 40.sub.22 through resistor 12.sub.2, thus supplying different voltages C.sub.11, C.sub.12, C.sub.13 and C.sub.14 to gates 40.sub.11, 40.sub.12, 40.sub.21 and 40.sub.22, respectively. Likewise, control pulse C.sub.2 is supplied to gate 40.sub.31 through resistors 13.sub.2 and 13.sub.1 and to gate 40.sub.32 through resistor 13.sub.2, the same pulse being applied to gate 40.sub.41 through resistors 14.sub.2 and 14.sub.1 and to gate 40.sub.42 through resistor 14.sub.2, thus supplying different voltages C.sub.21, C.sub.22, C.sub.23 and C.sub.24 to gates 40.sub.31, 40.sub.32, 40.sub.41 and 40.sub.42, respectively. In like manner, control pulse C.sub.3 is applied to gate 41.sub.1 through resistors 15.sub.2 and 15.sub.1 and to gate 41.sub.2 through resistor 15.sub.2, and control pulse C.sub.4 is applied to gate 41.sub.3 through resistors 16.sub.2 and 16.sub.1 and to gate 41.sub.2 through resistor 16.sub.2, thus supplying different voltages C.sub.31, C.sub.32, C.sub.41 and C.sub.42 to gates 41.sub.1, 41.sub.2, 41.sub.3 and 41.sub.4, respectively. It is seen that gates 40.sub.12, 40.sub.22, 40.sub.32, 40.sub.42, 41.sub.2 and 41.sub.4 are given priority over their companion gates 40.sub.11, 40.sub.21, 40.sub.32, 40.sub.41, 41.sub.1 and 41.sub.3, when coincidence occurs between incoming header pulses and their gate control pukes. The self-routing network of this configuration can be said to operate on a successive "tournament" basis as will be understood with reference to FIG. 13. As shown in FIG. 13, the triggering voltage of each control pulse has a duration T equal to the duration of each header pulse. Timing margins are provided between the leading edges of successive gate control pulses. For purposes of clarity, the timing margins are set equal to the duration T. Assume that a contention is likely to occur between the header pulses P1b and P3b of packets P1 and P3 and between the header pulse P2b and P4b of packets P2 and P4. The header pulse P1a of packet P1 coincides with control pulse C.sub.11 at gate 40.sub.11 without contention with gate 40.sub.12, allowing the packet to be routed through combiner 50.sub.1 to output gate 41.sub.1, while the header pulse P3a of packet P3 coincides with control pulse C.sub.13 at gate 40.sub.21 without contention with gate 40.sub.22, routing the packet through combiner 50.sub.2 to output gate 41.sub.2. In like manner, the header pulse P2a of packet P2 coincide with control pulse C.sub.22 at gate 40.sub.32 without contention with gate 40.sub.31, allowing the packet to be routed through combiner 50.sub.3 to output gate 41.sub.3, while the header purse P4a of packet P4 coincides with control pulse C.sub.24 at gate 40.sub.42 without contention with gate 40.sub.41, muting the packet through combiner 50.sub. 4 to output gate 41.sub.4.

Contention occurs between the header pulses P1b and P3b at gates 41.sub.1 and 41.sub.2 as they are simultaneously supplied with the triggering voltages of control pulses C.sub.31 and C.sub.32. Since control pulse C.sub.32 has a higher triggering voltage than control pulse C.sub.31, Gate 41.sub.2 wins the contention, passing packet P3 through combiner 50.sub.5 to outlet terminal 60.sub.1. A similar situation occurs between the header pulses P2b and P4b at gates 41.sub.3 and 41.sub.4, as they are simultaneously supplied with the triggering voltages of control pulses C.sub.41 and C.sub.42. Because of the higher triggering voltage, gate 41.sub.4 wins the contention for transmitting packet P4 to outlet terminal 60.sub.2. If a contention occurs between input gates 40.sub.i1 and 40.sub.i2 (where i=1, 2, 3, 4), gate 40.sub.i2 is always the winner by virtue of their higher triggering voltage.

An embodiment shown in FIG. 14 is a modification of the embodiment of FIG. 12, the difference being in the exclusion of resistors 11.sub.1, 12.sub.1, 13.sub.1, 14.sub.1, 15.sub.1 and 16.sub.1 so that equal triggering voltages (C.sub.1a, C.sub.1b, C.sub.2a, C.sub.2b, C.sub.3a, C.sub.4a) are supplied to the optical gates of contending partners (pairs) and in the generation of header pulses having different light intensities as seen from FIG. 15. As illustrated, the header pulses are assumed to occur in the same time slots as in the case of FIG. 14. As in the previous embodiment, packets P1 and P3 are routed through input gates without contention to output gates 41.sub.1 and 41.sub.2 between which contention arises, and the other packets are routed to output gates 41.sub.3 and 41.sub.4 between which contention arises. The header pulses of packet P1 have the highest light intensity, and those of packets P2, P3 and P4 have decreasing light intensities in the order given. Since header pulses P1b and P2b have a higher light intensity than those of the contending packets, packets routed to output gates 41.sub.1 and 41.sub.3 are the winners of the contentions, so that P1 is passed through combiner 50.sub.5 to outlet terminal 60.sub.1 and P2 is passed through combiner 50.sub.6 to outlet terminal 60.sub.2. A self-routing network of a 4.times.2 switch configuration can also be implemented in a single contention stage for each outlet terminal as shown in FIG. 16. Optical gates 42.sub.1 .about.42.sub.4 are coupled respectively to the first outputs of splitters 30.sub.1 .about.30.sub.4 for resolving a contention among packets destined to outlet terminal 60.sub.1 through combiner 50.sub.1, and optical gates 43.sub.1 -43.sub.4 are coupled respectively to the second outputs of splitters 30.sub.1 .about.30.sub.4 for resolving a contention among packets that are destined for outlet terminal 60.sub.2 through combiner 50.sub.2. Gate controller 10e supplies a control pulse C.sub.1 through series-connected resistors 17.sub.4, 17.sub.3, 17.sub.2 and 17.sub.1 to develop successively decreasing control voltages C.sub.14, C.sub.13, C.sub.12 and C.sub.11 for coupling to gates 42.sub.4, 42.sub.3, 42.sub.2 and 42.sub.1, respectively. Likewise, gate controller 10e further supplies a control pulse C.sub.2 through series-connected resistors 18.sub.4, 18.sub.3, 18.sub.2 and 18.sub.1 to develop successively decreasing control voltages C.sub.24, C.sub.23, C.sub.22 and C.sub.21 for coupling to gates 43.sub.4, 43.sub.3, 43.sub.2 and 43.sub.1, respectively.

As shown in FIG. 17, each optical packet has a single header pulse. If header pulse P1a and P3a occur in the same time slot t.sub.1 -t.sub.2 so that packets P1 and P3 are destined to outlet terminal 60.sub.1 and header pulse P2a and P4a occur in the same time slot t.sub.2 -t.sub.3 so that packets P2 and P4 are destined to outlet terminal 60.sub.2, contention occurs at gates 42.sub.1 and 42.sub.3 as well as at gates 43.sub.2 and 43.sub.4 as packets P1 and P3 coincide with control pulses C.sub.11 and C.sub.13, respectively, and the other packets P2 and P4 coincide with control pulses C.sub.22 and C.sub.24, respectively. Since gate 42.sub.3 is supplied with a higher triggering voltage than the voltage supplied to gate 42.sub.1, packet P3 wins the race for contention with packet P1. In a similar manner, if gate 43.sub.4 is supplied with a higher triggering voltage than the voltage at gate 43.sub.1, packet P4 is the winner. FIG. 18 is a modification of the embodiment of FIG. 16, the difference being the exclusion of resistors 17.sub.1 -17.sub.3 and resistors 18.sub.1 -18.sub.3, so that equal triggering voltages (C'.sub.1 and C'.sub.2) are supplied to the optical gates of contending partners (sets) and in the generation of header pulses having different light intensities, as seen from FIG. 19. As illustrated, the header pulses are assumed to occur in the same time slots as in the case of FIG. 17. As in the previous embodiment, packets P1 and P3 are applied to gates 42.sub.1 and 42.sub.3, respectively, and packets P2 and P4 are applied to gates 43.sub.2 and 43.sub.4, respectively. As shown in FIG. 19, the header puke of packet P1 have the highest light intensity, and those of packets P2, P3 and P4 have decreasing light intensities in the order given. Since header pulses P1b and P2b have a higher light intensity than those of the contending packets, packets P1 and P2 supplied to gates 42.sub.1 and 43.sub.2 are the winners of the race to respective outlet terminals 60.sub.1 and 60.sub.2.

The length of a header increases with the amount of traffic to be carried by the self-routing network. The header length can be conserved by multiplexing optical packets upon different light wavelengths. The wavelength multiplexing concept of this invention for two wavelengths is implemented by a 2.times.4 network configuration as shown in FIG. 20. Electrical packets P1 and P2 from a user station are successively transmitted on access line L.sub.1 and received by line interface 1'.sub.1 and packets P3 and P4 from another user station are successively transmitted on access line L.sub.2 and received by line interface 1'.sub.2. Routing controller 120 is coupled to the line interfaces, determines a wavelength and a header time slot according to the information contained in a packet received from the associated interface in relation to the timing and amplitude pattern of the gate control pulses supplied from gate controller 10f, and instructs the interface to carry the packet on the determined wavelength and insert a header pulse into the determined time slot. For purposes of illustration, packets P1 and P2 are converted by line interface 1'.sub.1 L to optical signals of wavelength .lambda..sub.1, and packets P3 and P4 are converted by line interface 1'.sub.2 to optical signals of wavelengths .lambda..sub.2 and .lambda..sub.1, respectively. The outputs of interfaces 1'.sub.1 and 1'.sub.2 are connected respectively by light waveguides 70.sub.1 and 70.sub.2 to optical splitters 80.sub.1 and 80.sub.2, each having four outputs. Optical gates 90.sub.11, 90.sub.12, 90.sub.13 and 90.sub.14 are connected respectively to the outputs of splitter 80.sub.1, and gates 90.sub.11 and 90.sub.12 are tuned to wavelength .lambda..sub.1, and gates 90.sub.13 and 90.sub.14 are tuned to wavelength .lambda..sub.2. Optical gates 90.sub.21, 90.sub.22, 90.sub.23 and 90.sub.24 are likewise connected to the outputs of splitter 80.sub.2, with gates 90.sub.21 and 90.sub.22 being tuned to wavelength .lambda..sub.1 and gates 90.sub.23 and 90.sub.24 being tuned to wavelength .lambda..sub.2. The outputs of gates 90.sub.ij (I=1, 2, 3, 4) are connected respectively to the first inputs of combiners 100j and the outputs of gates 90.sub.2j are connected to the second inputs of combiners 100j. Gate controller 10f supplies control pulses C.sub.1 and C.sub.2 to gates 90.sub.i1 and 90.sub.i2 (i=1, 2) and control pulses C.sub.3 and C.sub.4 to gates 90.sub.i3 and 90.sub.i4.

As shown in FIG. 20A, each of the optical gates 90.sub.ij is preferably constructed of a narrow-band wavelength tunable optical element 85 and a wide-band wavelength tunable optical element 86 coupled together and arranged in the path of incident light beam.

As illustrated in FIG. 21, the triggering voltages of all control pulses C.sub.1 .about.C.sub.4 have equal amplitude V.sub.H for gate excitation, with the triggering voltages of pulses C.sub.1 and C.sub.3 having an equal time slot t.sub.1 -t.sub.2 and those of pulses C.sub.2 and C.sub.4 having an equal time slot t.sub.2 -t.sub.3. According to different wavelengths, control pulses C.sub.1 and C.sub.2 have a trailing voltage V.sub.L1 for tuning to wavelength .lambda..sub.1, while the trailing voltage of pulses C.sub.3 and C.sub.4 is set equal to V.sub.L2 for tuning to wavelength .lambda..sub.2.

Assume that header pulses P1a and P2a for packets P1 (.lambda..sub.1) and P2(.lambda..sub.1) are inserted into the same time slot t.sub.1 -t.sub.2 of successive headers and the header pulse P3a of packet P3(.lambda..sub.2) is inserted to the time slot t.sub.1 -t.sub.2 of an initial header. The header pulse P4a of packet P4(.lambda..sub.1) is assumed to be inserted in the time slot t.sub.2 -t.sub.3 of a subsequent header.

It is seen that header pulses P1a and P2a successively coincide with control pulse C.sub.1 at gate 90.sub.11, so packets P1(.lambda..sub.1) and P2(.lambda..sub.1) are routed to an outlet terminal 110.sub.1 via combiner 100.sub.1. Header pulse P3a coincides with control pulse C.sub.3 at gate 90.sub.23, allowing packet P3(.lambda..sub.2) to be routed to outlet terminal 110.sub.3 via combiner 100.sub.3. In like manner, header pulse P4a coincides with control pulse C.sub.2 at gate 90.sub.22, muting packet P4(.lambda..sub.1) to outlet terminal 110.sub.2 via combiner 100.sub.2.

However, data collision is likely to occur between packets of the same wavelength at the inputs of a combiner 100 if their header pulses are inserted to successive time slots of the same header and partially coincide with a control pulse due to timing inaccuracies. To resolve the collision problem, the embodiment of FIG. 20 is modified as shown in FIG. 22 in which the network is implemented in a 4.times.2 switch configuration. Optical splitters 80.sub.1, 80.sub.2, 80.sub.3 and 80.sub.4, arranged to receive optical packets P1(.lambda..sub.1), P2(.lambda..sub.2), P3(.lambda..sub.1) and P4(.lambda..sub.2) from waveguides 70.sub.1 .about.70.sub.4, are connected respectively to wavelength tunable optical gates 91.sub.1j, 91.sub.2j, 91.sub.3j and 91.sub.4j (i=1, 2). The outputs of gates 91.sub.i1 and 91.sub.i2 (i=1, 2, 3, 4) are coupled to the ith inputs of combiners 100.sub.1 and 100.sub.2. Gates 91.sub.i1 and 91.sub.i2 are tuned to wavelength .lambda..sub.1 and .lambda..sub. 2, respectively, and supplied with control pulses C'.sub.1 and C'.sub.2 via resistors 19.sub.1 and 19.sub.2, respectively, from gate controller 10g.

As shown in FIG. 23A, gate control pulses C.sub.1 and C.sub.2 generated by controller 10g have triggering voltages of a duration twice as long as the duration of the header pulse. Assume that header pulses P1a and P2a are inserted to time slot t.sub.1 -t.sub.2, and header pulses P3a and P4a are assigned time slot t.sub.2 -t.sub.3. It is seen that gate 91.sub.11 is excited upon coincidence between header pulse P1a and control pulse C'.sub.1, producing a voltage drop across resistor 19.sub.1 and allowing packet P1(.lambda..sub.1) to be routed to combiner 100.sub.1. Similarly, gate 91.sub.22 is excited upon coincidence between header pulse P2a and control pulse C'.sub.2, producing a voltage drop across resistor 19.sub.2 and allowing packet P2(.lambda..sub.2) to be routed to combiner 100.sub.2. However, due to the voltage drop across resistor 19.sub.1, gate 91.sub.31 is not excited and packet P3(.lambda..sub.1) is the loser of the contention with packet P1(.lambda..sub.1). In like manner, packet P4(.lambda.2) is the loser of the contention with packet P2(.lambda..sub.2).

Alteratively, the triggering voltages of all control pulses are of equal duration to the duration of the header pulse and the header of each packet has different light intensities as shown in FIG. 23B. In this way, packets P1.about.P4 have decreasing levels of priority in the order named that contention between packets P1 and P3 at gates 91.sub.11 and 91.sub.31 is resolved by giving priority to packet P1, while contention between packets P2 and P4 is resolved by giving priority to packet P2.

The foregoing description shows only preferred embodiments of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims. Therefore, the embodiments shown and described are only illustrative, not restrictive.