Field Effect Transistor Having a Sandwiched Channel Layer

1. Field of the Invention

The present invention relates to a field effect transistor (FET) operated with low noise at high speed.

2. Related Background Art

Japanese Patent Laid-Open No. 63-90861, Japanese Patent Laid-Open No. 63-272080, and Japanese Patent Laid-Open No. 64-2371 disclose techniques related to an FET using n-type GaInAs as a channel.

In these techniques, since Si is uniformly doped in GaInAs, electrons serving as carriers are scattered by Si atoms, and a sufficient overshoot-effect of drift velocity cannot be obtained and therefore sufficient characteristics to operate with low noise at high speed cannot be obtained. In Japanese Patent Laid-Open No. 63-90861, a technique for planer-doping Si in a GaInAs layer is disclosed. However, an FET having a deep gate threshold value voltage Vth cannot easily be formed by that planer-doping. For this reason, the following problems rises. That is, 1 an FET having a high output cannot be formed, and 2 the degree of freedom of circuit design is low.

It is an object of the present invention to provide an FET using GaInAs as a channel and operated with low noise at a speed higher than that of a conventional FET.

It is another object of the present invention to provide a field effect transistor comprising an epitaxially grown n-type GaInAs channel layer, first and second undoped GaInAs layers formed to sandwich the channel layer, a buffer layer formed by a semiconductor having an energy band gap higher than that of the first layer to be lattice-matched with the first layer and to be in contact with one side of the first layer, a cap layer formed by a semiconductor having a band gap higher than that of the second layer to be lattice-matched with the second layer and to be in contact with one side of the second layer, and a gate electrode formed to be in Schottky contact with the cap layer.

In the above field effect transistor, a three-layered structure obtained by sandwiching the n-type GaInAs channel layer between the undoped GaInAs layers is formed on a substrate through the buffer layer, and the cap layer is formed on the resultant structure. According to this field effect transistor, the region permitting carrier electrons to travel at a high speed are not only located in the channel layer, but a part of the region extends to the undoped GaInAs layers. For this reason, carrier electrons present in the undoped GaInAs layers are not scattered by dopant atoms, and the carrier electrons are permitted to travel at a high speed in the overshoot-effect. Therefore, the source resistance is decreased, and the transconductance (g.sub.m) is increased. In addition, a high-speed operation with low noise can be achieved.

The buffer layer is made of GaAs, and the cap layer is made of GaAs or AlGaAs. In addition, undoped GaInAs graded layers are formed as the first and second layers. In these graded layers, the In composition ration is gradually varied such that the In composition ratio is about 0 on the junction surfaces with the buffer layer and the cap layer and it becomes substantially equal to the In composition ratio of the channel layer on the junction surfaces with the channel layer. The present invention has as its object to provide the above field effect transistor. As described above, when the graded layers are used as the first and second layers, lattice mismatches between the buffer layer, the first layer, the channel layer, the second layer, and the cap layer can be prevented, and a field effect transistor capable of achieving a high-speed operation with low noise can be obtained.

The buffer layer is made of GaAs, the cap layer is made of GaAs or AlGaAs, the first and second graded layers are made of undoped Ga.sub.0.85 In.sub.0.15 As, and the channel layer is made of Ga.sub.0.85 In.sub.0.15 As in which an n-type impurity is doped. The present invention has as its object to provide a field effect transistor in which the total film thickness of the first layer, the channel layer, and the second layer is, e.g., about 150 .ANG., less than a critical film thickness at which dislocation is caused by lattice distortion. As described above, when the total film thickness is less than the critical film thickness at which dislocation is caused by lattice distortion, lattice defects can be suppressed, and a field effect transistor capable of achieving a high-speed operation with low noise can be obtained.

The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

FIGS. 1A to 1D are sectional views showing the steps in manufacturing an FET according to an embodiment of the present invention;

FIGS. 2A and 2B are energy band diagrams for explaining an operation of the first embodiment of the present invention;

FIGS. 3A and 3B are energy band diagrams for explaining an operation of the second embodiment of the present invention; and

FIGS. 4A and 4B are sectional views showing a method of forming an electrode according to an embodiment of the present invention.

FIGS. 1A to 1D are sectional views showing the steps in manufacturing an FET according to an embodiment of the present invention.

The steps according to the first embodiment of the present invention will be described below. A GaAs substrate 1 is used as a semiconductor substrate, and a buffer layer 2 (background p-type, p=3.times.10.sup.15 cm.sup.-3) which is an undoped GaAs monocrystalline layer is epitaxially grown on the GaAs substrate 1 by, e.g., an organometallic vapor phase epitaxy method (OMVPE method), to have a thickness of 5,000 .ANG. (FIG. 1A). An undoped Ga.sub.1-X In.sub.X As graded layer 3 in which the In composition ratio X is gradually increased from GaInAs and it is set to be 0.15 on the upper most surface is grown on the resultant structure to have a thickness of 50 .ANG. (FIG. 1B). A channel layer 4 made of n-type Ga.sub.1-X In.sub.X As (n=4.times.10.sup.18 cm.sup.-3) and uniformly doped with Si is grown on the graded layer 3 to have a thickness of 50 .ANG.. The In composition ratio X of the channel layer 4 is substantially equal to the In composition ratio in the upper surface of the graded layer 3, i.e., X=0.15. A Ga.sub.1-X In.sub.X As graded layer 5 in which the In composition ratio X is gradually decreased and the uppermost surface region is made of GaAs is formed on the channel layer 4 to have a thickness of 50 .ANG. (FIG. 1C).

Thereafter, a cap layer 6 made of an undoped GaAs single crystal is grown on the graded layer 5 to have a thickness of 400 .ANG.. Finally, a gate electrode 7, a source electrode 8, and a drain electrode 9 are formed on the cap layer 6, thereby constituting the FET according to this embodiment (FIG. 1D).

An operation of the FET manufactured as described above will be described below with reference to the energy band diagrams of FIGS. 2A and 2B. FIG. 2A is an enlarged energy band diagram showing the channel portion of a conventional n-type GaInAs channel FET uniformly doped with Si. In FIG. 2A, reference numeral 21 denotes a GaInAs channel layer; 22, a GaAs buffer layer; 23, a cap layer; 24, a conduction band level; and 25, a valence band level. FIG. 2B is an enlarged energy band diagram showing the channel portion of the n-type GaInAs channel FET of this embodiment. In this energy band diagram, parts corresponding to the epitaxial layers 2 to 6 in FIG. 1A to 1D are represented by the same reference numerals as in FIG. 2B, reference numeral 26 denotes a conduction band level, and reference numeral 27 denotes a valence band level. In FIGS. 2A and 2B, reference symbols E.sub.0 and E.sub.1 denote quantized energy levels, and curves 31 and 32 indicated by alternate long and short dash lines represent presence probabilities of electrons at the energy levels E.sub.0 and E.sub.1, respectively.

As is apparent from FIGS. 2A and 2B, in the conventional FET (FIG. 2A), a region in which carrier electrons are present is mostly located in an n-type GaInAs quantum well formed by the channel layer 21. Therefore, the carrier electrons are scattered by Si atoms in the GaInAs layer and a sufficient overshoot-effect of drift velocity cannot be obtained. For this reason, the source resistance is increased, and the transconductance (g.sub.m) is decreased. In contrast to this, in the FET of this embodiment, since a part of a region in which carrier electrons are present overlaps the undoped GaInAs graded layers 3 and 5, the carrier electrons are permitted to move faster in this FET than in the conventional FET. For this reason, a low source resistance and a high transconductance (g.sub.m) can be obtained.

Since the n-type GaInAs channel layer 4 which is not lattice-matched with GaAs is sandwiched between the GaInAs graded layers 3 and 5, distortion caused by a lattice mismatch can be relieved, and transportation characteristics of carrier electrons are expected to be improved.

The steps of the second embodiment will be described below with reference to the sectional views of FIGS. 1A to 1D showing the steps. A GaAs substrate 1 is used as a semiconductor substrate, and a buffer layer 2 (background p-type, p=3.times.10.sup.15 cm.sup.-3) which is an undoped GaAs monocrystalline layer is epitaxially grown on the GaAs substrate 1 by, e.g., an organometallic vapor phase epitaxy method (OMVPE method), to have a thickness of 5,000 .ANG. (FIG. 1A). An undoped Ga.sub.1-X In.sub.X As graded layer 3 which is not originally lattice-matched with GaAs is formed on the resultant structure to have a thickness of 50 .ANG. (FIG. 1B). In this embodiment, an In composition ratio X of the layer 3 is set to be 0.15. A channel layer 4 made of n-type Ga.sub.1-X In.sub.X As (n=8.times.10.sup.18 cm.sup.-3) and uniformly doped with Si is grown on the undoped Ga.sub.1-X In.sub.X As layer 3 to have a thickness of 50 .ANG.. Note that the In composition ratio of the channel layer 4 is set to be equal to the In composition ratio of the undoped Ga.sub.1-X In.sub.X As layer 3, i.e., X=0.15. In addition, an undoped Ga.sub.1-X In.sub.X As layer 5 having the same composition as that of the undoped Ga.sub.1-X In.sub.X As layer 3, is formed on the channel layer 4 to have a thickness of 50 .ANG. (FIG. 1C). Each of the epitaxial layers 3 to 5 has a thickness of 50 .ANG. as described above, thereby obtaining a total film thickness of 150 .ANG.. This thickness of 150 .ANG. is smaller than a critical film thickness at which dislocation is caused by a lattice mismatch.

Thereafter, a cap layer 6 made of an undoped GaAs single crystal is grown on the undoped Ga.sub.1-X In.sub.X As layer 5 to have a thickness of 400 .ANG.. Finally, a gate electrode 7, a source electrode 8, and a drain electrode 9 are formed on the cap layer 6, thereby constituting the FET according to this embodiment (FIG. 1D).

An operation of the FET manufactured as described above will be described below with reference to the energy band diagrams of FIGS. 3A and 3B. FIG. 3A is an enlarged energy band diagram showing the channel portion of a conventional n-type GaInAs channel FET uniformly doped with Si. In FIG. 2A, reference numeral 21 denotes a GaInAs channel layer; 22, a GaAs buffer layer; 23, a cap layer; 24, a conduction band level; and 25, a valence band level. FIG. 3B is an enlarged energy band diagram showing the channel portion of an n-type GaInAs channel FET of this embodiment. In this energy band diagram, parts corresponding to the epitaxial layers 2 to 6 in FIG. 3B are represented by the same reference numerals as in FIG. 1A to 1D, reference numeral 28 denotes a conduction band level, and reference numeral 29 denotes a valence band level. In FIGS. 3A and 3B, reference symbols E.sub.0 and E.sub.1 denote quantized energy levels, and curves 31 and 32 indicated by alternate long and short dash lines represent presence probabilities of electrons at the energy levels E.sub.0 and E.sub.1, respectively.

As is apparent from FIGS. 3A and 3B, in the conventional FET (FIG. 3A), a region in which carrier electrons are present is mostly located in an n-type GaInAs quantum well formed by the channel layer 21. Therefore, the carrier electrons are scattered by Si atoms in the GaInAs layer and a sufficient overshoot-effect of drift velocity cannot be obtained. For this reason, the source resistance is increased, and the transconductance (g.sub.m) is decreased. In contrast to this, in the FET of this embodiment, since a part of a region in which electrons are present overlaps the undoped GaInAs graded layers 3 and 5, the carrier electrons are permitted to move faster in this FET than in the conventional FET. For this reason, a low source resistance and a high transconductance (g.sub.m) can be obtained.

Although the n-type GaInAs channel layer 4 and the undoped GaInAs layers 3 and 5 which sandwich the n-type GaInAs channel layer 4 are not originally lattice-matched with GaAs, since the total thickness of the three layers is smaller than the critical film thickness at which dislocation is caused by lattice distortion, lattice defects do not occur.

An embodiment wherein electrodes are formed is shown in FIGS. 4A and 4B.

As in the first and second embodiments, when a cap layer 6 is made of GaAs, after a gate electrode 7 is formed on the cap layer 6, Si ions are implanted to form contact regions 10 at the portions of the source electrode 8 and the drain electrode 9. The source electrode 8 and the drain electrode 9 are formed in the contact regions 10 (FIG. 4A).

Unlike the first and second embodiments, when the cap layer 6 is made of AlGaAs, GaInAs layers doped with Si or GaAs layers doped with Si are formed as contact layers 11 on the cap layer 6 at the portions of the source electrode 8 and the drain electrode 9. In addition, the gate electrode 7 is formed on the cap layer 6 having a recess structure, and the source electrode 8 and the drain electrode 9 are formed on the contact layers 11 (FIG. 4B).

From the invention thus described, it will be obvious that the invention may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.