Method for Fabrication of Close-Tolerance Lines and Sharp Emission Tips on a Semiconductor Wafer

The invention relates in general to a method for fabricating submicron lines on wafers and sharp tips for field effect device and, in particular, to the method for forming a close-tolerance line or sharp tip in a semiconductor wafer substrate or layer using a loose tolerance trench, or well.

Often times in semiconductor wafer fabrication, it is desirable to fabricate a line having closer tolerances than photolithography or other line-forming methods. These close-tolerance lines are utilized for field effect devices and other integrated circuit devices produced on semiconductor wafers. In the past, it has been necessary to either purchase expensive precision fabrication equipment or relax the tolerances. Accordingly, it would be desirable to have a method for fabricating a close-tolerance line or sharp tip without requiring close-tolerance precise fabrication equipment. One example of use of this line would be for a narrow gate on a MOS FET device.

The present invention is a novel method for producing close-tolerance sharp tips or narrow lines in a semiconductor wafer substrate or layer where the fabrication equipment, i.e., photolithography apparatus, is only capable of producing a larger, looser tolerance line. The first step of the method is to fabricate a trench in a first layer over the substrate using the looser tolerance photolithography or other fabrication equipment available. The next step is to deposit a non-conformal material over the wider line and substrate, thereby forming a void with a uniform, close-tolerance width regardless of variations in the previously formed trench. Next, a chemical mechanical polish (CMP) process is performed to planarize and expose the close-tolerance width dimension void. An etch-resist conformal material is then deposited over the first layer and in the void. The conformal material is then planarized leaving material only in the void to form a mask of a predetermined close-tolerance width. The walls of the non-conformal material and the first layer are then etched away, leaving a ridge or wall under the mask of the same close-tolerance thickness as the void, disposed above the original wafer substrate in a position where a new line of close tolerance is to be formed at the predetermined desired position along the substrate.

This formed, two-layer ridge or wall then acts as a hard mask for subsequent patterning of the substrate by etching or other fabrication techniques. The ridges or lines formed in this manner can be in the range of 0.1 to 0.15 .mu.m.

In a second embodiment, the same process can be used to form a sharp, pointed tip such as that desired for high resolution field emission tips used in cold cathode emitters that are utilized in the field emitter display devices. In this case, the tip mask is formed as a cylindrical vertical pillar in lieu of a line or linear trench.

Other objects, advantages, and capabilities of the present invention will become more apparent as the description proceeds.

FIG. 1 is a perspective view of a submicron line formed by the present inventive method;

FIG. 2 is a perspective view of a sharp tip formed by the present method;

FIG. 3 is a partial side section view of an integrated circuit (IC) semiconductor die;

FIG. 4 is a partial side section view of an upper section the IC semiconductor die of FIG. 3 after etching;

FIG. 5 is a partial side section view of an IC semiconductor die of FIG. 4 after non-conformal layering;

FIG. 6 is a partial side section view of an IC semiconductor die of FIG. 5 after planarizing;

FIG. 7 is a partial side section view of an IC semiconductor die of FIG. 6 after conformal layering;

FIG. 8 is a partial side section view of an IC semiconductor die of FIG. 7 after a second planarizing of the conformal layer;

FIG. 9 is a partial side section view of an IC semiconductor die of FIG. 8 after a selective etching;

FIG. 10 is a partial side section view of an IC semiconductor die of FIG. 9 after a second selective etching;

FIG. 11 is a partial side section view of an IC semiconductor die of the final submicron line;

FIG. 12 is a partial side section view of an IC semiconductor die having a pair of trenches of differing widths filled with a non-conformal layer;

FIG. 13 is the partial side section view of an IC semiconductor die having a pair of trenches of differing widths of FIG. 12 now filled with a non-conformal layer of deeper depth;

FIG. 14 is a graph of void width as a function of trench width;

FIG. 15 is a partial side section view of an IC semiconductor die having a non-conformal layer over different width trenches;

FIG. 16 is a partial side section view of an IC semiconductor die having a non-conformal layer over different width trenches after planarization;

FIG. 17 is a partial side section view of an IC semiconductor die having different width lines;

FIG. 18 is a partial section perspective view of a sharp point "mask" process; and

FIG. 19 is a partial section perspective view of a completed sharp point.

The final submicron line 10 fabricated by this inventive process can be seen in FIG. 1. This line which may be used as a gate in a final integrated circuit (IC) device and can have a width dimension of 0.1 .mu.m as at 12 which is significantly narrower than the width available by current photolithography methods. The line has been fabricated in substrate 14 and has a gate oxide layer 16 under the line 10.

In a second embodiment, a sharp point 20 may be seen in FIG. 2 fabricated by the same basic process. A sharp point is needed in the fabrication of a field emitter device having a cold cathode (point) 20, a control grid, and an anode (not shown) on a substrate 22. The process for forming the point 20 is similar to the submicron line process except for the shape, i.e., a circular pyramid 20 in lieu of a line 10 (FIG. 1).

The process for submicron line formation 10 will be described by referring to FIGS. 3-11. FIG. 3 indicates the typical beginning steps in IC semiconductor wafer. The substrate 14 has a typical gate oxide layer 16 formed over substrate 14 and a typical gate polysilicon layer 24 deposited over the oxide 16. A mask oxide layer 28 is deposited over the gate polysilicon layer 24. FIG. 4 shows the results of the photolithography method of forming a trench through a photoresist layer 30 and the mask oxide layer 28 by an etching process. After etching, the photoresist layer 30 is removed by a stripping process. The line or trench 32 is then filled by depositing a non-conformal material 34 as in FIG. 5 which in this inventive process forms a tear-drop shaped void or gap 36 at the center of line 32. A good material for this layer would be plasma silicon oxide (SiO.sub.2) or plasma silicon nitride (Si.sub.3 N.sub.4). Plasma oxide will be used in the described process flow. The depth of layer 34 is controlled and is dependent on the width and depth of line 32. As shown, a typical void width is about 0.1 .mu.m as at 38 when the depth of the non-conformal layer is 0.45 .mu.m as at 40.

After planarizing the non-conformal material 34 by a chemical mechanical polish, the surface and exposed void 36 appears as in FIG. 6. A key aspect of this invention is the ability to form a void of consistent width 38 without being affected by minor variations in the width of gap 32 which is due to the physical limitations of the photolithography and etch processes.

Referring now to FIG. 7, a conformal mask material 42 is deposited and may consist of any conformal material capable of having a differing plasma etch rate than layer 34. For the process flow shown, polysilicon is deposited by a low pressure chemical vapor deposition (LPCVD) process and is representative of such conformal material.

A second chemical mechanical polishing is performed to remove all the conformal material 42 except that within void 36, as illustrated in FIG. 8. An anisotropic oxide etch simultaneously etches both the plasma oxide 34 and masking oxide 28 down to gate polysilicon layer 24, as in FIG. 9. Next, a plasma polysilicon etch can be done to pattern the underlying oxide 16 and gate polysilicon 24 to form the submicron (0.1 .mu.m) line as illustrated in FIG. 10. Also, note that the conformal polysilicon layer 42 is simultaneously etched away in this polysilicon etch step. FIG. 11 illustrates the submicron gate material 24 and gate oxide 16 over substrate 14 after typical ion implantation at 44. The remaining steps in the process are dependent on the type of device being fabricated.

Referring now to FIGS. 12 and 13, the capability to form lines of consistent close-tolerance width in spite of variations in trench width 50,52 is demonstrated. Trench lines 50 and 52 have a typical width dimension of 0.4 .mu.m and 0.6 .mu.m, respectively, and the deposition of non-conformal layer 34 to a depth of about 0.3 .mu.m is shown at 54. Void width at 56 is shown about 0.1 .mu.m while void 58 at this point is about 0.2 .mu.m. FIG. 13 shows the effect of continuing the deposition of layer 34 to about 0.45 .mu.m as at 60. This deposition to a depth of 0.45 .mu.m at 60 has resulted in closing the void at the top section 61 and narrowing the void at 58 to a new void width of 0.1 .mu.m at 62, thereby matching the void width 56.

The graph of FIG. 14 is used to illustrate the variation of void width as a function of trench width. Using a conformal material would result in linear relationship at 64. The ideal response would be a flat line as at 66, and a desired response or relationship is shown at 68 which indicates about a 0.02 .mu.m change in void width for a 0.2 .mu.m change in trench width as at 70. For trench widths over 0.7 .mu.m, the line 68 would curve upward so as to be parallel to line 64 as at 71 (FIG. 14).

Referring to FIGS. 15-17, it is also demonstrated that it is also possible to purposely fabricate wide lines and narrow lines simultaneously by controlling the non-conformal layer depth 72. In this instance, the non-conformal layer 74 is above two significantly different width trenches 76 and 78. When these trenches have the conformal mask material 80 deposited and then planarized down to the polysilicon layer 82, the cross-section appears as at FIG. 16. A final gate material 84 cross-section shown in FIG. 17 would have a narrow gate line 86 and wider gate line 88 after etching down to gate oxide 89. It is noted that for the wider trench widths, the final mask width can be controlled by careful control of the non-conformal mask material depths as at 72' (FIG. 15), i.e., the deeper the mask depth deposited, the narrower the final gap as at 91 (FIG. 15).

The cross-section perspective view of FIG. 18 discloses the fabrication process to make a sharp point for a cold cathode or similar device as shown in FIG. 19. In this case, we have polysilicon layer 90 over the substrate 92 and a non-conformal circular plug 94 in a well 95 in lieu of a trench or line (FIGS. 6-8) and the hard mask TEOS 96 or other material sets within well 95 surrounded by the plug 94. Isotropic etching of the substrate 92 and mask and plug removal would expose the cone-shaped sharp point as at 98 (FIG. 19) of a very small diameter, on the order of 0.1 micron. A cylindrical pillar could also be formed by use of an anisotropic etch process.

It is also possible to fabricate circular gates and anodes surrounding the sharp tip 98 by a similar process.

While preferred embodiments of the invention have been disclosed, various modes of carrying out the principles disclosed herein are contemplated as being within the scope of the following claims. Therefore, it is understood that the scope of the invention is not to be limited except as otherwise set forth in the claims.