Slew-Rate Limited Voltage Controlled Oscillator Control Voltage Clamp Circuit

This invention relates to voltage-controlled oscillator clamp circuits and is particularly concerned with clamp circuits that are slew-rate limited in the clamping action.

Multiple line access to digital telecommunications equipment necessitates its organization into groupings of similar circuit packs, for example into shelves of receivers and transmitters. Typically, clock signals needed by the individual transmitters are provided by a single transmitter designated as a master, with respect to clocking, and the remaining transmitters being slaved from the master. Each transmitter also typically has a local clock circuit comprising for example, a voltage-controlled crystal oscillator (VCXO). The master transmitter could either phase-lock to a standard clock signal or use its internal VCXO. Transition between the reference clock signal and the internal VCXO is typically achieved using a clamping circuit which clamps the VCXO to a preset reference voltage representing a desired free-running frequency for the VCXO. An individual circuit pack may be able to tolerate the phase shift introduced by the clamping action, however when several circuit packs are slaved to a master circuit pack for clocking, rapid phase shifts may cause problems. It is desirable to limit the rate at which the master circuit pack changes its frequency.

An object of the present invention is to provide an improved voltage-controlled oscillator clamping circuit.

In accordance with another aspect of the present invention there is provided a clamp circuit for use in a phase-locked loop clock circuit, the phase-locked loop including a phase detector with inputs for reference clock signal and oscillator signal, a loop filter with an input connected to the phase detector, and a voltage-controlled oscillator with an output connected to the phase detector, the clamping circuit connected between an output of the loop filter and an input of the voltage-controlled oscillator, said clamping circuit including: a bypass circuit for connecting the loop filter to the input of the voltage-controlled oscillator; resistor-capacitor time constant means for providing a time constant varying potential; first clamping means for clamping the input of the voltage-controlled oscillator to the time constant varying potential; and control means, responsive to a clamping signal for selectively disabling the bypass circuit and enabling the first clamping means; whereby the resistor-capacitor time constant means slew-rate controls the potential applied to the voltage-controlled oscillator.

In accordance with another aspect of the present invention there is provided a clock circuit comprising an input terminal for receiving a reference clock signal, an output terminal for providing a clock signal; and a phase-locked loop; said phase-locked loop including: a phase detector having two inputs, one connected to the input terminal, and an output, a loop filter having an input connected to the output of the phase detector and having an output, a clamping circuit having a first input connected to the output of the loop filter, a second input for receiving a clamping signal, and an output, and a voltage-controlled oscillator having an input connected to the output of the clamp circuit and an output connected to the output terminal and the other input of the phase detector; said clamping circuit including: a bypass circuit for connecting the output of the loop filter to the input of the voltage-controlled oscillator, resistor-capacitor time constant means for providing a time constant varying potential, first clamping means for clamping the input of the voltage-controlled oscillator to the time constant varying potential, and control means, responsive to a clamping signal for selectively disabling the bypass circuit and enabling the first clamping means and whereby the resistor capacitor time constant means slew-rate controls the potential applied to the voltage-controlled oscillator.

In an embodiment of the present invention the clamp circuit further comprising a second clamping means for clamping the output of the loop filter to a reference potential.

Conveniently, the control means comprise first and second comparators, each having one input connected to a reference potential and the other input connected to the second input of the clamping circuit, and an analog multiplexer, having an input connected to the second input of the clamping circuit.

Conveniently, the time constant means comprises a capacitor and a voltage follower connected to the first clamping means and a resistor selectively connected between the capacitor and ground via the analog multiplexer, for providing a time constant varying potential thereto.

An advantage of the present invention is providing a slew-rate limited potential when clamping the controlled oscillator for free-running operation, thereby avoiding sudden phase or frequency shifts.

The present invention will be further understood from the following description with reference to the drawings in which:

FIG. 1 illustrates a phase-locked loop circuit in accordance with an embodiment of the present invention; and

FIG. 2 schematically illustrates the loop filter, slew-rate limited clamp circuit and voltage-controlled oscillator of FIG. 1.

Similar references are used in different Figures to denote similar components.

Referring to FIG. 1, there is illustrated a phase-locked loop circuit in accordance with an embodiment of the present invention. The phase-locked loop includes a phase detector 10, a loop filter 12, a slew-rate limited clamp circuit 14, and a voltage-controlled oscillator (VCXO) 16 serially connected in a loop. The phase detector has an input 18 for a reference signal. The VCXO has an output 20 for a clock signal. The clamp circuit 14 has an input 22 for a clamp signal.

In operation, when a clamp signal is not asserted, the phase-locked loop is in a closed state and matches the frequency of the VCXO 16 to that of the reference signal applied to the input 18, in a known manner, by comparing the phase of the VCXO 16 output to the reference signal using the phase detector 10. The phase detector 10 provides a voltage signal which is filtered, to remove any noise component outside the bandwidth of the phase-locked loop, by the loop filter 12, to produce a control voltage v.sub.c, the control voltage v.sub.c is then applied to the VCXO 16. In this case, the clamp circuit 14 is internally bypassed.

When a clamp signal is asserted, the clamp circuit opens the loop, thereby removing the control voltage v.sub.c from the VCXO, and applies a predetermined, fixed voltage v.sub.f to the VCXO. As a result the VCXO acts as a free-running, fixed-frequency oscillator. Depending upon the difference in frequency between the fixed-frequency and the reference frequency, a relatively large frequency or phase step could occur on assertion of the clamp signal. As a relatively large step may cause problems, it is desirable to limit the slew-rate of the change between the control voltage v.sub.c and the fixed voltage v.sub.f. Thus, the clamp circuit 14 includes slew-rate control as described in further detail hereinbelow.

Referring to FIG. 2, there is schematically illustrated the loop filter, slew-rate limited clamp circuit and voltage-controlled crystal oscillator of FIG. 1. The loop filter 12 includes an operational amplifier 30 having noninverting and inverting inputs coupled to inputs 32 and 34, respectively, and an output 36. The clamp circuit 14 includes an analog MUX 40, comparators 42 and 44, diode networks 46 and 48, a voltage follower 50, a capacitor 52, and bypass circuit 54. The clamp signal input 22 is connected to the select input of analog MUX 40, the noninverting input of comparator 42 and the inverting input of comparator 44. The noninverting input of comparator 44 and the inverting input of comparator 42 are connected to a positive TTL reference voltage V.sub.ref. Outputs of comparator 42 and comparator 44 are coupled to anode and cathode ends, respectively, of diode networks 46 and 48.

The diode network 46 includes four diodes 56, 58, 60 and 62, series connected in pairs and in the same orientation, to form two parallel paths, one being diodes 56 and 58 with a node 64 therebetween, the other being diodes 60 and 62 with a node 66 therebetween. Similarly, the diode network 48 includes four diodes 68, 70, 72 and 74, series connected in pairs and in the same orientation, to form two parallel paths, one being diodes 68 and 70 with a node 76 therebetween, the other being diodes 72 and 74 with a node 78 therebetween. The nodes 64, 66, 76 and 78 are connected to the VCXO 16, the output of voltage follower 50, ground, and the output of the loop filter 12, respectively.

Inputs of analog MUX 40 are coupled to ground and the node 64 via resistors 86 and 88, respectively. The output of analog MUX 40 is connected to the input of voltage follower 50, which is capacitively coupled to ground via the capacitor 52. The bypass circuit 54 includes a J-FET 80, a biassing resistor 82, and a diode 84. The diode 84 has its anode connected to the output of comparator 42 and its cathode connected to the gate of J-FET 80. Drain and source terminals of J-FET 80 are connected to node 78 and 64, respectively.

The VCXO input includes a resistor 90 connected to the input of the VCXO and a variable resistor 92 coupled to a -4.5 V supply.

In operation, when no clamp signal is asserted at the input 22, that is TTL logic `0` is present, the comparator 42 has an output, negative supply voltage and the comparator 44 has an output, positive supply voltage. Hence, the diode networks 46 and 48 are reversed biassed. In this state, a current flows through the biassing resistor 82 to the -4.5 V supply connected to the variable resistor 92, thereby turning the J-FET 80 `ON`. Thus, the clamping circuit is bypassed and the phase-locked loop is closed. In this state, the analog MUX 40 connects the capacitor 52, via the resistor 88, to the node 64 thereby causing the capacitor 52 to be charged to an average of the control voltage of the loop v.sub.c.

When a logic `1` TTL clamp signal is asserted at the input 22, the outputs of comparators 42 and 44 become saturated to the positive supply voltage and the negative supply voltage, respectively. The diode networks 46 and 48 are thereby forward biassed, causing the potential to be the same at nodes 64 and 66 and at nodes 76 and 78. The output of comparator 42 via the diode 84 makes the voltage at the gate of J-FET 80 more positive than the source of J-FET 80, thereby turning the J-FET 80 `OFF`. This opens the phase-locked loop. The logic `1` TTL clamp signal is also applied to the select input of analog MUX 40, which in response thereto connects the capacitor 52 to ground via the resistor 86. The time constant R.sub.86 C.sub.52 sets the slew-rate of the voltage to which the VCXO is clamped in the following manner. The voltage follower 50 holds the node 66 at the voltage on the capacitor 52, and as the voltage drops across diodes 60 and 56 are the same, the same voltage appears at the node 64, which is connected to the input of VCXO 16 via the resistor 90. As the capacitor 52 discharges, the voltage controlling the VCXO drops until the fixed voltage v.sub.f, set by the variable resistor 92, is reached. Subsequently, the VCXO operates as a free-running fixed-frequency oscillator as long as the clamp signal remains at a TTL logic `1`. The capacitor 52 continues to discharge approaching ground potential.

When the clamp signal returns to a TTL logic `0`, the diode networks 46 and 48 are reverse biased, the J-FET 80 is turned `ON`, and the analog MUX is switched so that the output of the loop filter 12 is applied to the capacitor 52. The loop filter integrates from ground potential to a new control voltage at a rate set by the loop parameters.

Numerous modifications, variations and adaptations may be made to the particular embodiments of the invention described above without departing from the scope of the invention, which is defined in the claims.