US 5,329,152 AGrant

Ablative Etch Resistant Coating for Laser Personalization of Integrated Circuits

Issue Date:1994-07-12

•17 Claims

•18 Drawing Sheets

Abstract

A programmable integrated circuit for prototyping applications including a first patterned metal layer, an insulation layer formed over the first metal layer and a second patterned metal layer formed over the insulation layer, the first and second patterned metal layers being formed with selectably removable regions, the insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions a coating comprising a layer of a dielectric material of high laser radiation absorption coefficient.

Metadata

Assignee

Quick Technologies Ltd.

Inventors

Meir I. Janai
Zvi Orbach
Alon Kapel
Sharon Zehavi

Application Information

Application Number:US 8253587

Filing Date:1992-01-24

Priority Date:1986-11-26

Art Unit:258

Classifications

IPC:

H01L 2702

Field of Search:

257529;530;665

Patent Drawings (18 sheets)

Description

Brief Description of the Drawings

The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings wherein

FIG. 1 is a cross-sectional illustration of a portion of a typical integrated circuit;

FIG. 2 is a cross-sectional illustration of a typical integrated circuit having apertures formed in insulating layers thereof;

FIG. 3A is a cross-sectional illustration of a typical integrated circuit having apertures formed in insulating layers thereof and coated with a metal etch-resistant coating;

FIG. 3B is a cross-sectional illustration of the integrated circuit of FIG. 2 coated with a two layer etch-resistant coating;

FIG. 3C is a cross-sectional illustration of the integrated circuit of FIG. 2 coated with a three layer etch-resistant coating;

FIG. 3D is a cross-sectional illustration of the integrated circuit of FIG. 2 coated with a three-layer etch resistant coating wherein the lower layer is a planarization layer.

FIG. 4A is a cross-sectional illustration of the integrated circuit of FIG. 3A after laser removal of the etch-resistant coating from one of the above-selected apertures;

FIG. 4B is a cross-sectional illustration of the integrated circuit of 3B after laser removal of the laser absorbing layer and most of the etch-resistant coating from one of the above-selected apertures;

FIG. 4C is a cross-sectional illustration of the integrated circuit of FIG. 3C after laser removal of the laser absorbing layer and most of the middle layer of the etch-resistant coating;

FIG. 4D is a cross-sectional illustration of the integrated circuit of FIG. 4B after dry etching of the etch-resistant layer;

FIG. 4E is a cross-sectional illustration of the integrated circuit of FIG. 4C after selective etching of the middle layer of the etch-resistant coating;

FIG. 4F is a cross-sectional illustration of the integrated circuit of FIG. 4E after selective etching of the bottom layer of the etch-resistant coating;

FIG. 4G is a cross-sectional illustration of the integrated circuit of FIG. 3D after laser removal of the laser absorbing layer and the middle etch resistant layer,

FIG. 4H is a cross-sectional illustration of the integrated circuit of FIG. 4G after etching of the planarization layer,

FIG. 5A is a cross-sectional illustration of the integrated circuit of FIG. 4A after chemical etching of the metal underlying the removed etch-resistant coating;

FIG. 5B is a cross-sectional illustration of the integrated circuit of FIG. 4D after dry etching of the metal underlying the removed etch resistant coating;

FIG. 5C is a cross-sectional illustration of the integrated circuit of FIG. 4F after dry etching of the metal underlying the removed etch-resistant coating and

FIG. 6 is a cross-sectional illustration of the integrated circuit of FIGS. 4A, 4B, and 4C after metal etching and removal of the etch resistant coating.

Detailed Description of Preferred Embodiments

Reference is now made to FIGS. 1-6, which illustrate a technique for manufacture of a prototype integrated circuit in accordance with a preferred embodiment of the present invention.

FIG. 1 illustrates in cross-section (not to scale) a portion of a typical integrated circuit comprising a substrate layer 10, typically formed of silicon or gallium arsenide. A plurality of ion implanted or diffusion doped layers 12 and 13 are disposed over substrate layer 10 and are covered by insulative layers 14 and 15, such as layers formed of silicon oxide, silicon nitride or polyimide. A conducting layer, such as a polysilicon gate 16, lies over layers 14 and 15. Gate 16, layer 15 and layer 14 are in turn covered by a further insulating layer 17, such as a layer formed of phosphorous-doped or undoped silicon oxide, silicon nitride or polyimide. Contact holes are formed in insulating layers 15 and 17 in order to provide electrical contact between layers 10, 12, 13 and 16 at required locations.

A patterned conducting metal layer 18, such as a layer formed of aluminum, copper, gold, titanium, molybdenum, nickel, chrome, tungsten or combinations of the above, with or without silicon, is located over layer 17 and in local communication with a portion of diffusion layer 13. A further insulating layer 19, such as a layer formed of silicon oxide, silicon nitride or polyimide, overlies layers 17 and 18. An additional patterned conducting metal layer 20 may be locally deposited over insulative layer 19. An insulative protective layer 21 overlies layers 19 and 20.

Referring now to FIG. 2, there is seen an integrated circuit of the same configuration as that illustrated in FIG. 1, and formed in accordance with the present invention. It is seen that insulative layers 19 and 21 have been formed with discrete apertures 22, indicated by reference letters A and B, so as to expose metal layers 18 and 20 respectively. In accordance with the present invention, apertures are defined in the insulative layer or layers at all locations at which it may be desired to remove metal thereunder.

According to a preferred embodiment of the present invention, shown in FIG. 3A, the configuration shown in FIG. 2 is further coated by an etch resistant volatile layer 30, typically formed of amorphous silicon (a-Si). Layer 30 is selected so as to absorb, at room temperature, at least 10% of the energy of a pulsed laser such as a Q-switched Nd+YAG laser and is of typical thickness between 3000 Angstrom and 10,000 Angstrom.

Preferably layer 30 is a-Si deposited by sputtering or by low-pressure, plasma-enhanced chemical vapor deposition at a temperature below 250 degrees Celsius so as to provide good step coverage without damaging the properties of metal layers 18 and 20 or the contact properties of the metal to semiconductor layers 10, 12, 13 and 16.

The chemical makeup of layer 30 preferably includes at least one of the following: As.sub.2 S.sub.3, nitrocellulose, polyimide, or a novolac resin with a high concentration of a laser absorbing dye, amorphous silicon (a-Si) or a-Si alloy such as a-Si:H, a-Si.sub.x O.sub.1-x :H, a-Si.sub.x N.sub.1-x :H, a-Si.sub.x O.sub.y N.sub.1-x-y :H, where x is greater than or equal to 0.5 and x+y are less than or equal to 1.

The a-Si layer may be phosphorous-doped or boron-doped with doping levels up to 10%. The hydrogen content may be up to 30%.

Referring now to FIG. 4A, it is seen that the amorphous silicon layer 30 is blown away by the application of laser energy at selected locations over apertures 22, corresponding to locations where it is desired to remove the underlying metal. The laser radiation may be provided by a Q-switched frequency doubled NdYAG laser with pulse energy typically between 0.2 J/cm.sup.2 and 10 J/cm.sup.2 and pulse duration 50 nsec. Alternatively, a pulsed laser diode or Excimer laser may be employed for this purpose. A typical peak power density is 5.times.10.sup.7 W/cm.sup.2.

Further in accordance with an embodiment of the invention, etchable regions may be selectably defined by dissolving the etch resistant layer with the underlying metal by means of suitable laser radiation. This may be achieved, for example, where layer 30 is formed of amorphous silicon and layer 18 is formed of aluminum or gold. Under laser radiation the amorphous silicon is heated and reacts with the aluminum to form microscopic metallic filaments through the amorphous silicon coating as well as microcrystalline aluminum-doped silicon grains in the aluminum layer. This causes the etch resistant layer at the selected regions to become relatively transparent to metal etchants. In this embodiment of the invention it is not necessary to use a laser with high peak power density, however, at laser pulse durations shorter than 1 microsecond with pulse energy density above 10 J/cm.sup.3, part of the etch resistant layer may also be blown away. Typically the laser radiation may be provided by a concentrated frequency doubled Nd+YAG laser with pulse duration up to 0.1 second and peak power density below 10.sup.6 W/cm.sup.2. Alternatively an argon ion laser or a pulsed laser diode or Excimer laser may be employed for this purpose.

Additionally in accordance with an embodiment of the invention, laser radiation may be substituted by any other suitable type of radiation, including, for example, electron beam radiation and focused ion beam radiation. A suitable ion beam has 10.sup.19 ions/cm.sup.2 and an energy flux above 10 J/cm.sup.2.

Following definition of etchable regions underlying the amorphous silicon layer 30 at the selected locations, the integrated circuit blank is subjected to etching typically by an aluminum etchant, such as nitric acid combined with phosphoric acid and acetic acid, in solution for removal of the metal underlying those of apertures 22 having the etchable regions defined thereunder. Alternatively the metal removal may be achieved by plasma containing chlorine. It is appreciated that in any case layer 30 serves to protect all of the remaining surface of the integrated circuit, including those surfaces on which apertures 22 have been defined, against etching or metal removal by any other technique. FIG. 5A illustrates the partially completed integrated circuit after the above-described selected metal removal.

Following metal removal, the amorphous silicon layer 30 may be removed as by an amorphous silicon wet or dry etchant, such as a solution of HF:HNO.sub.3 :CH.sub.3 COOH, Hydrazene of XeF gas. This stage is illustrated in FIG. 6.

Additionally in accordance with an embodiment of the present invention, an anti-reflective coating may be formed over the etch-resistant layer in order to reduce the energy requirements of the laser radiation.

Reference is now made to FIG. 3B, which is a cross-sectional illustration of the integrated circuit of FIG. 2 coated with a two layer etch-resistant coating;

According to a preferred embodiment of the present invention, the etch resistant coating includes an insulation layer, indicated by reference numeral 40, which has good resistivity to metal etchants and good step coverage and is preferably composed of a dielectric material such as Si.sub.3 N.sub.4 (silicon nitride).

Formed over layer 40 is a laser radiation absorbing layer 42, typically composed of amorphous silicon (a-Si), which absorbs laser radiation in the visible and near UV range and particularly at 5320 Angstroms.

Upon application of laser radiation to selected locations such as location A, all of layer 42 and most of layer 40 is removed, as is seen in FIG. 4B. This would be usually effected by a Q-switched Nd+YAG laser at an energy density between 5 and 10 J/cm.sup.2.

Following application of laser radiation, a dry etch step may take place, employing, for example an RIE etcher such as Plasma Term System 72, commercially available from Plasma Therm Inc. of the U.S.A., with a CF.sub.4 gas at a plasma RF power of 200W, for a period of 60-120 seconds. This step is effective to completely clean the layer 40 at the selected locations, such as location A, while leaving sufficient thickness of the etch resistant layer to ensure etch resistance at non selected locations. The result of application of this step is seen in FIG. 4D.

Thereafter a conventional metal etch step may take place for disconnecting the metal links at the selected locations. The result of this step is shown in FIG. 5B.

Following the metal etching step, the layers 40 and 42 may be completely removed from all locations to enable subsequent probing and bonding of the integrated circuit. The result of this step is shown in FIG. 6.

Reference is now made to FIG. 3C, which is a cross-sectional illustration of the integrated circuit of FIG. 2 coated with a three layer etch-resistant coating.

According to an alternative to the embodiment of the invention described above and illustrated in FIG. 3B, in FIG. 3C there is shown an arrangement wherein the etch resistant coating includes a two-layered insulation layer, indicated by reference numeral 50, including a lower layer 52 of silicon oxide (SiO.sub.2) and an upper layer 54 of silicon nitride (Si.sub.3 N.sub.4). The remainder of the integrated circuit may be identical to that shown in FIG. 3B. Layer 52 may have a typical thickness of between 1000 and 4000 angstrom and layer 54 may have a typical thickness of between 3000 and 10,000 angstrom.

This arrangement provides a convenient etch stop between layers 54 and 52 and between layers 52 and 21 which is useful during the removal of etch resistant layers 42 and 50.

FIG. 4C shows the structure of FIG. 3C after the application of laser radiation to selected locations such as 22A.

Following application of laser radiation, selective etching of layer 54 removes the residue of this layer at location 22A, as shown in FIG. 4E. Further selective etching of layer 52 removes the bottom layer at location 22A, as shown in FIG. 4F. The underlying metal can then be removed as shown in FIG. 5C.

Reference is now made to FIG. 3D which is a cross-sectional illustration of the integrated circuit of FIG. 2, coated with a three layer etch resistant coating, wherein the bottom layer of the coating is a planarization layer.

In accordance with the alternative embodiment illustrated in FIG. 3D, the bottom layer, indicated by reference numeral 56, may be a planarization layer composed of polyimide, probimide, spin-on glass or similar dielectric coating. The remainder of the integrated circuit may be identical to that shown in FIG. 3C. The planarization layer 56 may have a thickness preferably between 0.5 and 2 micron.

This arrangement provides a convenient etch stop between layers 56 and 21 and, additionally, it allows uniform laser ablation of the etch resistant coating over different metal levels such as 18 and 20 at locations 22A and 22B, respectively, of FIG. 2. FIGS. 4G and 4H show the corresponding steps of laser removal of the upper two layers of the etch resistant coating and the etching of the planarization layer 56, respectively, at selected locations such as 22A. This is followed by removal of the metal layer as shown in FIG. 5C.

It is appreciated that in accordance with an alternative embodiment of the invention, the apertures 22, such as at locations A and B, need not be formed or may extend only partially through the respective insulative layers. In such a case, the insulative layers 40 or 50 may be eliminated and the laser-absorbing layer is coated directly over layer 21. In this case the laser energies applied should be adjusted to take into account the differences in thickness of the insulative layers. It is further noted that the elimination of apertures 22 may alternatively exist only over metal II and not over metal I.

It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined only by the claims which follow:

Claims

We claim:

1. A semiconductor device comprising: a first patterned metal layer; an insulation layer formed over the first metal layer; and a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions; said insulation layer being formed with apertures overlying at least some of the selectively removable regions, and there being formed over the selectably removable regions an ablative triple layer coating comprising a layer of silicon oxide over which is formed a layer of silicon nitride and over which is formed a layer of amorphous silicon.

2. Apparatus according to claim 1 and wherein the silicon oxide layer has a thickness of between 1000 and 3000 angstrom.

3. Apparatus according to claim 1 and wherein the amorphous silicon layer contains up to 30% atomic weight of at least one of Hydrogen, Carbon, Nitrogen and Oxygen.

4. Apparatus according to claim 1 and wherein the silicon oxide layer contains up to 10% atomic weight of at least one of arsenic, phosphorous and boron.

5. A semiconductor device comprising: a first patterned metal layer; an insulated layer formed over the first metal layer; and a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions, said insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions an ablative multi-layer coating comprising first and second dielectric layers having different etchability and thereover a layer of amorphous silicon.

6. Apparatus according to claim 5 and wherein at least one of said dielectric layers comprises silicon nitride.

7. Apparatus according to claim 5 and wherein the amorphous silicon layer contains up to 30% atomic weight of at least one of Hydrogen, Carbon, Nitrogen and Oxygen.

8. Apparatus according to claim 5 and wherein said apertures overlie removable regions on both said first and second metal layers.

9. Apparatus according to claim 5 and wherein said first dielectric layer comprises a planarization layer.

10. Apparatus according to claim 9 and wherein said planarization layer comprises a polymeric substance.

11. Apparatus according to claim 9 and wherein said planarization layer comprises a spin-on glass layer.

12. A semiconductor device comprising: a first patterned metal layer; an insulation layer formed over the first metal layer; a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions, said insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions an ablative multi-layer dielectric coating comprising a dielectric layer and thereover a layer of laser energy absorbing material comprising amorphous silicon.

13. Apparatus according to claim 12 and wherein the amorphous silicon layer contains up to 30% atomic weight of at least one of Hydrogen, Carbon, Nitrogen and Oxygen.

14. A semiconductor device comprising: a first patterned metal layer; an insulation layer formed over the first metal layer; and a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions, and there being formed over the selectably removable regions an ablative multi-layer coating comprising a dielectric layer and thereover a layer of amorphous silicon.

15. Apparatus according to claim 14 and wherein said dielectric layer comprises silicon oxide, silicon nitride, or polyimide.

16. Apparatus according to claim 14 and wherein the amorphous silicon layer contains up to 30% atomic weight of at least one of Hydrogen, Carbon, Nitrogen and Oxygen.

17. Apparatus according to claim 16 and wherein said dielectric layer contains up to 10% atomic weight of at least one of arsenic, phosphorous and boron.

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Abstract

Description