Harmonic Feedback Control for an Inverter

The present invention relates generally to inverters for inverting direct current (DC) power to alternating current (AC) power and, more particularly, to such inverters which are controlled so as to reduce harmonic content in the AC output of the inverters.

An inverter is employed to invert direct current power into alternating current power. In one form of such an inverter, a plurality of inverter switches are connected to a DC link and are controlled by pulse-width modulated (PWM) pulses. The inverter switches produce output PWM pulses which are supplied to a filter. The filter reduces or removes harmonics of an inverter fundamental frequency so that an AC output approximating an AC sinusoidal waveform is produced.

A common prior art PWM inverter control includes a comparator which compares a triangular waveform to a reference sinusoidal waveform. The reference sinusoidal waveform has the desired shape of the AC output from the inverter. The output of the comparator comprises a PWM waveform having a substantial frequency component at the desired inverter fundamental frequency.

Filters, particularly those which are arranged to filter out the lower frequency harmonics such as the fifth and seventh harmonics, are expensive, heavy and large. Many inverter systems control the inverter switches so as to reduce or eliminate a preselected number of the lower frequency harmonics in the inverter AC output. Thus, the filter is instead arranged to filter out higher frequency harmonics so that the expense, weight and size of the filter are accordingly reduced.

One system for supplying PWM pulses to the switches of an inverter is shown in U.S. Pat. No. 4,527,226 to Glennon In this system, a memory stores a plurality of PWM pulse patterns (or "angle sets") each having a unique set of switching angles. The switching angles of the stored angle sets are predetermined analytically so that selected harmonics in the inverter output can be minimized. A set of switching angles is selected from the memory based in part upon the power factor at the inverter output. This selected set of switching angles is supplied to the inverter switches so that the harmonic content in the output of the inverter is reduced.

Inverter systems utilizing stored patterns have limited harmonic reduction capability because only a limited number of angle sets are available for use. In such systems, if a power factor is sensed for which there is no stored angle set, the stored angle set associated with the power factor closest to the sensed power factor is selected. However, use of this angle set does not result in minimum harmonic content. Also, many prior art inverter systems assume that the DC voltage on the DC link is stiff, i.e., has no ripple. However, an inverter is bidirectional in the sense that any harmonic ripple in the output of the inverter passes back through the inverter to the DC link. This ripple on the DC link modulates the output of the inverter to produce further harmonic content in the inverter output. Inverter systems utilizing stored angled sets are typically not arranged to compensate for this additional harmonic content. Furthermore, many stored angle set systems do not directly measure harmonic content in the inverter output, but develop an approximation thereof, and hence cannot completely eliminate controlled harmonics.

A system in which the DC link is not assumed to be stiff and which senses the harmonic content in the output of an inverter is disclosed in Kirchberg, et al., U.S. Pat. No. 4,994,956. In this system, parameters of the inverter output are used to select an initial angle set from a memory storing a plurality of such angle sets. The Fourier coefficients of selected harmonics in the inverter output are determined and these Fourier coefficients are used to adjust the switching angles of the selected angle set in order to reduce the harmonic content in the inverter output regardless of whether this harmonic content arises from the PWM switching of the inverter switches or from harmonics passed back through the inverter to the DC link. This system has the further advantage in that harmonic reduction is not limited by the number of stored angle sets.

The present invention provides a closed loop system for the on-line, real time control of the switching angles of PWM pulses supplied to an inverter in order to reduce harmonic content in the output of the inverter.

According to one aspect of the invention, an inverter system includes an inverter for inverting DC power into AC power. Means are provided for sensing harmonics in the AC power. Means are coupled to the sensing means for generating a harmonic waveform having a harmonic component for each harmonic sensed in the AC power. Means are coupled to the generating means for controlling the inverter in accordance with the harmonic waveform such that the harmonics in the AC power are reduced.

According to another aspect of the invention, an inverter system is arranged for inverting DC power into AC power and for reducing harmonic content in the AC power. The AC power contains a fundamental frequency and the harmonic content includes harmonics of the fundamental frequency of the AC power. The inverter system includes an inverting means for inverting the DC power into the AC power. A harmonic sensing means senses components of the harmonics. A function generating means generates a sinusoidal function dependent upon the components of the harmonics. A PWM pulse generating means responds to the sinusoidal function by generating PWM pulses. The inverting means responds to the PWM pulses by inverting the DC power into AC power and by reducing harmonics in the AC power.

According to yet another aspect of the invention, a method of inverting DC power into AC power includes the steps of supplying DC power to an inverter, inverting the DC power into AC power, sensing harmonics in the AC power wherein each of the harmonics has a frequency, and comparing each of the harmonics to a reference in order to produce a plurality of errors wherein each error is dependent upon a different one of the harmonics. A plurality of multiplied functions is produced by multiplying each of the errors by a corresponding one of a plurality of a sinusoidal functions wherein each of the sinusoidal functions has the frequency of the harmonic from which its corresponding error is produced. The multiplied functions are compared to a triangular wave to produce PWM pulses and the PWM pulses are supplied to an inverter so as to invert the DC power into AC power and so as to reduce harmonics in the AC power.

These and other features and advantages will become more apparent from a detailed consideration of the invention when taken in conjunction with the drawings in which:

FIG. 1 is a block diagram of an inverter system according to the present invention;

FIG. 2 shows the inverter of FIG. 1 in greater detail;

FIGS. 3A and 3B show in greater detail one embodiment of the inverter controller of FIG. 1; and,

FIGS. 4A and 4B show in greater detail a further embodiment of the inverter controller of FIG. 1.

As shown in FIG. 1, an inverter system 10 includes a synchronous generator 12 which is driven by a prime mover (not shown), such as an aircraft jet engine, and which produces three-phase, variable-frequency AC power. This variable-frequency AC power is converted by a rectifier/filter 14 into a DC voltage on a DC link 16. The DC link 16 includes a positive DC rail 18 and a negative DC rail 20. The positive DC voltage on the positive DC rail 18 and the negative DC voltage on the negative DC rail 20 are supplied to an inverter 22.

An inverter controller 24 supplies input PWM pulses to the inverter 22. In response to these input PWM pulses, the inverter 22 inverts the DC voltage on the DC link 16 into three-phase, constant-frequency AC power on inverter output lines 26A, 26B and 26C. The inverter 22 may alternatively develop a different number of phase outputs, if desired. As noted in greater detail hereinafter, the inverter controller 24 samples the voltages on the inverter output lines 26A, 26B and 26C in order to measure the harmonics in the output of the inverter 22 and controls the inverter 22 so as to reduce those harmonics. The inverter controller 24 may instead sense the harmonics at a point of regulation (POR), if desired.

The inverter output on each of the lines 26A, 26B and 26C is in the form of output PWM pulses. The output PWM pulses on the output line 26B are shifted in phase by 120.degree. with respect to the output PWM pulses on the output line 26A, and the output PWM pulses on the output line 26C are shifted by an additional 120.degree. with respect to the output PWM pulses on the output line 26A.

The output PWM pulses from the inverter 22 are filtered by a filter 28 in order to remove preselected harmonics from the output of the inverter 22. For example, the filter 28 may include an L-C filter having a corner frequency at the sixth harmonic in order to attenuate harmonics having frequencies above the frequency of the sixth harmonic. Furthermore, the filter 28 may also include notch filters for removing selected harmonics having frequencies above the frequencies of the harmonics controlled by the controller 24. The filter 28 smooths the output PWM pulses on the lines 26A, 26B and 26C into AC waveforms approximating sinusoidal waves. Each AC waveform is separated in phase by 120.degree. from the other two AC waveforms and is supplied to one or more load(s) 30. A neutral line 31 connects the rectifier/filter 14 to the filter 28 and the load(s) 30. This neutral line 31 indicates that the rectifier portion of the rectifier/filter 14 is a half bridge rectifier and is at a potential midway between the voltages on the positive and negative rails 18 and 20.

The inverter 22 is shown in greater detail in FIG. 2. This inverter 22 includes six transistors Q1-Q6 which are connected in a conventional three-phase bridge configuration and which are operated as switches by the inverter controller 24 to invert the DC power on the DC link 16 to AC power. A plurality of flyback diodes D1-D6 are connected in antiparallel relationship across the emitter-collector circuits of the transistors Q1-Q6.

FIGS. 3A and 3B, taken together, show the inverter controller 24 in greater detail. As shown in FIG. 3A, a harmonic analyzer 38 samples the voltage on the inverter output line 26A to determine the Fourier magnitude coefficients of the controlled components (i.e., the fundamental component and selected harmonics of interest) in the inverter output. Accordingly, the harmonic analyzer 38 has a plurality of output lines 40.sub.1 -40.sub.n on which output signals are developed wherein each output signal has a magnitude substantially equal to the Fourier magnitude coefficient of a corresponding controlled harmonic. Thus, a first output signal on the output line 40.sub.1 from the harmonic analyzer 38 provides the Fourier magnitude coefficient of the first or fundamental harmonic or component in the output of the inverter 22, a second output signal on the output line 40.sub.3 provides the Fourier magnitude coefficient of the third harmonic of the inverter fundamental frequency in the output of the inverter 22, and so on with the output 40.sub.n providing the Fourier magnitude coefficient of the nth harmonic in the output from inverter 22. The letter "n" represents the highest odd selected harmonic of interest.

The first output signal on the output line 40.sub.1 is subtracted by a summer 42.sub.1 from a first reference signal REF 1 to produce an error signal. The first reference REF 1 represents the desired magnitude of the inverter output voltage at the fundamental frequency. Also, the output signals on the output lines 40.sub.3 -40.sub.n are subtracted from corresponding reference signals REF 3-REF N by summers 42.sub.3 -42.sub.n to produce corresponding error signals. The reference signals REF 3-REF N represent the desired magnitudes of the third through the nth harmonics. Since it is desired to eliminate these harmonics, the reference signals REF 3-REF N are all equal to zero.

The error signal from the summer 42.sub.1 is integrated by an integrator 44.sub.1. Similarly, the error signals from the summers 42.sub.3 -42.sub.n are integrated by corresponding integrators 44.sub.3 -44.sub.n. If the inverter controller 24 measures harmonic content at the POR at or near the load(s) 30, instead of at the output of the inverter 22, the integrators 44.sub.1, 44.sub.3 . . . 44.sub.n. may include compensation circuitry to compensate for the response of the filter 28 to each of the controlled harmonics. Thus, the term "inverter output" as used herein in connection with the measuring or sensing of the harmonics refers to the output of the inverter 22 and/or the output of the filter 28.

A multiplier 46.sub.1 multiplies the integrated error from the integrator 44.sub.1 by a sinusoidal waveform having a frequency equal to the frequency of the inverter fundamental frequency. A sinusoidal waveform may be a sine wave or a cosine wave. Accordingly, the output of the multiplier 46.sub.1 (which may also be referred to as a multiplied waveform) is a sinusoidal waveform having a magnitude determined by the integrated error between the reference REF 1 and the Fourier magnitude coefficient of the fundamental frequency in the inverter output. Similarly, multipliers 46.sub.3 -46.sub.n. multiply the outputs of the integrators 44.sub.3 -44.sub.n. by sinusoidal waveforms having the frequency of the third through nth harmonics, respectively, of the inverter fundamental frequency. The multiplied waveforms from the multipliers 46.sub.1, 46.sub.3. . . 46.sub.n are combined by a summer 48 to form a composite harmonic waveform Y.sub.c.

As shown in FIG. 3B, the composite waveform Y.sub.c is compared by a comparator 50 to a triangular waveform. When the magnitude of the triangular waveform is greater than the magnitude of the composite waveform Y.sub.c, the output of the comparator is low; on the other hand, when the magnitude of the triangular waveform is less than the magnitude of the composite waveform Y.sub.c, the output of the comparator is high. The comparator 50 generates several PWM pulses for each fundamental cycle of the composite waveform Y.sub.c. These PWM pulses have switching angles determined by the result of comparing the composite waveform Y.sub.c to the triangular waveform. As the harmonic content in the output of the inverter changes, the composite waveform Y.sub.c changes and the switching angles of the PWM pulses consequently change. The switching angles control the Fourier magnitude coefficients of the fundamental component and the controlled harmonics at the reference levels established by REF 1-REF N.

A base drive circuit 52 receives the PWM pulses from the comparator 50 and produces PWM control signals for the upper and lower switches in each leg of the inverter 22. Thus, for example, a first PWM control signal is produced at an output 54 for the upper switch Q1 and a second PWM control signal is produced at an output 56 for the lower switch Q2. The first and second PWM control signals are arranged so that, when the PWM pulses in the first control signal on the output 54 are high, the PWM pulses in the second control signal on the output 56 are low, and vice versa. This ensures that the transistors Q1 and Q2 are not conducting at the same time; thus, a short circuit condition between the positive DC rail 18 and the negative DC rail 20 is avoided. Furthermore, as is known, the base drive circuit 52 may be arranged to ensure that the pulses on its outputs 54 and 56 satisfy the minimum on-times for the transistors Q1 and Q2.

The output from the comparator 50 is phase shifted by 120.degree. by a phase shifter 58 and is supplied to a base drive circuit 60 which is identical to the base drive circuit 52. Accordingly, the transistors Q3 and Q4 are supplied with pulses similar to the pulses received by transistors Q1 and Q2 but shifted in phase by 120.degree. .

The output from the comparator 50 is also phase shifted by 240.degree. by a phase shifter 62 and is supplied to a base drive circuit 64 which is identical to the base drive circuits 52 and 60. Accordingly, the transistors Q5 and Q6 are supplied with pulses similar to the pulses received by transistors Q1 and Q2 but shifted in phase by 240.degree..

Since the PWM pulse patterns supplied to transistors Q3/Q4 and Q5/Q6 are merely shifted in phase relative to the PWM pulse pattern supplied to transistors Q1/Q2, it can be seen that the arrangement shown in FIGS. 3A and 3B is configured on the assumption that the load 30 remains balanced so that the phase relationships between the harmonics on the three inverter output lines 26A-26C remain constant and so that each harmonic on the inverter output line 26A is separated in phase from the corresponding harmonic on the inverter output lines 26B and 26C by 120.degree. and 240.degree. respectively.

On the other hand, for unbalanced loads, the phase relationships between the harmonics on the three inverter output lines 26A-26C may vary and the harmonics on the inverter output lines 26A-26C may be separated in phase from one another by angles other than 120.degree.. In this event, three sets of the arrangement shown in FIG. 4A and 4B are utilized, one set for each phase of the inverter output. Thus, a first FIG. 4A/4B arrangement responds to the Fourier coefficients of the harmonics in phase A of the inverter outputs. Similarly, a second FIG. 4A/4B arrangement responds to the Fourier coefficients of the harmonics in phase B of the inverter outputs, and a third FIG. 4A/4B arrangement responds to the Fourier coefficients of the harmonics in phase C of the inverter outputs. Accordingly, with three sets of the arrangements shown in FIGS. 4A/4B, the inverter transistors Q1/Q2, Q3/Q4, and Q5/Q6 can be independently controlled in response to Fourier magnitude coefficients as well as Fourier phase coefficients so that selected harmonics of interest are effectively reduced even in the presence of unbalanced loads.

As shown in FIG. 4A, a harmonic analyzer 68 samples the voltage on the inverter output line 26A to determine the Fourier sine and cosine coefficients of the controlled harmonic components in the inverter output. Accordingly, the harmonic analyzer 68 has a plurality of output lines 70.sub.s1 -70.sub.sn on which output signals are developed. Each such output signal has a magnitude substantially equal to the Fourier sine coefficient of a corresponding controlled harmonic. Similarly, the harmonic analyzer 68 has a plurality of output lines 70.sub.c1 -70.sub.cn on which output signals are developed. Each such output signal has a magnitude substantially equal to the Fourier cosine coefficient of a corresponding controlled harmonic. Thus, the output line 70.sub.s1 from the harmonic analyzer 68 provides the Fourier sine coefficient of the first or fundamental harmonic or component in the Phase A output of the inverter 22, and so on with the output line 70.sub.sn providing the Fourier sine coefficient of the nth harmonic in the Phase A output from inverter 22. The output line 70.sub.c1 from the harmonic analyzer 68 provides the Fourier cosine coefficient of the first or fundamental harmonic or component in the Phase A output of the inverter 22, and so on with the output line 70.sub.cn. providing the Fourier cosine coefficient of the nth harmonic in the Phase A output from inverter 22.

The signal on the output line 70.sub.s1 is subtracted by a summer 72.sub.s1 from a reference signal REF S1 to produce an error signal. The signal on the output line 70.sub.c1 is subtracted by a summer 72.sub.c1 from a reference signal REF C1 to produce an error signal. The references REF S1 and REF C1 represent the desired magnitudes for the Fourier sine and cosine coefficients, respectively, for the inverter output voltage at the fundamental frequency. The signal on the output line 70.sub.sn is subtracted from the corresponding reference signal REF SN by a summer 42.sub.sn to produce a corresponding error signal. The signal on the output line 70.sub.cn is subtracted from the corresponding reference signal REF CN by a summer 42.sub.cn to produce a corresponding error signal. The references REF SN and REF CN represent the desired magnitudes of the Fourier sine and cosine coefficients, respectively, for the inverter output voltage at the nth harmonic. Since it is desired to eliminate harmonics of the fundamental frequency but not the fundamental frequency itself, all reference signals, other than the reference signals REF S1 and REF C1, are equal to zero.

The error signal from the summer 72.sub.s1 is integrated by an integrator 74.sub.s1 and the error signal from the summer 72.sub.c1 is integrated by an integrator 74.sub.c1. Similarly, the error signal from the summer 72.sub.sn is integrated by an integrator 74.sub.sn. and the error signal from the summer 72.sub.cn is integrated by an integrator 74.sub.cn. A multiplier 76.sub.s1 multiplies the integrated error from the integrator 74.sub.s1 by a sine wave, sin(1.omega.t), having a frequency equal to the frequency of the inverter fundamental frequency. Accordingly, the output of the multiplier 76.sub.s1 is a sine wave having a magnitude determined by the integrated error between the reference REF S1 and the Fourier sine coefficient of the phase A inverter output voltage at the fundamental frequency. A multiplier 76.sub.c1 multiplies the integrated error from the integrator 74.sub.c1 by a cosine wave, cos(1.omega.t), having a frequency equal to the frequency of the inverter fundamental frequency. Accordingly, the output of the multiplier 76.sub.c1 is a cosine wave having a magnitude determined by the integrated error between the reference REF C1 and the Fourier cosine coefficient of the phase A inverter output voltage at the fundamental frequency.

Similarly, a multiplier 76.sub.sn multiplies the integrated error from the integrator 74.sub.sn by a sine wave, sin(n.omega.t), having a frequency equal to the frequency of the nth harmonic of the inverter fundamental frequency. Accordingly, the output of the multiplier 76.sub.sn by a sine wave, having a magnitude determined by the integrated error between the reference REF SN and the Fourier sine coefficient of the nth harmonic of the inverter fundamental frequency. A multiplier 76.sub.cn multiplies the integrated error from the integrator 74.sub.cn by a cosine wave, cos(n.omega.t), having a frequency equal to the frequency of the nth harmonic of the inverter fundamental frequency. Accordingly, the output of the multiplier 76.sub.cn is a cosine wave having a magnitude determined by the integrated error between the reference REF CN and the Fourier cosine coefficient of the nth harmonic of the inverter fundamental frequency. The multiplied waveforms from the multipliers 76.sub.s1, 76.sub.c1 . . . 76.sub.sn, 76.sub.cn are combined by a summer 78 to form a composite harmonic waveform Y.sub.CA.

As shown in FIG. 4B, the composite waveform Y.sub.CA is compared by a comparator 80 to a triangular waveform. When the magnitude of the triangular waveform is greater than the magnitude of the composite waveform Y.sub.CA, the output of the comparator is low; on the other hand, when the magnitude of the triangular waveform is less than the magnitude of the composite waveform Y.sub.CA, the output of the comparator is high. The comparator 80 generates several PWM pulses for each fundamental cycle of the composite waveform Y.sub.CA. These PWM pulses have switching angles determined by the result of comparing the composite waveform Y.sub.CA to the triangular waveform. As the harmonic content in the output of the inverter changes, the composite waveform Y.sub.CA changes and the switching angles of the PWM pulses consequently change. The switching angles control the Fourier sine and cosine coefficients of the fundamental component and the controlled harmonics at the reference levels established by REF S1, REF C1 . . . REF SN, REF CN.

A base drive circuit 82, similar to base drive circuit 52, receives the PWM pulses from the comparator 80 and produces PWM control signals for the upper and lower switches Q1 and Q2 in the inverter 22. The transistor pairs Q3/Q4 and Q5/Q6 are controlled by corresponding sets of the arrangement shown in FIGS. 4A/4B. However, in the case of the transistor pair Q3/Q4, the associated harmonic analyzer measures the Fourier coefficients in the phase B inverter output voltage, and, in the case of the transistor pair Q5/Q6, the associated harmonic analyzer measures the Fourier coefficients in the phase C inverter output voltage.

While the inverter controller 24 has been shown in the drawings as discrete circuit elements, it should be apparent that all or some of the functions performed by the circuit elements of FIGS. 3A and 3B and by the circuit elements of FIGS. 4A and 4B could be performed in a computer.

Many other modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.