US 5,319,649 AGrant
Transmission Systems and Decoders Therefor
Issue Date:1994-06-07
•26 Claims
•12 Drawing Sheets
Abstract
Digital data is processed by quantizing the data to produce samples, each with a most significant bits and least significant bits with the least significant bits representing reliabilities, generating a parities from the most significant bits of the samples, generating weight functions corresponding to the parities on the basis of the number of times a reliability measure occurs, and producing a corrected stream of data with the weight functions and the corresponding parities.
Metadata
Assignee
- Comstream Corporation
Inventors
- Sreenivasa A. Raghavan
- Yoav Hebron
Application Information
Application Number:US 8148899
Filing Date:1991-12-27
Priority Date:1991-12-27
Art Unit:233
Classifications
IPC:
G06F 1110H03M 1300H03M 1312
Field of Search:
37137.1;37.8;49.2;43
Patent Drawings (12 sheets)
Description
Background of the Invention
This invention relates to communication and other data transfer systems and to decoders therefor, and particularly to systems and decoders using soft decisions for decoding convolutional and block codes.
Communication and other data transfer systems employ error correction decoders to enhance the accuracy of the received information. In such systems the use of soft decision decoding of convolutional and block codes improves the error correction capability of a particular code. One technique of soft decision decoding is the optimum symbol-by-symbol decoding method disclosed in the article of C. R. P. Hartman, and L. D. Rudolph, entitled "An Optimum Symbol-by-Symbol Decoding Rule for Linear Codes," in the IEEE Transactions on Information Theory, IT-22, 514-517, September 1976. Another technique is a priori probabilistic (APP) decoding disclosed in the book "Threshold Decoding", by J. L. Massey, MIT Press 1963, Cambridge, Massachusetts.
The optimum symbol-by-symbol decoding technique uses soft decisions for decoding any block code whereas the APP decoding approach is suitable for threshold decodable codes, which may be block codes or convolutional codes. Threshold decodable codes are very helpful because of the simplicity of their implementations. However, the exact weight function needed to benefit from soft decisions in either the optimum symbol-by-symbol decoding operation or the exact APP decoding method is highly non-linear and very complex to implement when the block length or the constraint length is large. Hence it is practical to apply a simple approximation of the weight function that can give a good coding gain.
Previously known simple approximations of the weight function for soft decision decoding appear in the article of H. Tanaka, K. Furusawa, and S. Kaneku entitled "A Novel Approach to Soft Decision Decoding of Threshold Decodable Codes", IT-26, 244-246, March 1980. However, these fail to obtain the possible coding gain when the block code is long, i.e. has large block length, or if the constraint length of the convolutional code is long.
Objects and Summary of the Invention
An object of this invention is to improve communication systems and error correction decoders.
Another object is to furnish such systems and error correction decoders with a simple, easily implemented weight function.
According to a feature of the invention, such objects are attained by generating a number of parity checks from the most significant bits of quantized data samples of signals that have passed through a transmission channel of a communication system, and generating weight functions corresponding to the parity checks on the basis of the number of times a reliability measure occurs. This results in an improved soft decision decoder.
Another aspect of the invention involves decoding the output of a soft decision decoder that uses weight functions based on the number of times a reliability measure occurs.
These and other features of the invention are pointed out in the claims. Other objects and advantages of the invention will become evident from the following detailed description when read in light of the accompanying drawings.
Brief Description of the Drawings
FIG. a block diagram of a system embodying features of the invention.
FIG. 2 is a block diagram of a decoder in FIG. 1 and also embodying features of the invention
FIG. 3 is a block diagram of a parity generator in FIG. 2.
FIG. 4 is a block diagram of a weight function generator in FIG. 2.
FIGS. 5 and 6 are logic and block diagrams showing details of portions of FIG. 2.
FIGS. 7A to 7C are block and circuit diagrams showing details of portions of FIG. 2.
FIG. 8 is a partial block and logic diagram showing a communication system embodying features of the invention and including a weight function circuit according to the invention.
FIG. 9 is a block diagram illustrating details of a transmitter shown in FIG. 1.
FIG. 10 is a block diagram showing an output circuit forming part of a receiver in FIG. 1.
FIG. 11 is a block diagram of a transmission system depicting a combination of circuitry in FIGS. 1, 2, and 3.
FIG. 12 is a block diagram of another system embodying the features of FIG. 1.
FIG. 13 is a diagram illustrating the arrangement in FIG. 1 that generates the parities in FIG. 1.
FIGS. 14 and 15 are other embodiments of portions of the circuit in FIG. 2.
FIG. 16 is yet another embodiment of portions of the circuit in FIG. 2.
FIGS. 17, 18, 19, and 20 illustrate still other embodiments of the invention.
Detailed Description of Preferred Embodiments
In the communication system of FIG. 1, a transmitter TR.sub.1 transmits digital data through a communication channel CC.sub.1 to a receiver RE.sub.1. The receiver RE.sub.1 includes a demodulator DM.sub.1, a storage buffer SB.sub.1, a decoder DE.sub.1, and an output circuit OC.sub.1.
In FIG. 1, the demodulator DE.sub.1 extracts samples from the data and quantizes each extracted sample to Q bits, for example 3 bits. The most significant bits (MSB) in a sample from the demodulator DE.sub.1 represent the hard decision and the least significant bits (LSB) represent the magnitude, or the reliability, of the sample. In a general case of Q bits, the first bit is used as the most significant bit and the last Q-1 bits the reliabilities. The storage buffer SB.sub.1 stores the MSB's and LSB's of successive blocks of samples for application by block to the decoder DE.sub.1.
Components of the decoder DE.sub.1, appear in FIG. 2. Here a parity generator PG.sub.1 receives the MSB's of samples in a block of data and generates J+1 parities B.sub.o to B.sub.J. A weight function generator WG.sub.1 receives the LSB's of the samples in a block of data and generates J+1 weight functions W.sub.o to W.sub.J. A mapping circuit MC.sub.1, weights and maps the parities B.sub.o to B.sub.J with the weight functions W.sub.o to W.sub.J to produce weighted parities (2B.sub.0 -1)W.sub.0 to (2B.sub.J -1)W.sub.J which enter the inputs of a full adder FA.sub.1. The latter forms a decision variable F. A comparator CO.sub.1 compares the value F with 0 to produce a value C.sub.m to establish a value 1 or 0. The value 1 or 0 passes to the output circuit OC.sub.1 either directly or through a second buffer.
The generators PG.sub.1 and WG.sub.1 repeat the process with the mapping circuit MC.sub.1, the full adder FA.sub.1, and the comparator CO.sub.1, for all the samples. The resulting bits also pass to the output circuit OC.sub.1 either directly or through the second buffer. When the bits representing all the samples have been shifted, the buffer SB.sub.1 applies the MSB's and LSB's of samples in a new block to the respective generators PG.sub.1 and WG.sub.1.
Details of the parity generator PG.sub.1 appear in FIG. 3. Here, to generate J parities, a select switch SE.sub.1 composed of two or more gates (not shown) selects n MSB's of a block of n samples stored in the buffer SB.sub.1 and feeds them into an n stage shift register SR.sub.1 with stages S.sub.0 to S.sub.(n-1). Thereafter, the select switch SE.sub.1 selects, i.e. connects to, a feedback path. In the first decoding cycle, after feeding of the MSB's in samples to the shift register SR.sub.1, a reordering circuit OC.sub.1 connects the stages S.sub.0 to S.sub.(n-2) to J sets of multiple input exclusive OR circuits XO.sub.1 to XO.sub.J. The latter forms J parities B.sub.1 to B.sub.J. The stage S.sub.(n-1) forms parity B.sub.0. Hence the system produces (J+1) parities B.sub.0 to B.sub.J from the n MSB's.
Reordering circuits of S.sub.j, where j=1 to n, are known and have connections based on known codes. Further details of circuits such as SE.sub.1, SR.sub.1, RC.sub.1, XO.sub.1 to XO.sub.J appear in more detail in FIG. 13. The operation of such circuits is described in the book "Error Control Coding; Fundamentals and Applications", by Lin and Costello, page 208. The description is rendered in terms applicable to block code. This is only illustrative and the invention is usable with other codes, such as threshold decodable convolution codes.
FIG. 4 illustrates the weight function generator WG.sub.1. Here, at the same time that the selector switch SE.sub.1 supplies the n MSB's to the shift register SR.sub.1 from the demodulator DE.sub.1, a selector switch SE.sub.2 furnishes the corresponding Q-1 LSB's from each of the n samples to a shift register SR.sub.2 whose length is (Q-1)*n bits. Thus the shift register SR.sub.2 receive n*(Q-1) LSB's from the block of samples.
A reorder circuit RC.sub.2 reorders the first (Q-1) * (n-1) outputs at the stages S.sub.0 to S.sub.[(n-1)(Q-1)-1] of the shift register SR.sub.2 into J sets SE.sub.1 to SE.sub.J of m*(Q-1) outputs each. The number m is a parameter of the known code (see Lin and Costello supra) and is the number of components in the parity equation for which the weight function is being determined. Each of the sets is divided into Q-1 groups of m binary elements. The m signals (Q-1) groups of J sets enter the inputs of J weight function circuits WF.sub.1 to WF.sub.J. The latter produce J weight functions W.sub.1 to W.sub.J each corresponding to the analogous one of the J parities B.sub.1 to B.sub.J.
The last Q-1 stages, stages S.sub.[(n-2)(Q-1)] to S.sub.(n-1)(Q-1)-1], of the shift register supply a weight function circuit WF.sub.0. The latter produces a weight W.sub.0 corresponding to the parity B.sub.0.
The parities B.sub.0 to B.sub.J of FIGS. 2 and 3 have levels of either 0 or 1. The mapping circuit MC.sub.1 maps the parities B.sub.0 to B.sub.J as shown in FIGS. 7A, 7B, and 7C. Each of the weights W.sub.i is inverted if B.sub.i equals 0 and is not inverted if B.sub.i =1 (i=0 to J). This produces weighted parities (2B.sub.0 -1) W.sub.0, (2B.sub.1 -1) W.sub.1, . . . (2B.sub.J -1) W.sub.J.
The full adder FA.sub.1 of FIG. 2 sums the weighted parities (2B.sub.0 -1) W.sub.0, (2B.sub.1 -1) W.sub.1, . . . (2B.sub.J -1) W.sub.J to obtain a decision variable F. The comparator C0.sub.1 compares the value of F with 0 to produce a value C.sub.m representing the decode orthogonal bit. If the value F>0, then C.sub.m is 1, if F<0, then C.sub.m is 0.
Upon completion of the operation by the comparator C0.sub.1, the sampled data is shifted cyclically one bit to the right.
The above circuitry of FIGS. 1 to 4 repeats the aforementioned process to decode a different bit of the code word. The new bit formed is now the orthogonal code bit. The system repeats the process n times to decode the entire code word. After decoding the entire code word, the select switches SE.sub.1 and SE.sub.2 enter a new code word into the shift register SR.sub.1 and SR.sub.2. Suitable memories in the demodulator and the output circuit store the samples and orthogonal bits as needed.
The circuit of FIGS. 1 to 4 improves the operation of the communication system and the efficiency of the decoding by virtue of the operation of the weight function circuits WF.sub.0 to WF.sub.J. The latter determine not only the least reliable component of the weights W.sub.0 to W.sub.J, i.e. the minimum of the n outputs, but also the number of occurrences of the minimum value.
FIGS. 5 and 6 exhibit details of the weight function circuit WF.sub.J, which is identical to and representative of the circuits WF.sub.0 to WF.sub.J. As noted from FIG. 4, each weight function circuit WF.sub.1 to WF.sub.J receives (Q-1)*m samples from the reorder circuit RC.sub.2. As shown in FIG. 5, Q is assumed to be 3, and the inputs to the weight function circuit WF.sub.J are regrouped from m groups of Q-1 inputs as shown in FIG. 4, to Q-1 groups of m inputs each. The first group of m inputs carries the name a.sub.1, and the second group of m inputs bears the designation a.sub.2. This arises because if we assume Q=3, each of the n received samples is represented by a 3 bit number a.sub.0, 1, and a.sub.2 one of which, a.sub.0, is the hard decision in the sample. Accordingly, the remaining two bits a.sub.1 and a.sub.2 in the sample represent the reliabilities or soft decision. Thus, the output of the reorder circuit OC.sub.1 to the weight function WF.sub.J is in the form of m samples a.sub.1 and a.sub.2. The magnitude of each of the m samples is a.sub.1 a.sub.2 for that sample. These are regrouped in the form of m inputs a.sub.1, a.sub.2.
The values of the m components a.sub.1 constitute the input of an AND gate AD.sub.1 as well the inputs of respective exclusive OR gates XR.sub.1, XR.sub.2, . . . XR.sub.m. The output M.sub.1 of the AND gate AD.sub.1 is 0 if any one of the four inputs a.sub.1 to the AND gate AD.sub.1 is 0. If all of the inputs to the AND gate AD.sub.1 are 1, M.sub.1 equals 1.
The value 0 or 1 of M.sub.1 at the output of the AND gate AD.sub.1 forms the input of m exclusive OR gates XR.sub.1, XR.sub.2, . . . XR.sub.m. When M.sub.1 is 1, the output of the exclusive OR gates are all zeros because all the values a.sub.1 are also 1. When M.sub.1 is zero, then the output of each corresponding exclusive OR gate XR.sub.1, XR.sub.2, . . . XR.sub.m is the value a.sub.1 of the corresponding sample.
The outputs A.sub.1, A.sub.2, . . . A.sub.m of the exclusive OR gates XR.sub.1, XR.sub.2, . . . XR.sub.m appear at the inputs of OR gates OR.sub.1, OR.sub.2, . . . OR.sub.m. The other inputs to the latter OR gates are the m values a.sub.2. Hence, when M.sub.1 is 1, the output of the exclusive OR gates XR.sub.1 to XR.sub.m are all zeros and hence the outputs of the OR gates OR.sub.1, OR.sub.2, . . . OR.sub.m represent the m values a.sub.2.
When M.sub.1 is 0, the inputs to the OR gates OR.sub.1, OR.sub.2, . . . OR.sub.m from the exclusive OR gates XR.sub.1 to XR.sub.m correspond to the m values of a.sub.1. The other inputs to the OR gates OR.sub.1, OR.sub.2, . . . OR.sub.1 represent the m values of a.sub.2. Then each output of the OR gates OR.sub.1 to OR.sub.m is a 1 unless a corresponding pair of a.sub.1 and a.sub.2 is 0.
The OR gates OR.sub.1, OR.sub.2, . . . OR.sub.m pass the signals applied thereto to an AND gate AD.sub.2 having an output M.sub.2. If M.sub.1 is 1 because all m a.sub.1 values are 1 and hence all exclusive OR gates XR.sub.1 to XR.sub.m are 0, the AND gate AD.sub.2 goes to 1 only if all values a.sub.2 are 1 and goes to 0 if any one of the values a.sub.2 is 0.
On the other hand if M.sub.1 is 0 because at least one value a.sub.1 is 0, and hence the outputs of the exclusive OR gates XR.sub.1 to XR.sub.m correspond to the m values a.sub.1, then the AND gate AD.sub.2 produces a 1 unless a corresponding pair of values a.sub.1 and a.sub.2 is 0.
In effect, if M.sub.1 is 1, the circuitry ANDs, the components a.sub.2 to obtain M.sub.2. If M.sub.1 is zero, then the circuit logically ANDs only the values a.sub.2 whose components a.sub.1 in the sample are 0.
As shown in FIG. 6, the output M.sub.2 passes to the inputs of m exclusive OR gates Xr.sub.1, Xr.sub.2, . . . Xr.sub.m which also receive the m respective values a.sub.2. These gates indicate at their respective outputs X.sub.1, X.sub.2, . . . X.sub.m whether the value M.sub.2 corresponds to the values of a.sub.2. A similar determination occurred at the outputs A.sub.1 to A.sub.m which denoted whether M.sub.1 corresponds to the values a.sub.1. The plurality m NOR gates Nr.sub.1, Nr.sub.2, . . . Nr.sub.m receive respective values A.sub.1 to A.sub.m and values X.sub.1 to X.sub.m to determine whether they differ or not, and hence whether M.sub.1 M.sub.2 equals a.sub.1 a.sub.2 or not. An adder DD.sub.1 adds the outputs U.sub.1 to U.sub.m of gates Nr.sub.1 to Nr.sub.m to obtain the number N of times the minimum occurs.
A read only memory (ROM) RM.sub.1 receives the output M.sub.1 at the output of the AND gate AD.sub.1, the value M.sub.2 at the AND gate AD.sub.2, and the number N from the adder DD.sub.1 to produce the weight W.sub.J. The ROM RM.sub.1 establishes the minimum .vertline.y.sub.min .vertline. which represents the digital value of the values M.sub.1 and M.sub.2. It then produces an output W.sub.J based on the following look-up table. This look-up table is, for an example, for the (21, 11) threshold decodable block code, J=5, m=4.
FIGS. 7A to 7C illustrate a mapping circuit embodying the invention. FIG. 7B shows details of FIG. 7A, and the latter is a shorthand version of FIG. 7B. Here multiplexers MUX.sub.i, where i=0 . . . J, receive the value W.sub.i directly and W.sub.i through inverters IN.sub.i. The multiplexers MUX.sub.i choose one of inputs W or W depending on whether B is 0 or 1. FIG. 7C illustrates a circuit equivalent of the diagrams in FIG. 7A and 7B. Here the switches B.sub.i switch between W.sub.i and W.sub.i.
According to other embodiments of the invention, n can be other lengths such as 273 or 1057 or any shortened version of such codes.
As stated, the weighted parities (2B.sub.O -1)W.sub.O to (2B.sub.J -1)W.sub.J enter the inputs of a full adder FA.sub.1. The latter forms a decision variable F. As shown in FIG. 2, the comparator CO.sub.1 compares the value F with 0 to produce a value C.sub.m to establish a value 1 or 0. The value 1 or 0 passes to the output circuit OC.sub.1 either directly or through a second buffer.
The select switch SE.sub.1 then circulates the last bit on the right of the register SR.sub.1 to the first position and shifts the content of the register one bit to the right. The select switch SE.sub.2 then circulates the last Q-1 bits of the SR.sub.2 to the entry positions and shifts the content of the register Q-1 bits to the right. This starts the next cycle. The process now repeats until the formation of a new bit C.sub.m.
When all the cycles have been completed, i.e. the bits representing all the samples have been shifted, the storage buffer SB.sub.1 replaces the MSB's and LSB's of the samples in the shift registers SR.sub.1 and SR.sub.2 with the MSB's and LSB's in a new block. The cycles are then repeated for the new block.
FIG. 8 illustrates a more specific embodiment of the invention wherein Q=3, m=4, and J=5. The circuit elements and operation are otherwise the same as the circuits in FIGS. 1 to 6.
FIG. 9 illustrates the transmitter TR.sub.1 of FIGS. 1 and 7. Here, an analog video generator AV.sub.1 generates analog video signals which enter an analog to digital (A/D) converter ADC. The latter converts the video signals and passes them to a compressor CP.sub.1 which compresses the signals. An encryptor EN.sub.1 encrypts the compressed signals and passes the signals to a forward error correction (FEC) encoder FE.sub.1. A modulator MD.sub.1 then modulates the resulting data stream and sends it to the communication channel.
FIG. 10 shows the output circuit OC.sub.1 which, together with the demodulator DM.sub.1 and the decoder DE.sub.1, forms the receiver of the communication system in FIGS. 1 to 9. The output circuit OC.sub.1 includes a decryptor DY.sub.1 that decrypts the error corrected received data, a decompressor DP.sub.1 for decompressing the decrypted signals, a digital to analog (D/A) converter DAC for reconverting the signal to the analog state, and a display system DS.sub.1 that includes audio and video outputs. The complete system is shown in FIG. 11. Here, like reference characters denote like parts of those in FIGS. 1 to 10, and the like parts perform the same functions.
According to an embodiment of the invention, the systems of FIGS. 9 to 11 do not include the encryptor EN.sub.1, the compressor CP.sub.1, the decrypter DY.sub.1, and the decompressor DP.sub.1. FIG. 12 discloses this arrangement.
FIG. 13 depicts details of an example of a circuit for generating the parities B.sub.0 to B.sub.J in FIGS. 2, 3, and 8. Here n=21, a number permitting simple diagramming of the connections. The selector SE.sub.1 enters the MSB's of the quantized samples into the shift register SR.sub.1 with a gate GA.sub.1 while a gate GA.sub.2 holds feedback from the stage S.sub.20. When gate GA.sub.2 conducts gate GA.sub.1 is non-conductive. As mentioned the shift register SR.sub.1 has twenty one stages S.sub.0 to S.sub.20. Terminals r.sub.0 to r.sub.19 of the reorder circuit RC.sub.1 have subscripts identifying the corresponding stages S.sub.0 to S.sub.19 to which the reorder circuit connects them. Only some of the connections are portrayed while others are omitted for clarity. The reorder circuit RC.sub.1 collects the connections into five groups of four lines each to exclusive OR (XOR) circuits XO.sub.1 to XO.sub.J on the basis of a known predetermined code. The circuits XO.sub.1 to XO.sub.J XOR the values to produce parities B.sub.1 to B.sub.J. The stage S.sub.20 itself forms the parity B.sub.0.
The selector SE.sub.2, shift register SR.sub.2, and the reorder circuit RC.sub.2 in FIG. 4 operate in similar manner on the basis of a known code. The final two stages of the shift register SR.sub.2 form the input to the weight function circuit WF.sub.0.
In operation, the demodulator DM.sub.1 receives signal distorted by the channel CH.sub.1 from the transmitter TR.sub.1 and quantizes samples of the signals into Q=3 bits which it applies stores in the storage buffer SB.sub.1. The latter applies them to the decoder DE.sub.1. The MSB becomes the hard decision on the sample and the Q-1=LSB's represent the magnitude of the sample. Hence, if Q=3, there are two possibilities for the hard decision or parity of each sample and the 2.sup.Q-1 =m=2.sup.2 =4 possibilities for the magnitude or reliability of each quantized sample. The circuits SE.sub.1, SR.sub.1, RC.sub.1, and XO.sub.1 to XO.sub.J form the parities B.sub.0 to B.sub.J on the basis of the exclusive OR gates XO.sub.1 to XO.sub.J. On the other hand, the circuits SE.sub.2, SR.sub.2, RC.sub.2, and WF.sub.1 to WF.sub.J implement weight functions W.sub.0 to W.sub.J for the parities B.sub.0 to B.sub.J. Only the magnitudes of the m components of the LSB's determine the weight function. The weight function circuits establish the minimum in each sample of the m magnitudes and the number of times N the minimum appears. The result appears at the read only memory RM.sub.1 whose output is the weight function represented by K bits. The possible values for the weight function are preset according to the aforementioned table. In this regard, the determinations are based on equations (3) or (4) to follow.
The determination of the minimum value of m positive numbers and the number of occurrences of the minimum value is done in the weight function circuit WF.sub.J as shown in FIGS. 5 and 6. In this case Q=3. The quantized received samples are represented by the 3-bit number a.sub.0 a.sub.1 a.sub.2 and the hard decision on the sample is a.sub.0. Hence a.sub.1 a.sub.2 represent the magnitude of the sample. The minimum of the magnitudes of m samples is M.sub.1 M.sub.2. The a.sub.1 's of the numbers are logically ANDed to obtain the M.sub.1 of the minimum value. M.sub.2 of the minimum value is established as follows.
If M.sub.1 is 1, logically AND the a.sub.2 's to obtain M.sub.0. On the other hand, if M.sub.1 is 0, then logically AND on the a.sub.2 's of those components whose a.sub.1 are 0. When M.sub.1 is 1, then A.sub.1 to A.sub.m (the output of the gates XR.sub.1 to XR.sub.m ) are all 0's (since all the a.sub.1 's are 1) and hence the output of the OR gate following the A.sub.1 to A.sub.m is the corresponding a.sub.2. These are logically ANDed to get M.sub.2. Hence the corresponding A.sub.2 passes through to the final AND gate only if an a.sub.1 is an 0. Otherwise, a 1 is passed to the final AND gate AD.sub.2. To count the number of elements that are equal to the minimum, it is noted that any A.sub.1 to A.sub.m serves as a flag to indicate if a.sub.1 is equal to the corresponding M.sub.1 or not. That is, if A.sub.1 to A.sub.m are all 0, then the i-th a.sub.1 is equal to M.sub.1. The XOR gates Xr.sub.1 to Xr.sub.m create a similar flag X.sub.1 to X.sub.m to indicate if a.sub.2 is equal to M.sub.2 or not. NOR gates Nr.sub.1 to Nr.sub.m execute logical NOR operations on X.sub.1 to X.sub.m and A.sub.1 to A.sub.m to obtain U.sub.1 to U.sub.m which indicates if M.sub.1 M.sub.0 is equal to a.sub.1 a.sub.2 or not. The values U.sub.1 to U.sub.m are added to the number of minima N.
Another embodiment of the invention appears in FIGS. 14 and 15 for obtaining weight functions in soft decision decoding of a rate k/n threshold decodable convolutional code.
In FIGS. 14 and 15, the quantizing and storage CS.sub.1 performs the functions of demodulator DE.sub.1 and buffer SB.sub.1, while a register RE.sub.1 corresponds to the parity generator PG.sub.1. The unit UN.sub.1 supplies the generator GW.sub.1 corresponding to WG.sub.1. In FIG. 15, a set of full adders AF and comparators OC form output bits i.sub.k.
The Invention is based upon the following general considerations. It should be noted that the symbols in the following may not conform to those previously used.
Denote a parity (or syndrome), determined from the binary hard decisions of the components of an error correction code by
where the symbol .sym. represents binary XOR operation. Further, denote by p.sub.i the probability that the hard decision r.sub.i is in error, given that the corresponding quantized (to Q bit representation) analog sample is y.sub.i. Since one of the Q bits is used to represent the hard decision r.sub.i, the remaining (Q-1) bits are used to represent the absolute value of the sample y.sub.i. The possible values .vertline.y.sub.i .vertline. are denoted 0, 1, . . . , (2.sup.Q-1 -1), where the notation .vertline.x.vertline. denotes the absolute value of the real number x . Denote by W the soft decision weight function of B involved in the soft decision decoding of the error correction code.
The previously known simplified weight function uses only the "least reliable" component (in other words, the component with the smallest magnitude) of B. See the aforementioned article by Tanaka et al. Though this method of determining W gives good coding gain for codes with small m, it fails to give good coding gain when m is large.
The invention uses not only the least reliable component of B, but also the number of times it occurs in the parity B in determining the corresponding weight W. This can be written as:
where
.vertline.y.sub.min .vertline.=minimum of {.vertline.y.sub.s .vertline.; 0<s<(m+1)}
N is the number of elements y.sub.t such that
The function F(.vertline.y.sub.min .vertline., N) can be chosen to be one of several functions. Some possible choices are: ##EQU1## where the function
is given by
and K is a positive constant.
The expression p(.vertline.y.sub.min .vertline.) represents the probability of an error given that the (Q-1) bit representation of the magnitude of the received sample is .vertline.y.sub.min .vertline.. This appears in the book Threshold Decoding, by J. L. Massey, published by MIT Press, Cambridge, Massachusetts, 1963. ##EQU2## when 0<.vertline.y.sub.min .vertline.<2.sup.(Q-1) -2, and ##EQU3## when .vertline.y.sub.min .vertline.=2.sup.(Q-1) -1.
The function .phi.(x) is given by ##EQU4## In (4), E.sub.s is the channel symbol energy in BPSK transmission, N.sub.0 is the power spectral density of the additive white Gaussian noise, and .DELTA. is the step size of the uniform quantizer and is chosen without loss of generality to be ##EQU5## where R is the chosen range of the absolute value of the received samples.
The general considerations behind the read-only-memory (ROM) are as follows. Assuming that the demodulator output is quantized to 3 bits for the purpose of soft decision decoding, the reliability of any sample is represented by either 0, 1, 2, or 3. Further assuming that the parameter .DELTA., as defined in equation (7), is equal to 0.3(E.sub.s).sup.(1/2) then equation (4) gives ##EQU6##
Assuming that
then p(0)=0.2398, p(1)=0.0296, p(2)=0.003, and p(3)=0.00013. Now the weight W is determined by using Equation (3a). For the values of the minimum reliabilities and the values N in Table 1, the first computed values are, from top to bottom in Table 1, 0.0638, 0.1232, 0.2412, 0.5011, 0.9156, 1.0396, 1.215, 1.516, 1.9195, 2.0445, 2.2205, 2.5216, 3.2195. The value of K is then chosen to normalize the values that W can take. In Table 1, the value K is chosen equal to the inverse of the minimum value 0.0638, which allows the other values to come close to some positive integers to facilitate the easy implementation of the ROM. Since the largest value of the normalized weight is 50, only 6 bits are needed to represent normalized W. Hence the size of the ROM is 13*6=78 memory locations.
According to another embodiment, a further simplification occurs when the blocklength of a block code is large, or when the constraint length of the convolutional code is large and when the signal-to-noise ratio is low to moderate. A weight function circuit embodying this principle appears in FIG. 16. In such a case, instead of determining the .vertline.y.sub.min .vertline. from m elements each having a (Q-1) bit representation, it is assumed that .vertline.y.sub.min .vertline. is 0 and only the number of components in the parity equation (1) with magnitude 0 are counted. This simplifies the decoder a great deal. Thus when quantizing the samples to be used in soft decision decoder, it is sufficient to store the hard decision and if the magnitude of the sample is 0 or not.
The circuit of FIG. 16 replaces those of FIGS. 5 and 6 and receives the same inputs. Here, however the m* (Q-1) inputs are not regrouped from the m groups of Q-1 inputs to the weight function circuits of FIG. 4. Rather the inputs remain grouped in as m groups of (Q-1) inputs a.sub.1 a.sub.2. NOR gates NR.sub.1, NR.sub.2 . . . NR.sub.m each receive inputs a.sub.1 and a.sub.2 and apply them to adder DD.sub.1. The latter is the same as that of FIG. 6. The ROM RM.sub.1 operates on the same basis with 0 inputs for M.sub.1 and M.sub.2.
The extra coding gain that can be obtained by using this weight function is substantial when the block code has large block length, or, when the convolutional code has large constraint length (and/or high rate). It is easy to implement and does not have the complexity of the exact weight function.
In other embodiments of the invention, the soft decision decoder output is either fed back to itself, i.e. the decoder input, or fed forward to a separate decoder. The output of the soft decision decoder can be either hard decisions or soft decisions.
FIG. 17 shows hard decision output of the soft decision decoder being fed forward to a hard decision decoder. In FIG. 17, the decoder DE.sub.2 replaces the soft decision decoder DE.sub.1 in the circuits of FIGS. 1, 8, 11, and 12. The decoder DE.sub.2 includes the decoder DE.sub.1, a buffer BU.sub.2 to store the output of the decoder DE.sub.1, and a hard decision decoder HD.sub.1. The hard decision decoder HD.sub.1 takes the output of the soft decision decoder DE.sub.1 stored in the buffer BU.sub.2 and subjects it to hard decision decoding to form the output of the decoder DE.sub.2.
FIG. 18 corresponds to FIG. 17 but substitutes a decoder DE.sub.3 in which the hard decision decoder HD.sub.1 is replaced with a soft decision decoder SD.sub.1, for example a decoder corresponding to DE.sub.1.
FIG. 19 shows a decoder DE.sub.4 which is another form of the decoder DE.sub.2 in FIG. 17. The decoder DE.sub.4 is identical to the decoder DE.sub.1 except for omission of the connection between the last stage of shift register SR.sub.1 to the select circuit SE.sub.1 of FIGS. 3 and 8. Instead the output of the soft decision decoder DE.sub.1 is fed back to the input of the same soft decision decoder at the shift register SR.sub.1 for the hard decisions. Here the decoded output C.sub.m from the comparator CO.sub.1 of FIGS. 2 and 8 passes not only to the output circuit OC.sub.1, but also feeds back to the select circuit SE.sub.1 at the input of the hard decision shift register SR.sub.1 of FIGS. 3 and 8. This feedback replaces the feedback in FIGS. 3 and 8 from the last stage of the shift register SR.sub.1 to the select circuit SE.sub.1. This arrangement improves the resulting decoding. The circuit CT.sub.1 includes the elements RC.sub.1, RC.sub.2, WF.sub.i, XO.sub.i, B.sub.i (i=0 . . . J), MC.sub.1, FA.sub.1,etc. in FIGS. 2 to 4 and 8.
FIG. 20 shows a decoder DE.sub.5 which is another form of the decoder DE.sub.3 in FIG. 18. The decoder DE.sub.5 is identical to the decoder DE.sub.4 except for the omission of the connection from the last stage of the register SR.sub.2 to the select circuit SE.sub.2. Instead in FIG. 20, an absolute value generator AG.sub.1 produces the absolute value of the output F from the full adder FA.sub.1 in FIGS. 2 and 8. A scaling circuit SC.sub.1 divides the absolute value by J+1 and feeds the divided value to the select circuit SE.sub.2 at the input to the soft decision shift register SR.sub.2 in FIGS. 4 and 8. This feedback replaces the feedback in FIGS. 4 and 8 from the last stage of the shift register SR.sub.2 to the select circuit SE.sub.2. This arrangement further improves the resulting decoding.
While embodiments of the invention have been described in detail, it will be evident to those skilled in the art that the invention may be embodied otherwise.
Claims
What is claimed is:
1. An apparatus for processing a stream of data, comprising: first generating means for generating a set of hard decisions and a set of soft decisions from the stream of data; means for forming a plurality of first subsets from the set of hard decisions parity generating means for generating a set of parities from a plurality of first subsets of said set of hard decisions; means for forming a plurality of second subsets from the set of soft decisions; weight function generating means for generating a plurality of weight functions from said plurality of second subsets of the set of soft decisions based on how many times a given one of said soft decisions occurs in each second subset, and correcting means for producing a corrected data stream with said weight functions and said parities.
2. An apparatus as in claim 1, wherein: said first generating means includes means for quantizing said stream of data into multiplicities of bits each multiplicity having a most significant bit and bits of lesser significance; said first generating means includes means for generating each of said hard decision from the most significant bit; and said first generating means includes means for generating said soft decisions form the lesser significant bits.
3. An apparatus as in claim 1, wherein: said parity generating means includes means for logically combining the hard decisions of said first subsets; and said correcting means for producing a corrected data stream includes means for weighting the parities with the weight functions, means for adding the weighted parities, means for comparing the added weighted parities to a threshold for producing said corrected set of bits.
4. An apparatus as in claim 3, wherein: said first generating means includes means for forming the set of hard decisions and the set of soft decisions, and means for cyclically shifting the set of hard decisions and the set of soft decisions to create new sets of hard decisions and soft decisions.
5. An apparatus as in claim 3, wherein: said first generating means includes means for generating a hard decision and a soft decision from the same data element in a stream of data producing a set of soft decisions that correspond to the set of hard decisions; said parity generating means and said weight function generating means form a corresponding plurality of first functions form the subsets of hard decisions and a plurality of second function from the subsets of soft decisions.
6. An apparatus as in claim 1, wherein: said soft decisions represent reliabilities and are defined by two bits with values 00, 01, 10 and 11, wherein a reliability increases as the value of the bits increases.
7. An apparatus as in claim 6, wherein: said soft decision is 00 in each of said second subsets.
8. An apparatus as in claim 1, wherein: said soft decisions in each second subset include a given minimum value soft decision, ad the given soft decision is the minimum value soft decision in each second subset.
9. An apparatus as in claim 8, wherein each soft decision has two bits, one of said bits being a more significant bit and the other bit being a lesser significant bit said weight function generating means for establishing a given minimum value soft decision from each second subset and how often the given minimum value soft decision occurs in each second subset includes: means for logically ANDing a set of more significant bits of two bits representing the soft decisions of a second subset to obtain a first result; logic means responding to the first result being 1 for logically ANDing the lesser significant of the two bits representing the set of soft decisions of the second subset to obtain a second result; said logic means responding to the first result being zero for logically ANDing the lesser significant of the two bits representing the soft decisions of the second subset whose more significant bit is a 0; means for determining whether each of the more significant of the two bits representing the soft decisions of the second subset is equal to the first result and for determining whether each of the lesser significant of the two bits representing the soft decisions of the second subset is equal to the second result; and means for logically NORing the determining of said determining means to obtain a plurality of indicators; and means connected to the means for logically NORing for adding the indicators.
10. An apparatus as in claim 1, wherein: a predetermined look-up table receives said soft decisions and how many times the given one of the soft decisions occurs in each of said second subsets to obtain a weight function.
11. An apparatus as in claim 1, further comprising: decoding means coupled to said correcting means for further decoding said corrected data stream to produce a further corrected data stream.
12. An apparatus as in claim 1, further comprising: feedback means for feeding the corrected data stream of said correcting means to said parity generating means for further decoding the corrected data stream.
13. The method of processing a stream of data, comprising: generating a set of hard decisions and a set of soft decisions form the stream of data forming a plurality of first subsets from said set of hard decisions; generating a set of parities from each of first subsets of said set of hard decisions; forming a plurality of second subsets from said set of soft decisions; generating a plurality of weight functions from said plurality of second subsets of the set of soft decisions, said generating of each weight function includes determining how many times a given one of the soft decisions occurs in each second subset; and producing a corrected data stream with said weight functions and said parities.
14. The method as in claim 13, wherein: said steps of generating said sets of hard decisions includes quantizing said stream of data into a plurality of bits each plurality having a most significant bit and bits of lesser significance; and each of said hard decisions is generated from the most significant bit; and said soft decisions are generated from the bits of lesser significance.
15. The method as in claim 13, wherein: said step of generating a set of parities includes logically combining the hard decisions of said first subsets; and said step of producing a corrected data stream includes weighting the parities with the weight functions, adding the weighted parities, comparing the added weighted parities to a threshold to obtain results, the results of said comparisons being the said corrected set of bits.
16. The method as in claim 15, wherein: said step of generating a set of hard decisions and a set of soft decisions includes the substeps of: forming a set of the hard decisions and a set of the soft decisions, cyclically shifting the set of hard decisions and cyclically shifting the set of soft decisions to form new sets of hard decisions and set of soft decisions.
17. The method as in claim 15, further comprising: further decoding said corrected data stream to produce further corrected data streams.
18. The method as in claim 15, wherein: said generating step for generating a set of hard decisions and a set of soft decisions includes generating a hard decision and a corresponding soft decision form the same data element in a stream of data and producing a set of soft decisions that correspond to the set of hard decisions; said parity generating step and said weight function generating step form a corresponding plurality of first functions form the subsets of hard decisions and a plurality of second functions from the subsets of soft decisions.
19. The method as in claim 13, wherein: the soft decisions have values represented by 2 bits having magnitudes, namely 00, 01, 10, and 11, wherein a value increases as the magnitude of the bits increases.
20. The method as in claim 19, wherein: said soft decisions having minimum values, said step of generating weight functions includes establishing minimum soft decisions having minimum values; said given soft decision is the minimum soft decision in each second subset.
21. The method as in claim 20, wherein each soft decision measure has two bits, one of said bits being a more significant bit and the other bit being a lesser significant bit the step of a minimum soft decision from each second subset and the number of times the minimum soft decision occurs in each second subset includes: logically ANDing the set of more significant of the two bits representing the reliabilities of the members of a second subset to obtain a first result; if the first result is 1, logically ANDing the lesser significant of the two bits representing the soft decisions of a second subset to obtain a second result; if the first result is zero, logically ANDing the lesser significant of the two bits representing the soft decisions of the second subset whose more significant bit is a 0; determining whether each of the more significant of the two bits representing the soft decisions of the second subset is equal to the first result; determining whether each of the lesser significant of the two bits representing the soft decisions of the second subset is equal to the second result; and logically NORing the determining of said determining steps to obtain a plurality of indicators, and adding the logically NORed indicators.
22. The method as in claim 20, wherein: said minimum soft decision and how many times the minimum soft decisions occurs in each said second subset is in put to a pre-determined look-up table to obtain a weight function.
23. The method as in claim 13, wherein: said given soft decisions is set at 00 in each of said second subsets.
24. A data transfer system, comprising: a source of a stream of data; receiver for receiving the stream of data, including a demodulator, an error corrector, and an output; said demodulator including generating means for generating a set of hard decisions and a set of soft decisions from the stream of data; said error correcting means including means for forming a plurality of first subsets from the set of hard decisions; said error corrector including parity generating means for generating a set of parities from a plurality of first subsets of said set of hard decisions; said error corrector including means for forming a plurality of second subsets form the set of soft decisions; said error corrector including weight function generating means for generating a plurality of weight functions from said plurality of second subsets of the set of soft decisions based on how many times a given one of said soft decisions occurs in each second subset, and said output including correcting means for producing a corrected data stream with said weight functions and said parities.
25. A system as in claim 24, further comprising: decoding means coupled to said correcting means for further decoding said corrected data stream to produce a further corrected data stream.
26. A system as in claim 24, further comprising: feedback means for feeding the corrected data stream of said correcting means to said parity generating means for further decoding the corrected data stream of said correcting means.