US 5,319,264 AGrant
Logarithmic Amplifying Circuit
Issue Date:1994-06-07
•5 Claims
•5 Drawing Sheets
Abstract
In a logarithmic amplifier circuit including a plurality of cascaded differential amplifiers, a plurality of blocks of logarithmic full-wave rectifiers are provided, each producing output currents having logarithmic full-wave rectification characteristics in respect to voltages of their input signals. Each logarithmic full-wave rectifier is formed by a plurality of squaring full-wave rectifiers each producing an intermediate current having squaring full-wave characteristics. A current adder is provided for each or a group of the squaring full-wave rectifiers to add up the intermediate currents thereof and produce an output current. A common adder is provided for adding the output currents from all logarithmic full-wave rectifiers to produce a current output signal.
Metadata
Assignee
- Nec Corporation
Inventor
- Katsuji Kimura
Application Information
Application Number:US 0977314
Filing Date:1993-07-27
Priority Date:1990-10-30
Art Unit:254
Classifications
IPC:
G06F 7556G06F 724
Field of Search:
307328330492;494;495;497145;26;32253
Patent Drawings (5 sheets)
Description
Background of the Invention
1. Field Of The Invention
The present invention relates to a logarithmic amplifying circuit and, more particularly, to a logarithmic amplifying circuit suited for a MOS integrated circuit.
2. Description Of The Related Arts
A conventional logarithmic amplifying circuit of the type is generally realized in a bipolar integrated circuit. A logarithmic amplifying circuit realized in a MOS integrated circuit is disclosed in, e.g., Japanese Patent Laid-Open No. 62-292010.
The logarithmic amplifying circuit in this MOS integrated circuit is designed in such a manner that multistage MOS differential amplifiers are connected in cascade, and squaring full-wave rectifiers are respectively connected to an input of the first stage and output terminals of the subsequent stages. With this arrangement, signals at these input and output terminals are subjected to squaring full-wave rectification, and the outputs from the squaring full-wave rectifiers are added together. For this reason, these outputs are affected by the characteristics of the respective squaring full-wave rectifiers, which include dynamic range characteristics, and hence excellent logarithmic characteristics cannot be obtained.
Summary of the Invention
It is an object of the present invention to provide a logarithmic amplifying circuit which has a wide dynamic range and can obtain excellent logarithmic characteristics.
In order to achieve the above object, according to the present invention, there is provided a logarithmic amplifying circuit comprising a plurality of stages of cascaded differential amplifiers for respectively performing differential amplification of signals from preceding stages and transferring the amplified signals to subsequent stages, a plurality of logarithmic full-wave rectifiers including a plurality of squaring full-wave rectifiers for respectively outputting currents having squaring full-wave rectification characteristics with respect to an input voltage, and adding means for adding the output currents from the squaring full-wave rectifiers and outputting the resultant values, the logarithmic full-wave rectifiers being connected to an input terminal of a first-stage differential amplifier an to output terminals of the respective stages so as to receive voltages at the input terminal of the first stage and at the output terminals of the respective stages and respectively output currents having logarithmic full-wave rectification characteristics with respect to the input voltages, and an adder for adding the output currents from the logarithmic full-wave rectifiers and outputting a signal corresponding to the sum of current.
In addition, the squaring full-wave rectifier comprises a first transistor having a gate connected to a first input terminal of a pair of first and second input terminals for receiving an input voltage, and a source connected to a first current source circuit, a ratio of a gate width to a gate length of the first transistor being set to be a predetermined value, a second transistor having a gate and source respectively connected to the second input terminal and the first current source circuit, a ratio of a gate width to a gate length of the second transistor being set to be different from that of the first transistor, and the second transistor constituting a first differential pair together with the first transistor, a third transistor having a gate and a source respectively connected to the second input terminal and a second current source circuit, a ratio of gate width to gate length of the third transistor being set to be a predetermined value, a fourth transistor having a gate and a source respectively connected to the first input terminal and the second current source circuit, a ratio of gate width to gate length of the fourth transistor being set such that the gate-width/gate-length ratios of the third and fourth transistors are equal to those of the first and second transistors, and the fourth transistor constituting a second differential pair together with the third transistor, a first current mirror circuit having a current input terminal connected to drains of the first and third transistors, and a current output terminal connected to drains of the second and fourth transistors, and a second current mirror circuit having a current input terminal connected to the drains of the second and fourth transistors and to the current output terminal of the first current mirror circuit. Furthermore, the adding means of the logarithmic full-wave rectifiers is constituted by a set of first and second current mirror circuits commonly used for the respective squaring full-wave rectifiers in place of the first and second current mirror circuits of each squaring full-wave rectifier.
Brief Description of the Drawings
FIG. 1 is a block diagram showing a logarithmic amplifying circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram showing a logarithmic full-wave rectifier in the logarithmic amplifying circuit of the present invention;
FIG. 3 is a circuit diagram showing a squaring full-wave rectifier, as a basic unit, constituting the logarithmic full-wave rectifier shown in FIG. 2; and
FIGS. 4 and 5 are graphs showing the characteristics of a squaring full-wave rectifier, in which ratio W.sub.1 (gate width)/L.sub.1 (gate length) is used as a parameter.
Detailed Description of Preferred Embodiment
The present invention will be described below with reference to accompanying drawings.
FIG. 1 is a block diagram showing a logarithmic amplifying circuit according to an embodiment of the present invention.
The logarithmic amplifying circuit comprises a plurality of (m) stages of cascaded differential amplifiers 11, 12, . . . , and 1m, a plurality of logarithmic full-wave rectifiers 21, 22, . . . , and 2(m+1) respectively connected to the input and output terminals of the first-stage differential amplifier 11 and the output terminals of the differential amplifiers 12 to 1m of the subsequent stages and designed to respectively output currents I.sub.RSJ (J=1 to m+1) having logarithmic full-wave characteristics with respect to an input voltage V.sub.1, and an adder 3 for adding the output currents I.sub.RSJ from the logarithmic full-wave amplifiers 21, 22, . . . , and 2(m+1) and outputting a signal V.sub.0 corresponding to the sum current.
Since the logarithmic full-wave rectifiers 21, 22, . . . , and 2(m+1) of the logarithmic amplifying circuit are all the same in circuitry arrangement, only the logarithmic full-wave rectifier 21 is shown in FIG. 2.
Referring to FIG. 2, the logarithmic full-wave rectifier 21 comprises n squaring full-wave rectifiers (21-1), (21-2), . . . , and (21-n), and a pair of current mirror circuits 40A and 40B constituting an addition means for adding output currents from these squaring full-wave rectifiers. Each squaring full-wave rectifier is constituted by a set of two differential pairs. For example, in the squaring full-wave rectifier (21-1), a set of two differential pairs is constituted by differential pairs 30A.sub.1 and 30B.sub.1. In the squaring full-wave rectifier (21-2), a set of two differential pairs is constituted by differential pairs 30A.sub.2 and 30B.sub.2.
Since the squaring full-wave rectifiers are all the same in circuitry arrangement, only one of them is shown in FIG. 3, and its circuit arrangement and operation will be described below.
Referring to FIG. 3, each squaring full-wave rectifier comprises a set of two differential pairs 30A and 30B, and a pair of current mirror circuits 40A and 40B serving as an addition means. The differential pair 30A is constituted by first and second transistors M1 and M2. The gate of the first transistor M1 is connected to a first input terminal T.sub.1, one of a pair of first and second input terminals T.sub.1 and T.sub.2 for receiving an input voltage V.sub.1. The source of the transistor M1 is connected to a first current source I.sub.01. The ratio of the gate width to the gate length of the transistor M1 is set to be a predetermined value. The gate and source of the second transistor M2 are respectively connected to the input terminal T.sub.2 and the first current source I.sub.01. The ratio of the gate width to the gate length of the second transistor M2 is set to be different from that of the first transistor M1. The other differential pair 30B is constituted by third and fourth transistors M3 and M4. The gate and source of the third transistors M3 are respectively connected to the second input terminal T.sub.2 and a second current source I.sub.02. The ratio of the gate width to the gate length of the third transistor M3 is set to be a predetermined value. The gate and source of the fourth transistor M4 are respectively connected to the first input terminal T.sub.1 and the second current source I.sub. 02. The ration (W/L) of the gate width to the gate length of the fourth transistor M4 is set such that the ratios (W/L) of the gate-width/gate-length of the third and fourth transistors M3 and M4 are equal to those of the first and second transistors M1 and M2.
The first current mirror circuits 40A comprises transistors M5 and M6. The current input terminals of the current mirror circuit 40A is connected to the drains of the first and third transistors M1 and M3, whereas the current output terminal is connected to the drains of the second and fourth transistors M2 and M4. The second current mirror circuit 40B comprises transistors M7 and M8. The current input terminal of the current mirror circuit 40B is connected to the drains of the second and fourth transistors M2 and M4 and to the current output terminal of the first current mirror circuit 40A.
The squaring full-wave rectifier shown in FIG. 3 requires the pair of current mirror circuits 40A and 40B. However, in the squaring full-wave rectifier shown in FIG. 2 which is constituted by a plurality of differential pairs, the pair of current mirror circuits 40A and 40B is commonly used for all the differential pairs (21-1), (21-2), . . . , and (21-n).
An operation of this embodiment and the characteristics of the respective components will be described below.
The squaring full-wave rectifier will be described first.
Drain currents I.sub.d1, I.sub.d2, I.sub.d3, and I.sub.d4 of the transistors M1, M2, M3, and M4 are obtained as follows. If ratios W/L of gate widths W to gate lengths L of the respective transistors are represented by W.sub.1 /L.sub.1, W.sub.2 /L.sub.2, W.sub.3 /L.sub.3, and W.sub.4 /L.sub.4, then
In this case if ##EQU1## where u.sub.N is the mobility of the transistor, and C.sub.ox is the gate capacitance of the gate oxide film per unit area, then
for
where V.sub.t is the threshold voltage of the transistor.
The transistors M5, M6, M7, and M8 constitute the first and second current mirror circuits 40A and 40B, and an output current I.sub.RS from this squaring full-wave rectifier is given by ##EQU2##
FIG. 4 shows this output current I.sub.RS with K and W.sub.1 /L.sub.1 used as parameters. FIG. 5 shows the output current I.sub.RS as a function of V(dB).
The current I.sub.RSO in equation (9) in the absence of a signal is given by ##EQU3## The current I.sub.RSO monotonously increases with respect to K.
According to equation (9), if I.sub.RS =0, an operating maximum input voltage V.sub.I0 is given by ##EQU4## Even if the value K changes, the range of change is sufficiently compressed. Therefore, the voltage V.sub.I0 is substantially constant, if K has a large value.
Similarly, an input voltage V.sub.I0.5 for I.sub.RS =I.sub.RSO /2 is given by ##EQU5## Therefore, the input voltage V.sub.I0.5 remains substantially constant with respect to a change in K.
The inclination of the current I.sub.RS is obtained by differentiating equation (9) as follows: ##EQU6##
For example, when I.sub.RS becomes I.sub.RSO, the corresponding inclination is represented by ##EQU7##
That is, the current I.sub.RS monotonously decreases with respect to K.
The characteristics of the logarithmic full-wave rectifier 2J (J=1 to m+1) will be described below.
The operating dynamic range of the Xth (X=1 to n) squaring full-wave rectifier constituting the logarithmic full-wave rectifier is represented as the following equations by superposing the product by P.sub.X on I.sub.RSX, provided that the range of charge in output current I.sub.RSX is set to be (1-2P.sub.X) times the current I.sub.RSXO (0<P.sub.X <0.5):
In this case, V.sub.IX (P.sub.X) and V.sub.IX (1-P.sub.X) respectively represent input voltages at which the current I.sub.RSX is P.sub.X and (1-P.sub.X) times I.sub.RSXO (=I.sub.RSX (V.sub.IX =0)).
In this case, an operating dynamic range d of a logarithmic full-wave rectifier 2J is given by
If this value is expressed logarithmically,
According to equations (9) and (10), ##EQU8## Hence,
Therefore, the dynamic range d is obtained by ##EQU9##
For example, if
then, ##EQU10##
According to equations (15) to (17), ##EQU11##
The magnitude of a logarithmic characteristic error of the logarithmic full-wave rectifier 2J is determined by P.sub.X. In order to reduce the error, the value P.sub.X needs to be increased.
If, for example,
then,
If this value is expressed in terms of dB,
As a result, an operating dynamic range of 9.54 dB is obtained per squaring full-wave rectifier.
In addition, if
then,
If this value is expressed in terms of dB,
As a result, an operating dynamic range of 6.02 dB is obtained per squaring full-wave rectifier. If the value P.sub.X is increased, the operating dynamic range is reduced. However, since the operating dynamic range is increased n times at the output terminal of the logarithmic full-wave rectifier 2J, an operating dynamic range much wider than that of the conventional circuit can be obtained.
Since output currents I.sub.RSJ from the logarithmic full-wave rectifiers 2J having such characteristics are added together by the adder 3, and the sum current is converted into an output voltage V.sub.0, the output voltage V.sub.0 has a dynamic range of d.sup.(m+1). With this operation, excellent logarithmic characteristics with a wide dynamic range and a small error can be obtained.
As has been described above, according to the present invention, logarithmic full-wave rectifiers are respectively connected to the input and output terminals of a plurality of stages full-wave of cascaded differential amplifiers. Each logarithmic full-wave rectifier has a plurality of squaring full-wave rectifiers which perform squaring full-wave rectification of corresponding signals at these input and output terminals. The logarithmic full-wave rectifier adds the outputs from the squaring full-wave rectifiers, and output the sum. The outputs from the respective logarithmic full-wave rectifiers are added together. With this operation, excellent logarithmic characteristics with a wide dynamic range and a small error can be obtained.
Claims
What is claimed is:
1. An amplifier comprising: a plurality of amplifier stages each having first and second input nodes and first and second output nodes, said amplifier stages being connected to each other in cascaded arrangement such that said first and second output nodes of a preceding amplifier stage are connected respectively to said first and second input nodes of a succeeding amplifier stage, an input signal being supplied between said first and second input nodes of a first stage of said cascaded arrangement; a plurality of rectifier blocks, each rectifier block having first and second input terminals connected respectively to said first and second output nodes of an associated one of said amplifier stages to receive an output signal appearing between said first and second output nodes of the associated amplifier stage and rectifying said output signal to produce an output current representative of rectification of said output signal at first and second output terminals thereof, respectively, each rectifier block including: a first MOS transistor having a gate connected to said first input terminal, a drain connected to said first output terminal, and a source, said first MOS transistor having a first ratio of a gate width to a gate length, a second MOS transistor having a gate connected to said second input terminal, a drain connected to said second output terminal, and a source, said second MOS transistor having a second ratio of a gate width to a gate length, a third MOS transistor having a gate connected to said second input terminal, a drain connected to said first output terminal, and a source, said third MOS transistor having a third ratio of a gate width to a gate length, a fourth MOS transistor having a gate connected to said first input terminal, a drain connected to said second output terminal, and a source, said fourth MOS transistor having a fourth ratio of a gate width to a gate length, a first current source connected in common to the sources of said first and second MOS transistors, a second current source connected in common to the sources of said third and fourth MOS transistors, said first ratio being different from said second ratio, and said third ratio being different from said fourth ratio, a first current mirror circuit having a first input node connected to said first output terminal and a first output node connected to said second output terminal, a second current mirror circuit having a second input node connected said second output terminal and a second output node, and a current output terminal connected to the second output node of said second current mirror circuit to produce an output signal; and an adder coupled to said current output terminal of each of said rectifier blocks to add output signals from said rectifier blocks to each other and produce an added output signal of the amplifier.
2. The amplifier as claimed in claim 1, wherein a ratio of said first ratio to said second ratio is equal to a ratio of said third ratio to said fourth ratio.
3. An amplifier comprising a plurality of amplifier stages each having first and second input nodes and first and second output nodes, said amplifier stages being connected to each other in cascaded arrangement such that said first and second output nodes of a preceding amplifier stage are connected respectively to said first and second input nodes of a succeeding amplifier stage, and input signal being supplied between said first and second input nodes of a first stage of said cascaded arrangement; a plurality of rectifier blocks, each rectifier block having first and second input terminals connected respectively to said first and second output nodes of an associated one of said amplifier stages to receive an output signal appearing between said first and second output nodes of the associated amplifier stage and rectifying said output signal to produce an output current at first and second output terminals thereof, respectively, each rectifier block including first and second MOS transistors connected in a differential manner, said first MOS transistor having a gate connected to said first input terminal, a drain connected to said first output terminal and a first input terminal and a first ratio of a gate width to a gate length, said second MOS transistor having a gate connected to said second input terminal, a drain connected to said second output terminal and a second ratio of a gate width to a gate length, said first ratio being different from said second ratio, third and fourth MOS transistors connected in a differential manner, said third MOS transistor having a gate connected to said second input terminal, a drain connected to said first output terminal and a third ratio of a gate width to a gate length, said fourth MOS transistor having a gate connected to said first input terminal, a drain connected to said second output terminal and a fourth ratio of a gate width to a gate length, said third ratio being different from said fourth ratio, fifth and sixth MOS transistors connected in a differential manner, said fifth MOS transistor having a gate connected to said first input terminal, a drain connected to said first output terminal and a fifth ratio of a gate width to a gate length, said sixth MOS transistor having a gate connected to said second input terminal, a drain connected to said second output terminal and a sixth ratio of a gate width to a gate length, said fifth ratio being different from said sixth ratio, seventh and eighth MOS transistors connected in a differential manner, said seventh MOS transistor having a gate connected to said second input terminal, a drain connected to said first output terminal and a seventh ratio of a gate width to a gate length, said eighth MOS transistor having a gate connected to said first input terminal, a drain connected to said second output terminal and an eighth ratio of a gate width to a gate length, said seventh ratio being different from said eighth ratio, and an output circuit connected to said first and second output terminals to produce an output signal; and an adder connected to said output circuit of each of said rectifier blocks to add output signals from said rectifier blocks to each other and produce an added output signal of the amplifier.
4. The amplifier as claimed in claim 3, wherein a ninth ratio of said first ratio to said second ratio is equal to a tenth ratio of said third ratio to said fourth ratio and an eleventh ratio of said fifth ratio to said sixth ratio is equal to a twelfth ratio of said seventh ratio to said eighth ratio, said ninth ratio being different from said eleventh ratio.
5. The amplifier as claimed in claim 4, wherein said output circuit comprises a first current mirror circuit having a first input node connected to said first output terminal and a first output node connected to said second output terminal, and a second current mirror circuit having a second input node connected to said second output terminal and a second output node from which said output signal is derived.