Bus Arbitration Scheme

1. Field of the Invention

Computer systems contain bus structures in which several different devices compete for the mastership of the bus. Such devices would include signal processors, mass memories and input/output controllers. An arbitration scheme is generally incorporated into the design of the bus to decide which device can access the bus at any particular time. Depending on the arbitration strategy adopted, a considerable number of requests for the use of the bus may be delayed because other devices continually have prior mastership of the bus. This is not always acceptable and this invention relates to ways of avoiding such a situation occurring.

2. Prior Art

Several different arbitration schemes are used in a miniprocessor or microprocessor environment. They are mostly based on priorities and differ in the way in which these priorities are assigned and utilized.

The most basic arbitration scheme is the so-called FIFO (First-In-First-Out) Arbitrator similar to that described in "FIFO Arbitrator", IBM Technical Disclosure Bulletin, vol 31(2), July 1988, pp 47-51. In this scheme requests to access a memory port interface through a bus are treated strictly in the order in which they arrive. This scheme has the disadvantage in that no account is taken of the relative importance of each of the access requests. Thus any device urgently requiring access to the memory may have to wait whilst other lower-priority devices complete their operations.

A commonly used prior art method for bus arbitration which overcomes the above disadvantage involves the use of a central arbiter to communicate with all the devices desiring to use the bus. The central arbiter determines which device has the highest bus use priority taking into account how important the device is and how long the device has been requesting the use of the bus. It then sends out a signal permitting the device to use the bus. This whole processing system will fail should the central arbiter cease to function.

A third prior art system has been referred to as `daisy chaining` and is disclosed in more detail in European Patent Application EP-A-0 130 470 (IBM). In this method a signal indicating that the bus is available for use is transmitted from device to device in priority order. Any device therefore requiring access captures the signal and as a result may use the bus. This system fails to overcome the problem that low priority devices may have to wait an exorbitant length of time until they are granted access to the bus.

"Two-level internal bus arbitration for the system IO bus", IBM Technical Disclosure Bulletin, vol 32 (5A), October 1989, pp 225-228, teaches a fourth prior art system in which a fixed priority scheme is used to determine the arbitration. All requests received whilst a bus is mastered by another device are latched by common logic and will be processed in priority order when the bus next becomes free. Again this prior art fails to solve the problem that may occur when one low priority device is unable to access the bus since other higher-priority devices are granted continually mastership of the bus.

A rotating priority scheme such as that described in "Priority Controller for bus arbiter" IBM Technical Disclosure Bulletin, vol 30 (8), January 1988, pp 367-369 (a fifth prior art system), offers bus access to each device in strict rotation. While this overcomes the problems of some bus access requests being delayed for too long, it again fails to take into account the need for some devices to access the bus prior to others.

The invention overcomes these difficulties by grouping devices of similar priority together. At each priority level, requests for bus access are treated in the order at which they are generated. This arbitration scheme allows one to take into account the different timing relationship of each request and ensure that, at least within similar priority levels, no bus access request is unduly delayed. The apparatus to operate this request uses simple logic gates and hence does not require the use of a central arbiter.

FIG. 1 shows the basic implementation of the request-time dependant arbiter.

FIG. 2 shows the grant latch of the arbiter designed to handle three priority levels.

FIG. 3 shows the block latch of the arbiter designed to handle three priority levels.

FIGS. 4 and 5 show the decoding units to determine the priority level of each request.

FIG. 1 shows the basic implementation of the arbiter. It consists of a series of block latches 10, 12, 14, 16, 18 and 20 and a series of grant latches 50, 52 and 54 both of which are formed of set/reset flip-flops. The inputs to set the grant latches 50, 52, 54 are obtained from AND gates 60, 62, 64. The inputs to set the block latches 10, 12, 14, 16, 18 and 20 are obtained from AND gates 30, 32, 34, 36, 38 and 40.

The operation of the circuit can be considered in detail if we assume that the system has three devices each wishing to access the bus. Each device 1, 2 or 3 will issue a request for access at a different time along lines 4, 6 or 8. Let us suppose that the requests occur in the following order REQUEST.sub.-- 3 on line 8 followed by REQUEST.sub.-- 1 on line 4 and then REQUEST.sub.-- 2 on line 6.

The REQUEST-.sub.-- 3 will be granted by grant latch 54. Since at the beginning of the sequence no requests for access were present, the NO.sub.-- GRANT.sub.-- ACTIVE signal from grant active AND gate 70 is high, the NO.sub.-- BLOCK.sub.-- 3.sub.-- FROM.sub.-- 1 signal issued from block latch 12 is high and the NO.sub.-- BLOCK.sub.-- 3.sub.-- FROM 2 from block latch 16 is also high. Hence AND gate 64 sets grant latch 54 to allow device 3 issuing REQUEST.sub.-- 3 to be immediately granted mastership of the bus. The AND gates 38 and 40 cause the block latches 18 and 20 to set respectively the NO.sub.-- BLOCK.sub.-- 1.sub.-- FROM.sub.-- 3 and NO.sub.-- BLOCK.sub.-- 2.sub.-- FROM.sub.-- 3 low and thus grant latches 50 and 52 will not be able to grant access to the bus.

When REQUEST.sub.-- 1 (the second in the sequence of the example) is received on line 4, device 1 is not granted access to the bus since the low signal being issued on NO.sub.-- BLOCK.sub.-- 1.sub.-- FROM.sub.-- 3 from block latch 18 means that AND gate 60 cannot set grant latch 50. However the REQUEST.sub.-- 1 signal is passed to AND gate 30 to cause a low NO.sub.-- BLOCK.sub.-- 2.sub.-- FROM.sub.-- 1 signal to be issue from block latch 10 which will block future access to the bus by device 2. The REQUEST.sub.-- 2 signal (the last in the sequence of the example) when it is received cannot block either of the other two devices' access to the bus and thus takes the lowest priority for bus access.

After REQUEST.sub.-- 3 has been granted, an inverted output from grant latch 54 resets blocking latches 18 and 20 which set NO.sub.-- BLOCK.sub.-- 1.sub.-- FROM.sub.-- 3 and NO.sub.-- BLOCK.sub.-- 2.sub.-- FROM.sub.-- 3 high again. This allows AND gate 60 to pass REQUEST.sub.-- 1 to grant latch 50 and device 1 will be granted bus access when current bus use is completed (indicated by NO.sub.-- GRANT.sub.-- ACTIVE from AND gate 70 becoming high). Note that REQUEST.sub.-- 2 is still blocked by a low NO.sub.-- BLOCK.sub.-- 2.sub.-- FROM.sub.-- 1 signal from block latch 10. Future attempts by device 3 to access the bus will be blocked until REQUEST.sub.-- 1 and REQUEST.sub.-- 2 are both granted as low NO.sub.-- BLOCK.sub.-- 3.sub.-- FROM.sub.-- 1 and NO.sub.-- BLOCK.sub.-- 3.sub.-- FROM.sub.-- 2 signals are sent from block latches 12 and 16.

The arbitration scheme can be extended to different priority levels for each request line 4, 6 or 8. If we denote the signal notation L1 to be the lowest priority and L3 to be the highest priority then the AND gate 60 will be replaced by the circuit shown in FIG. 2. The effect of this circuit is to determine the relative priority of REQUEST.sub.-- 1 compared to REQUEST.sub.-- 2 and REQUEST.sub.-- 3 and, if necessary override previous access requests. Obviously, if neither device 2 nor device 3 are requesting mastership of the bus then no question of access priority will arise. In this case REQUEST.sub.-- 1.sub.-- L1, REQUEST.sub.-- 1.sub.-- L2 or REQUEST.sub.-- 1.sub.-- L3 will be passed directly to AND gates 120, 122 or 124 respectively and then to OR gate 126. AND gate 128 will pass a signal to grant latch 50 of FIG. 1 to ensure that device 1 is granted bus access when current bus use is completed (indicated by NO.sub.-- GRANT.sub.-- ACTIVE becoming high). If on the other hand, REQUEST.sub.-- 2 and/or REQUEST.sub.-- 3 signals are pending (and hence blocking immediate access to the bus by REQUEST.sub.-- 1), then the circuit must check their relative priorities. If REQUEST.sub.-- 1 has priority L2, then in AND gates 102 and 104 and OR gates 110 and 112 a comparison is made to see whether REQUEST.sub.-- 2 and/or REQUEST.sub.-- 3 have lower priority L1. If this is the case, then REQUEST.sub.-- 1.sub.-- L2 is passed to AND gate 122 and hence to OR gate 126 to allow AND gate 128 to set grant latch 50 to grant bus mastership to device 1 when the bus becomes free. The other REQUEST signals are still held, but do not receive access to the bus at this stage. If REQUEST.sub.-- 2 or REQUEST.sub.-- 3 have the same priority as REQUEST.sub.-- 1 then the circuit does not alter the order in which bus access is granted. The rest of the circuit shown in FIG. 2 determines, if REQUEST.sub.-- 1 has the highest priority L3, whether REQUEST.sub.-- 2 and/or REQUEST.sub.-- 3 have the same or lower priority and thus prescribes in a similar manner to that already described the order of access to the bus. The operation of this part of the circuit for the case in which a REQUEST signal may have one of three priority levels has only been described for the replacement of AND gate 60. It is clear that AND gates 62 and 64 will also have to be replaced with similar circuits, the operation of which will be the same.

Extension of the arbitration scheme to different priority levels involves also the replacement of the AND gates 30, 32, 34, 36, 38 and 40 with a circuit similar to that shown in FIG. 3. The function of this circuit will be described by taking AND gate 30 as an example. If REQUEST.sub.-- 1 has the lowest priority L1 then the circuit described will block device 2 only if NO.sub.-- BLOCK.sub.-- 1.sub.-- FROM.sub.-- 2 is high. This is achieved using the AND gate 170 and OR gate 180 to set block latch 10. If, however, REQUEST.sub.-- 1 has a higher priority L2, then REQUEST.sub.-- 2 can only be blocked (or continue to be blocked) if it has a lower priority L1. This is achieved by comparing REQUEST.sub.-- 2.sub.-- L1 and REQUEST.sub.-- 1.sub.-- L2 in AND gate 172. Similarly OR gate 162 and AND gate 174 allow the circuit to check whether, if REQUEST.sub.-- 1 has priority L3, REQUEST.sub.-- 2 has a priority L2 or L1 in which case REQUEST.sub.-- 2 will continue to be blocked. If REQUEST.sub.-- 2 has the same or higher priority than REQUEST.sub.-- 1 then the block latch 10 will not block REQUEST.sub.-- 2 to prevent device 2 from gaining access to the bus before device 1.

If two requests for mastership of the bus arrive at exactly the same time (or in the same time slot), then means must be provided to resolve this problem. This is achieved using the circuit shown in FIG. 4. This circuit can be broken down into the simpler units shown in FIG. 5 by considering each of the outputs of the circuit of FIG. 4 to consist of two AND gates and an OR gate. This basic output is illustrated in FIG. 5 as two AND gates 412 (corresponding to AND gates 270, 274, 280, 284, 288, 294, 298 and 302 of FIG. 4) and 414 (corresponding to AND gates 272, 276, 282, 286, 290, 296, 300 and 304 of FIG. 4) and an OR gate 416 (corresponding to OR gates 214, 216, 222, 224, 226, 228, 230 and 232 of FIG. 4). A REQUEST is passed to both AND gates 412 and 414 along line 402. If there is no higher priority request or if the higher priority request has already been blocked, then line 404 will be high and the REQUEST will be passed by the AND gate 412 to the OR gate 416. If the block latch for this REQUEST has already been set by another REQUEST, then line 406 will be high and the request passed through AND gate 414 to OR gate 416. In all other cases, the REQUEST will remain pending on line 402 until one of the above cases has been reached and either line 404 or line 406 become high. It should be noted that some of the AND gates of FIG. 4 (i.e. 274, 284, 288, 298 and 302) corresponding to AND gate 412 of FIG. 5 have more than two inputs. In this case line 404 of FIG. 5 can be taken to represent all the input lines to the AND gates of FIG. 4 except that line coming directly from the decoders 202, 204, 206. The REQUEST signals will only be passed when all of the input lines are high. The rest of the logic shown in FIG. 4 serves to determine which block latches 10, 12, 14, 16, 18 and 20 have already been set and which higher priority requests are pending.

Although the invention has been described in terms of three requestors and three priority levels, it will be obvious to a man skilled in the art that the principle and circuitry could be extended to include further requestors as well as more priority levels.