Apparatus and Method of Canceling Periodic Carrier Phase Jitter

1. Field of the Invention

The present invention relates to a data transmission system for transmitting QAM data over an analog line such as a telephone line, and more particularly, to an apparatus method for canceling periodic carrier phase jitter over transmission lines, in a data modem receiver.

2. Description of the Related Art

Digital data transmission using data modem receivers suffers transmission error caused by carrier phase jitter that is produced over the transmission line, resulting in a reduction in the data transmission efficiency. Various efforts have been made to reduce the phase jitter within data modem receivers.

Generally, apparatus for canceling carrier phase jitter comprises a carrier reproducing circuit for absorbing the carrier phase jitter, the carrier reproducing circuit comprising a phase-locked loop in the data modem receiver. However, as the response speed of the carrier reproducing circuit is increased for greater carrier phase jitter absorption, the carrier reproducing circuit becomes more sensitive to thermal noise from a transmission line. As the known result, the apparatus for canceling carrier phase jitter are degraded in-their overall characteristics.

Another known jitter canceler is disclosed in U.S. Pat. No. 4,639,939 assigned to NEC Corporation. The disclosed jitter canceler is more capable, in principle, of separating carrier phase jitter and thermal noise. However, since the jitter canceler is basically composed of an FIR filter, the scale and complexity of the circuit arrangement tends to be increased in order to provide sufficient jitter canceling characteristics.

In view of the above drawbacks in the conventional apparatus for canceling carrier phase jitter, it is an object of the present invention to provide an apparatus and method for canceling periodic carrier phase jitter, the apparatus having of a simpler arrangement with a high response speed and capable of reliably canceling carrier phase jitter.

According to the present invention, an apparatus is provided for canceling periodic carrier phase jitter produced over a transmission line in a data modem receiver which receives QAM data from an analog line. The apparatus comprises: a sample-hold circuit for sampling and holding a received signal, an analog-digital converter for converting an analog output signal from the sample-hold circuit into a digital signal, a demodulating circuit for demodulating the digital signal from the analog-digital converter into a complex baseband signal; a phase rotating circuit for imparting phase rotation that corresponds to a separately applied predictive signal to the complex baseband signal from the demodulating circuit, thereby generating a complex baseband signal that is compensated for a phase deviation; a decision circuit for determining the data point of a two-dimensional data point matrix of modulated signals which is closest to the compensated complex baseband signal from the phase rotating circuit and for providing a phase signal point vector corresponding to the determined data point; a phase rotation angle predicting circuit for calculating a phase rotation predictive value to compensate for the phase deviation of the complex baseband signal based on the phase error between the complex baseband signal from the demodulating circuit and the phase signal point vector from the decision circuit and for outputting a predictive signal representative of the phase rotation predictive value to the phase rotating circuit; and a predictive value correcting circuit for controlling the phase rotation angle predicting circuit to correct equations for calculating the predictive signal in the next sampling cycle based on a phase error between the complex baseband signal from the phase rotating circuit and the phase signal point vector from the decision circuit.

If the complex baseband signal is deviates in phase due to phase jitter contained in the received signal, the decision circuit employs the data point in a two-dimensional data point matrix which is closest to the deviated signal. The phase rotation angle predicting circuit detects the phase error between these signals and calculates a replica of the phase jitter component, which is a periodic function. In response to the detected phase error, the phase rotating circuit corrects the next sampled signal for the phase deviation. The equations for correcting the phase deviation are corrected in each sampling cycle by the predictive value correcting circuit. The phase jitter component contained in the received signal is therefore removed reliably, and a signal free of the phase jitter component is provided as an output from the decision circuit.

According to the present invention, there is also provided a method of canceling periodic carrier phase jitter contained in a received QAM signal using the above apparatus for canceling periodic carrier phase jitter.

The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate a preferred embodiment of the present invention.

FIG. 1 is a block diagram showing an embodiment of the present invention; and

FIG. 2 is a diagram showing a two-dimensional matrix of data points in a 16-point QAM system employed in the embodiment shown in FIG. 1.

Referring now to FIG. 1, an apparatus for canceling carrier phase jitter embodying the present invention is incorporated in a 16-point QAM data modem.

The apparatus includes a sample-hold circuit 101 for sampling and holding a received signal and an A-D (analog-digital) converter 102 for converting an analog output signal from the sample-hold circuit 101 into a digital signal. A demodulator 103 demodulates a digital output signal from the A-D converter 102 into a complex baseband signal. A phase rotating circuit 104 which is responsive to a separately applied phase rotation angle signal rotates the complex baseband signal from the demodulator 103, thereby generating a complex baseband signal that is compensated for phase deviation. A decision means 105 determines the data point of a two-dimensional data point matrix of modulated signals as shown in FIG. 2 which is closest to an output signal from the phase rotating circuit 104 and outputs a phase signal point vector corresponding to the determined data point.

The apparatus also includes a phase rotation angle predicting circuit which comprises a first phase comparator 107 for calculating the phase error between the output signal from the demodulator 103 and the output signal from the decision circuit 105. The phase rotation angle predicting circuit also comprises a sine function generator 112 for generating a signal sin .theta., a cosine function generator 111 for generating a signal cos .theta., an amplifier 119 for amplifying an output signal from the first phase comparator 107, and an amplitude limiter 120 for limiting the amplitude of the output signal from the amplifier 119. The phase rotation angle predicting circuit further comprises a first multiplier 108 for multiplying the output signal from the amplitude limiter 120 by the output signal from the cosine function generator 111, a low-pass filter 109 for smoothing the output signal from the first multiplier 108, an integrator 110 for integrating the output signal from the low-pass filter 109 and applying the integrated signal as an input signal .theta. to the sine and cosine function generators 112 and 111, a first register 116 for storing a first coefficient Cr, a second register 117 for storing a second coefficient Ci, a second multiplier 115 for calculating a signal Cr.cndot.sin .theta. based on output signals from the first register 116 and the sine function generator 112, a third multiplier 113 for calculating a signal Ci.cndot.cos .theta. based on output signals from the second register 117 and the cosine function generator 111, and a subtractor 114 for calculating the difference between output signals from the second and third multipliers 115, 13. The calculated difference is applied as a signal predictive of the phase rotation angle to the phase rotating circuit 104. The first multiplier 108, the low-pass filter 109, the integrator 110, and the cosine function generator 111 jointly serve as a phase-locked loop (PLL) which is synchronized in phase with a periodic function component contained in the phase error that is produced by the first phase comparator 107.

The apparatus further includes a predictive value correcting circuit which comprises a second phase comparator 106 for calculating the phase difference between the output signal from the phase rotating circuit 104 and the output signal from the decision circuit 105, and a processor 118 for correcting the first and the second coefficients Cr and Ci according to the following recurrence formulas:

where Cra, Cia are the stored contents of the first and second registers 116, 117 in the next sampling cycle, respectively, .epsilon. is the phase error from the second phase comparator 106, and .delta. and .delta.' are predetermined constants. The stored contents of the first and second registers 116, 117 are updated by output signals from the processor 118 for each cycle.

Operation of the embodiment will be described below.

A received signal is sampled and held by the sample-hold circuit 101 and then converted by the A-D converter 102 into a digital signal, which is then demodulated into a complex baseband signal by the demodulator 103. In the present embodiment, all circuit components other than the sample-hold circuit 101 and the A-D converter 102 carry out the required calculations according to digital signal processing. The complex baseband signal from the demodulator 103 is applied through the phase rotating circuit 104 to the decision circuit 105. The decision circuit 105 determines the data point of the applied complex baseband signal in the two-dimensional matrix of data points in a 16-point QAM system, thereby obtaining the ideal signal point vector.

More specifically, as shown in FIG. 2, sixteen ideal signal points 204 are arranged in four lines and four columns at equal intervals in a two-dimensional plane. If an output signal 201 from the phase rotating circuit 104 suffers a phase deviation, then the decision circuit 105 determines the output signal 201 to be the ideal signal point 202 closest thereto, and outputs the ideal signal point vector 203 representative of the ideal signal point 202 instead of the output signal 201. The first phase comparator 107 detects a phase error E between an output signal S from the demodulator 103 and an output signal D from the decision circuit 105 according to the equation: E=Im[S.cndot.conjg(D)], where Im[S.cndot.conjg(D)] represents an operator for extracting the imaginary part of a complex number D and conjg(D) represents an operator which takes a conjugate complex number of the complex number D.

When the receiver signal suffers carrier phase jitter interference, the phase error E contains a signal representative of a phase jitter component, which is a periodic function, with noise added thereto. The phase error E is amplified by the amplifier 119 and then converted into a rectangular wave whose amplitude is .+-.1 by the amplitude limiter 120. The rectangular wave has a frequency equal to that of the phase jitter component, and the amplitude thereof is .+-.1 at all times irrespective of the phase jitter angle.

As described above, the first multiplier 108, the low-pass filter 109, the integrator 110, and the cosine function generator 111 jointly serve as a phase-locked loop which is synchronized in phase with a periodic function component contained in the phase error E that is applied. Since the rectangular-wave output signal from the amplitude limiter 120 is applied as an input signal to the PLL, the loop band remains constant irrespective of the phase jitter angle. The sine function generator 112 is synchronized with the cosine function generator 111. The first and second registers 116, 117 store the respective coefficients Cr, Ci. The multipliers 113, 115 and the subtractor 114 jointly calculate a value .phi. according to the equation:

on the output signal sin .theta. from the sine function generator 112, the output signal cos .theta. from the cosine function generator 111 and the coefficients Cr and Ci stored in the first and second registers 116, 117.

If the coefficients Cr and Ci have adequate values, the calculated value .phi. becomes a replica of the phase jitter component contained in the input signal applied to the decision circuit 105. In response to the signal representing the value .phi., the phase rotating circuit 104 cancels the phase jitter component contained in the input signal applied to the decision circuit 105.

In order to correct the coefficients Cr and Ci adaptively into adequate values in each sampling cycle, the processor 118 of the predictive value correcting circuit employs the following algorithm: The second phase comparator 106 detects a phase error .epsilon. between an output signal S' from the phase rotating circuit 104 and an output signal D from the decision circuit 105 according to the equation:

When the contents Cra and Cri of the respective first and second registers 116 and 117 are to be defined for the next sampling cycle, the processor 118 corrects the coefficients Cr and Ci according to the following recurrence formulas:

where .delta. and .delta.' are predetermined constants.

By the correction according to these recurrence formulas, the coefficients Cr and Ci converge with the optimum values which satisfy the following equations ##EQU1## The recurrence formulas show that the coefficients Cr and Ci are corrected by ##EQU2## for each sampling period, respectively. This method of converging a coefficient is commonly used in, for example, automatic equalizers using digital filters and is known as "MSE (Mean Square Error) Method".

With the arrangement of the preferred embodiment described above, the phase jitter component contained in the received signal is detected, its replica is generated, and the phase jitter component contained in the input signal applied to the decision circuit is canceled out according to the generated replica. Thus, transmission error in a data modem can be reduced for increased data transmission efficiency.

Although one preferred embodiment of the present invention has been shown and described in detail, it should be understood that various changes and modifications may be made in the embodiment without departing from the scope of the appended claims.