Sense Amplifier for Performing a High-Speed Sensing Operation

The present invention relates to a dynamic random access memory (DRAM) of a semiconductor memory device, and more particularly to a sense amplifier capable of performing a sensing operation at high speed.

As the more large-scale integration in a semiconductor memory device is recently carried out, a demand for the lower operating voltage or the fast data access speed has increased. In order to meet such a demand, studies on a sensing operation of a bit line playing an important role in the high-speed operation of a memory device, have made most actively progress in field of the memory device. In particular, it is well known fact that the sensing operation of the bit line is dependent on a sensing capability and the operating speed of the sense amplifier.

FIG. 1 shows a circuit diagram of a conventional sense amplifier. The circuit comprises a pair of bit lines 9 and 10 connected to a memory cell array block, first and second p-type sensing transistors 5 and 6 constituting p-type sense amplifier, first and second n-type sensing transistors 7 and 8 constituting n-type sense amplifier, isolation transistors and 2, input/output transistors 3 and 4, and a pair of common input/output lines 11 and 12. If a memory cell connected to the bit lines 9 and 10 is selected by a word line (not shown), a voltage A2 of a control terminal of the isolation transistors 1 and 2 is raised to the logic "high" of a power voltage level. Also a voltage A4 of a control terminal of the input/output transistors 3 and 4 is raised to the logic "high" after the operation of the sense amplifiers 5 to 8, to thus transfer the output of data conveyed on the bit lines 9 and 10 to an exterior of the sense amplifier circuit.

The read operation of FIG. 1 is described with reference to a timing chart in FIG. 2. It should be noted that the bit lines 9 and 10 are precharged to a V.sub.cc /2 level before the memory cell is selected, and a node P1 of a common terminal in the p-type sense amplifier and a node N1 of a common terminal in the n-type sense amplifier are also precharged to the V.sub.cc /2 level by the voltages A1 and A3 of the control terminals, respectively. In this case, the voltages A1 and A3 of the control terminals are power sources supplying a potential of the V.sub.cc /2 level. However, when the memory cell is selected, the voltages A1 and A3 of the control terminals respectively provide a power voltage V.sub.cc and a ground voltage V.sub.ss level, by a row address strobe RAS signal. Then, the voltage level of the node N1 is shifted from the V.sub.cc /2 level to the ground voltage level, and the n-type sense amplifier drops the bit line close to the ground voltage level to the ground voltage level. After a given time is passed, the p-type sense amplifier operates and raises the bit line close to the power voltage level to the power voltage level. However, since sensing nodes SAN and SAN are initially precharged to the V.sub.cc /2 level, the charge sharing between the bit lines connected to both sides of the isolation transistors 1 and 2 is considerably delayed, and the variation speed of a potential difference between the bit lines 9 and 10 becomes extremely slow, because of the loading of the bit lines. This leads to a delay of time, the time being that the input/output transistors 3 and 4 are turned on when the potential difference between the bit lines 9 and 10 is approximately 1 V, thereby, the access time of the data becomes slow.

FIG. 3 shows a circuit diagram of another conventional sense amplifier. The circuit is constructed so that array blocks 40 and 45 neighboring to each other share an n-type sense amplifier, input/output transistors 31 and 32, and common input/output lines 35 and 36. Thus, when the array block 40 is selected, a voltage B5 of a control terminal of isolation transistors 23 and 24 is shifted to 0 V, thereby isolating the array block 45 from the shared components. In the same way, when the right array block 45 is selected, a voltage B2 of a control terminal of the isolation transistors 21 and 22 is shifted to 0 V. The circuit of FIG. 3 is greatly improved in view of the degree of integration, in comparison with the circuit of FIG. 1. However, it still has a disadvantage in that the high speed sensing operation is difficult since the sensing operation of the bit line and the transferring operation of data to the common input/output lines 35 and 36, are performed in the same method as that of the circuit of FIG. 1.

It is therefore an object of the present invention to provide a sense amplifier circuit capable of performing a high-speed sensing operation.

In accordance with the present invention, a sense amplifier for use in a semiconductor memory device, the semiconductor memory device having first and second memory blocks including a plurality of memory cells, a pair of sensing lines commonly connected to the first and second memory array blocks, through a pair of first isolation transistors and a pair of second isolation transistors isolating the first and second memory array blocks from the sensing lines when a given memory cell is selected, and a pair of common input/output lines for transferring input/output data to an exterior of a semiconductor memory chip, and data input/output transistors connected between the sensing lines and the common input/output lines, comprises a precharge means connected to the sensing lines positioned between the first and second isolation transistors, for precharging voltage of the sensing lines to a power voltage level by a given control signal, and a sensing means connected to the sensing lines, for amplifying a potential difference between the sensing lines. The precharging means is operated only when the control signal is active state, and the sensing means is operated only when the control signal is non-active state.

The advantages and features of the present invention will be more apparent from the detailed description hereunder, with the reference to the attached drawings, in which:

FIG. 1 shows a circuit diagram of a conventional sense amplifier;

FIG. 2 shows a timing chart illustrating a read operation of FIG. 1;

FIG. 3 shows a circuit diagram of another conventional sense amplifier;

FIG. 4 shows a circuit diagram of a sense amplifier according to the present invention; and

FIG. 5 shows a timing chart illustrating a read operation of FIG. 4.

In the following description, in order to avoid the confusion between the lines up to each array block from the isolation transistors 51 to 54 and the lines 63 and 64 positioned between isolation transistors 51 and 52, and 53 and 54, the former is designated as the bit line and the latter is denoted as the sensing line. Referring to FIG. 4, the reference numeral 100 designates a sense amplifier block according to the present invention. Since isolation transistors 51 to 54, input/output transistors 61 and 62, common input/output lines 65 and 66 and array blocks, etc., are generally known constructive elements, the description for function thereof is omitted. The sense amplifier block 100 is largely divided into a precharge means 100A and a sensing means 100B. The precharge means 100A includes a first load transistor 55 having a gate connected to receive a precharge signal .phi..sub.PR and having a channel connected between a power voltage terminal and a first sensing line 63, and a second load transistor 56 having a gate connected to receive the precharge signal .phi..sub.PR and a channel connected between the power voltage terminal and a second sensing line 64. In this case, it should be noted that the precharge signal .phi..sub.PR is generated from a row address strobe signal RAS, and when the row address strobe signal RAS is generated, the precharge signal .phi..sub.PR is the logic "high" level. The sensing means 100B is comprised of first and second p-type sensing transistors 57 and 58 and first and second n-type sensing transistors 59 and 60. The first p-type sensing transistor 57 has a channel connected between a node P receiving a first latch signal LA and the first sensing line 63, and a gate connected to the second sensing line 64. The second p-type sensing transistor 58 has a channel connected between the node P and the second sensing line 64, and a gate connected to the first sensing line 63. A channel of the first n-type sensing transistor 59 is connected between a node N receiving a second latch signal LA and the first sensing line 63, and a gate thereof is connected to the second sensing line 64. A channel of the second n-type sensing transistor 60 is connected between the node N and the second sensing line 64, and a gate thereof is connected to the first sensing line 63. The first and second p-type sensing transistors 57 and 58 constitute a p-type sense amplifier, and the first and second n-type sensing transistors 59 and 60 constitute an n-type sense amplifier. As shown, a first sensing node SAN on the first sensing line 63 and a second sensing node SAN on the second sensing line 64, sense a potential variation of each sensing line. Moreover, it should be noted that the first and second sensing nodes SAN and SAN are precharged to the potential of a power voltage level, by the first and second load transistors 55 and 56. Furthermore, the first and second latch signals LA and LA, as a load signal of the power voltage level, are applied to the nodes P and N, precharging the potential of the nodes P and N, respectively, to the potential of the power voltage level. During the sensing operation of the sensing line, the first latch signal LA maintains the power voltage level and the second latch signal LA is shifted to a ground voltage level.

The operating characteristic of FIG. 4 is hereafter described with reference to FIG. 5. Moreover, it will be readily appreciated that the first and second bit line BL and BL are precharged to a V.sub.cc /2 level, the first and second sensing nodes SAN and SAN are precharged to the power voltage level V.sub.cc, and the isolation transistors 51 to 54 are all turned off.

Data of a memory cell is transferred to the bit line connected to the memory cell by the selection of a word line, and a potential difference between the first and second bit lines BL and BL is generated. For example, let us assume that the memory cell in the array block 70 is selected. Here, if the logic "high" is applied to a control terminal ISOL of the isolation transistors 51 and 52, the isolation transistor 51 or 52 connecting the bit line of the logic "low" level out of the first and second bit lines BL and BL, to the sensing node SAN or SAN is first turned on. Therefore, the potential of the sensing node connected to the bit line of the logic "low" level comes to lower, since the potential of the sensing node is transferred to the bit line of the logic "low" level. For example, if the potential of the second bit line BL, is lowered, the isolation transistor 52 is turned on prior to the turning on of the isolation transistor 51, and the charge sharing with the second sensing node SAN is generated. Then, since the potential of the second sensing node SAN comes to lower and the first sensing node SAN maintains its potential level, the potential of the second sensing node SAM begins to discharge, through the node N shifted to the ground voltage. Thus, according as the potential of the second sensing node SAN is gradually lowered, the first sensing transistor 59 of the n-type sense amplifier is turned off by degrees and the potential of the first sensing node SAN comes to latch. For example, when reading data "0" of the cell, the data "0" is transferred to the bit line precharged to V.sub.cc /2 level and then is again transferred to the sensing node through the isolation transistor. At this time, assuming that there is no any potential variation, this can be expressed as "V.sub.cc /2.multidot.C.sub.s .apprxeq.(V.sub.cc -V.sub.f).multidot.C.sub.SN ". Wherein C.sub.S is capacitance of the memory cell and C.sub.SN is capacitance of the sensing node. The V.sub.F is a final potential level of the sensing node and is represented as "V.sub.F =V.sub.cc -(C.sub.S .multidot.V.sub.cc)/2C.sub.SN ". Therefore, if V.sub.cc is 5 V and C.sub.SN is 3C.sub.S, the V.sub.F becomes 4.17 V and the potential difference of 0.83 V is generated in the sensing node. The above expression is when the control voltage of the isolation transistor is "V.sub.cc /2+V.sub.TN ", V.sub.TN being a threshold voltage of the isolation transistor. Accordingly, if the control voltage is higher than "V.sub.cc /2+V.sub.TN ", the isolation transistor 51 which is previously turned off is turned on, to thus start the charge sharing with the first sensing node SAN which does not perform the charge sharing. The interval of the time that the isolation transistors 51 and 52 are turned on, can adjust by controlling a rising slope of the control voltage of the isolation transistors 51 and 52 as shown in FIG. 5. However, since the potential difference between the first sensing node SAN and the second sensing node SAN is previously amplified, the potential of the power voltage level is latched in the first sensing node SAN, and the potential of the lower level than the power voltage level is latched in the second sensing node SAN, the potential difference between the first and second sensing nodes SAN and SAN is continuously maintained. Accordingly, the potential of the second sensing node SAN is discharged through the node N of the ground voltage level, turning on the first p-type sensing transistor 57 of the p-type sense amplifier and turning off the first n-type sensing transistor 59 of the n-type sense amplifier, respectively. Also the potential of the first sensing node SAN continuously maintains the potential of the power voltage level through the node P of the power voltage level. Since the above sensing operation is performed at high speed and the potential difference between the first and second sensing nodes SAN and SAN is greatly increased, the sufficient potential difference is directly transferred to the common input/output lines 65 and 66 through the input/output transistors 61 and 62. Thus, the transfer of data to the exterior of the semiconductor memory chip is performed at high speed. This will be readily appreciated ,if comparing an interval T2 of FIG. 5 with the interval T1 of FIG. 2. That is, since at the interval T1, there is little difference between voltages of the common input/output lines I/O and I/O, it is difficult to perform the access operation of the desired data at high speed, but since at the interval T2, the difference between the voltages of the common input/output lines I/O and I/O is sufficiently large, the access operation of the data is performed at high speed.

As described above, the sense amplifier according to the present invention has a simple layout. Because the sensing operation is sufficiently performed at high speed, the sense amplifier according to the present invention is effective in a memory device using the low power voltage. Accordingly, the memory device having high operating speed, though the loading of the bit lines is large, such as a highly integrated dynamic RAM over 16 mega byte, can be realized.

While the present invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that foregoing and other changes in form and details may be made without departing from the spirit and scope of the present invention