Double Conversion Digital Tuning System Using Separate Digital Numbers for Controlling the Local Oscillators

This application is related to, but not dependent upon, copending application Ser. No. 815,721, filed Dec. 30 1991, entitled BANDSWITCHED TUNING SYSTEM FOR A DIGITAL TELEVISION RECEIVER.

This invention relates generally to double conversion television tuning systems and in particular to a double conversion tuning system for use with digital television (TV) signals.

The recently proposed Zenith/AT&T Digital Spectrum Compatible High Definition Television System (DSC/HDTV) transmits wide band television information that is digitally encoded. Processing of the digital information imposes severe restrictions on the amount of phase noise that may be tolerated in the tuning system. It is critical that the tuning system impose a minimal amount of phase noise on the digital information which, lacking the redundancy of conventional television signals, demands accurate detection and decoding. A double conversion type tuning system appears to be the most desirable for digital HDTV signals, although conventional NTSC double conversion tuning systems do not exhibit sufficiently low phase noise characteristics to be entirely satisfactory. This is due to both the low "Q" of the varactor diode-tuned tank circuit in the first local oscillator of the double conversion tuning stage and the narrow band phase locked loop (PLL) of the synthesizer. The arrangement of copending application Ser. No. 815,721 above remedies the first part of the problem, i.e. low Q of the tuned circuits. The latter part of the problem is the subject of the present invention. Thus the present invention describes a double conversion tuning system that meets both the criteria of low phase noise and tuning accuracy.

A principal object of the invention is to provide an improved double conversion television signal tuning system.

Another object of the invention is to provide a double conversion television tuning system that exhibits low phase noise.

A further object of the invention is to provide a double conversion tuning system suitable for use with digital television signals.

These and other objects and advantages of the invention will be apparent upon reading the following description in conjunction with the drawing, the single figure of which is a partial block diagram illustrating a double conversion television signal tuner constructed in accordance with the invention.

Referring to the figure, an RF input signal, which may comprise either an over-the-air or a cable-connected television signal in the VHF-UHF frequency range of 50 MHz to 800 MHz, is applied to an input terminal. In accordance with the disclosure in the above mentioned copending application Ser. No. D6613, a selective bandpass filtering and trapping network is provided for enhancing the tuned signal, i.e. minimizing interferences from other signals. The selective filtering circuit is controlled by a microprocessor 12 which also controls tuning of the tuning system and other functions of the receiver that are not relevant to this invention. The output of the selective filter 10 is coupled to a first mixer 14 that is supplied with a signal from a first local oscillator 11 which is part of a phase locked loop 16. A first IF signal is developed and applied to a first IF filter and amplifier 18, the output of which is applied to a second mixer 20. The output of a second local oscillator 26 is applied to second mixer 20 and is heterodyned with the first IF signal to produce a second IF signal of fixed frequency, which is applied to a second IF amplifier 28. A dielectric resonator 27 comprises the tank circuit of second local oscillator 26. The output of second IF amplifier 28 is supplied to a signal processing circuit 29 which should be understood to include the remainder of the television signal processing circuitry. Processing circuit 29 develops an AFC signal which is applied to an adder 24, the output of which controls, via properly coupled varactors (not shown), the resonant frequency of dielectric resonator 27, which in turn controls the frequency of the second local oscillator 26. It will be appreciated that other frequency controllable elements such as a SAW resonator may be used in place of dielectric resonator 27. The other input of adder 24 is supplied from microprocessor 12 through a digital-to-analog converter (D/A) 22. The phase locked loop 16 for controlling the first local oscillator signal includes a filter 13, a phase detector 15, a crystal controlled reference oscillator 17, a programmable divider 19 and a prescaler 21. Microprocessor 12 supplies a first digital number to programmable divider 19 that is related to the RF channel signal to be tuned. Divider 19, in conjunction with prescaler 21, develops an input to phase detector 15 that is representative of the frequency of first local oscillator 11 for comparison with a divided down reference signal. Crystal controlled reference oscillator 17 supplies a reference signal to a reference frequency divider 23 which provides the divided down reference signal to phase detector 15. Reference frequency divider 23 is also controlled by microprocessor 12, i.e. microprocessor 12 supplies a digital number to frequency divider 23 that is related to the RF signal to be tuned. The output of phase detector 15 is applied through a filter 13 for controlling the frequency of first local oscillator 11.

In accordance with the invention, phase locked loop 16 is designed to exhibit very low phase noise. To produce a low phase noise characteristic, a relatively large reference frequency is desirable. This makes it possible to increase the bandwidth of the phase locked loop and thus "clean" a wider frequency band of the first local oscillator noisy spectrum. The difficulty is that a large reference frequency for the first local oscillator results in tuning steps of almost 1 MHz, which are quite coarse. This coarse synthesizer resolution may be conventionally increased by using multiple loop synthesizers. However, such an approach, while justifiable for expensive test equipment, is out of the question for a television receiver tuner. In practice, the tuning system develops a first IF signal frequency that may deviate by .+-. 1/2 MHz from the desired first IF signal frequency. In the embodiment chosen for the purposes of description, the desired first IF signal frequency is 920 MHz and with the low phase noise phase locked loop system of the invention, the deviation in first IF signal frequency is within 1/2 MHz of 920 MHz. It will be appreciated that for some channels, the deviation may be less than 1/2 MHz. Also the system could be designed to accommodate a different maximum deviation.

A .+-. 1/2 MHz deviation in the first IF signal frequency is not acceptable with a fixed frequency second local oscillator downconverter. In the digital receiver, the second IF frequency must be maintained very close to 44 MHz. (The pull in range of the whole receiver is about .+-. 100 KHz.) In accordance with the invention, two look-up tables are provided for channel tuning. One look-up table contains a first digital number to apply to programmable divider 19 for coarsely controlling the desired one of the incoming RF television signal frequencies and the other look-up table contains a second digital number to be applied to D/A converter 22 for fine controlling the frequency of the second local oscillator to compensate for the (known) deviation in the first IF signal frequency. The result is that the second IF signal frequency is constant at 44 MHz despite the deviation in the first IF signal frequency.

Assume, for purposes of illustration, that a 100 MHz RF input signal is to be tuned. To produce a nominal 920 MHz first IF signal frequency, a first local oscillator signal of 1020 MHz is required. Downconversion to a 44 MHz second IF signal frequency requires a second local oscillator signal frequency of 920-44=876 MHz. Assume that the crystal reference and programmable divider used result in the first local oscillator signal frequency of 1020.5 MHz rather than 1020 MHz. The look-up tables accessed by the microprocessor would contain the first number for the programmable divider and the second number for the D/A 22. The second number would produce a voltage to adjust the second local oscillator signal frequency to compensate sufficiently for the fact that the first local oscillator signal frequency is 1/2 MHz higher than desired and has resulted in a first IF signal frequency that is also 1/2 MHz higher than the desired first IF signal frequency, i.e. 920.5 MHz rather than 920 MHz. The second local oscillator signal frequency, instead of being 876 MHz, is adjusted to 876.5 MHz. The adjustment results in the second IF signal frequency of 44 MHz. The provision of an AFC voltage to adder 24 is not required but may be useful for certain types of processing circuits 29.

Thus, with the invention, a single low noise wide band phase locked loop may be used for the first local oscillator in the double conversion tuner and deviations in the first IF signal frequency due to the relatively low resolution of the first local oscillator are compensated by increasing the resolution of the second local oscillator to maintain a second IF signal frequency of 44 MHz. It is recognized that numerous changes in the described embodiment of the invention will occur to those skilled in the art without departing from its true spirit and scope. The invention is to be limited only as defined in the claims.