Above via Metal-to-Metal Antifuse

1. Field Of The Invention

The present invention relates to user-programmable antifuse technology. More particularly, the present invention relates to metal-to-metal antifuses and to above-via metal-to-metal antifuses.

2. The Prior Art

In the practice of antifuse fabrication technology, it has been found that scaling problems occur when depositing antifuse material, such as PECVD amorphous silicon, into via openings having depths greater than about 0.4 microns and widths narrower than about 1.0 microns. These scaling problems consist of reduced antifuse breakdown voltage and uniformity and increased current leakage in the antifuse structure. As the depth/width aspect ratio of the antifuse via increases, the scaling problems get worse. This is due to the reduced step coverage (final thickness) of the antifuse material at the bottom of the antifuse via. As the antifuse via depth increases and or the width gets smaller, step coverage of most deposited films gets worse and the scaling problems increase. If the antifuse material layer is thickened to obtain higher breakdown voltage, a problem develops with the top electrode. Because the via is even smaller after the antifuse material layer is deposited, it becomes very hard to deposit enough upper electrode material into the via to ensure it will be reliable.

For example, if about 1,000 angstroms of amorphous silicon antifuse material (for a 10 volt antifuse breakdown voltage value) is required in the bottom of the via and the step coverage into a via having an initial size of 0.8 microns is 60%, the amorphous silicon deposition thickness required will be 0.18, so the sidewall coverage of the via at its thickest point at the top of the via will be about 0.18 microns. The resulting reduced-size via available for metal deposition is then roughly 0.8-0.36=0.44 microns wide. When depositing the top metal electrode into this 0.44 micron wide via, the amount of metal which can be deposited is limited by the fact that the via tends to close off during the deposition process, leaving a partial void. If the via is 0.44 microns, only 0.22 microns of metal may be deposited on the via sides before the via closes off. At about 50% step coverage inside the via, the 0.22 microns/side top electrode metal is about 0.11 microns thick at its thinnest point on the sidewall of the via. Because the via is now closed off, there is no room left for any interconnect metal to get into the via and the reliability of about 0.11 microns of top electrode as an interconnect may be a concern.

As those of ordinary skill in the art will appreciate, when this process is scaled to a via of 0.6 microns, and 0.2 microns/side of amorphous silicon is deposited (0.2 microns at 50% step coverage=0.1 microns at the bottom of the via, a reduced step coverage as via gets smaller) there is only 0.6-0.4=0.2 microns via left into which to deposit the top electrode. Now only 0.1 micron/side of top electrode can be deposited before the via closes off and, at 40% step coverage (step coverage is less due to smaller via size), there will be about 400 angstroms of top electrode as metal interconnect to the antifuse material at the thinnest point on the via sidewall. This 400 angstroms of interconnection to the antifuse in the via is a big reliability concern.

According to a first aspect of the present invention, a method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to expose an upper surface of the via metal layer and an upper surface of the interlayer dielectric layer so as to form a substantially planar surface comprising the upper surface of the interlayer dielectric layer, the planarizing layer, and the upper surface of the via metal layer; (7) forming an antifuse material layer over the substantially planar surface; (8) forming a metal capping layer over the antifuse material layer; and (9) defining the antifuse material layer and the metal capping layer. The method may include the steps of forming a spacer on sidewalls of the antifuse material layer and the metal capping layer; and forming and defining a second metal interconnect layer over the metal capping layer.

According to a second aspect of the present invention, a method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing and defining a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to form a planar surface on an upper surface of the via metal layer and to form spacers at the edges of the via metal layer; (7) forming an antifuse material layer over the substantially planar surface; (8) forming a metal capping layer over the antifuse material layer; (9) defining the antifuse material layer and the metal capping layer; and (10) forming spacers at the edge of the antifuse and metal layers.

According to a third aspect of the present invention, a method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to expose an upper surface of the via metal layer so as to form a substantially planar surface comprising the upper surface of the via metal layer; (7) forming an antifuse material layer over the substantially planar surface; (8) defining the antifuse material layer and the metal capping layer, and (9) forming spacers around the edges of the metal capping layer over the antifuse material layer.

According to a fourth aspect of the present invention, a method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to expose an upper surface of the via metal layer so as to form a substantially planar surface comprising the upper surface of the via metal layer; (7) forming a conductive layer over the planar surface; (8) defining the conductive layer and the via metal layer; (9) forming an additional dielectric layer and forming an antifuse aperture therein to expose the conductive layer; (10) forming an antifuse material layer over the additional dielectric layer in the antifuse via therein; (11) forming a metal capping layer over the antifuse material layer; (12) defining the antifuse material layer and the metal capping layer; and (13) forming spacers around the edges of the antifuse material layer and the metal capping layer. The method may include the steps of forming a spacer on sidewalls of the antifuse material layer and the metal capping layer; and forming and defining a second metal interconnect layer over the metal capping layer.

According to a fifth aspect of the present invention, a method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to expose an upper surface of the via metal layer and an upper surface of the interlayer dielectric layer so as to form a substantially planar surface comprising the upper surface of the interlayer dielectric layer, the planarizing layer, and the upper surface of the via metal layer; (7) forming a conductive layer over the substantially planar surface (8) forming an antifuse material layer over the conductive layer; (9) forming a metal capping layer over the antifuse material layer; and (10) defining the conductive layer, the antifuse material layer and the metal capping layer. The method may include the steps of forming a spacer on sidewalls of the antifuse material layer and the metal capping layer; and forming and defining a second metal interconnect layer over the metal capping layer.

FIG. 1 is a cross-sectional view of an above-via antifuse structure according to a first embodiment of the present invention.

FIGS. 2a-2e are cross-sectional views of the antifuse structure of FIG. 1 at various stages during the progression of the fabrication process.

FIG. 3 is a cross-sectional view of an above-via antifuse structure according to a second embodiment of the present invention.

FIGS. 4a-4c are cross-sectional views of the antifuse of FIG. 3 at various stages during the progression of the fabrication process.

FIG. 5 is a cross-sectional view of an above-via antifuse structure according to a third embodiment of the present invention.

FIGS. 6a-6d are cross-sectional views of the antifuse structure of FIG. 5 at various stages during the progression of the fabrication process.

FIG. 7 is a cross-sectional view of an above-via antifuse structure according to a fourth embodiment of the present invention.

FIGS. 8a-8d are cross-sectional views of the antifuse structure of FIG. 7 at various stages during the progression of the fabrication process.

FIG. 9 is a cross-sectional view of an above-via antifuse structure according to a fifth embodiment of the present invention.

FIGS. 10a-10b are cross-sectional views of the antifuse structure of FIG. 9 at various stages during the progression of the fabrication process.

Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

Referring first to FIG. 1, a cross-sectional view of the structure of an above-via antifuse 10 according to a first embodiment of the invention is shown. Antifuse 10 is formed on a substrate 12. Substrate 12 may comprise an insulating substrate or an insulating layer formed over a conductive or semiconductor substrate. A lower antifuse electrode 14 is disposed over the substrate 12 using standard deposition techniques. Lower electrode 14 may comprise a sandwich structure of TiW/AlSiCu/TiW, and may be a portion of a metal interconnect layer in an integrated circuit or other microcircuit.

An interlayer dielectric layer 16 is disposed over lower electrode 14 and may comprise, for example, PECVD silicon dioxide. An antifuse via 18 is then patterned and etched in the interlayer dielectric 16 to expose the upper surface of lower electrode 14.

Normally, a layer of antifuse material would next be formed in antifuse via 18 at this stage of a conventional antifuse fabrication process, and an upper electrode would be formed over the layer of antifuse material to complete the antifuse structure.

The structure of the antifuse of the present invention is different, and may be referred to as an "above-via" antifuse because of its structure. A layer of a conductive material 20, such as TiW, is formed in the antifuse via 18. Those of ordinary skill in the art will recognize that, due to the depth and aspect ratio of the antifuse via, a void will be unoccupied by conductive material 20. According to the present invention, a layer of planarizing material, such as spin-on glass (SOG) is deposited on the surface of the structure and a portion of planarizing material 22 fills the void volume. The surface of the planarizing material 22 and the conductive material 20 is then planarized to the surface of the interlayer dielectric 16 using appropriate etching techniques.

An antifuse material layer 24 is formed over the planarized surface of the conductive material 20 and planarizing material 22 in the antifuse via 18. According to a presently preferred embodiment of the invention, antifuse layer 24 may comprise a single layer of amorphous silicon. Alternatively, antifuse layer 24 may comprise a composite layer of silicon nitride, silicon nitride/amorphous silicon, amorphous silicon/silicon nitride, silicon nitride/amorphous silicon/silicon nitride, amorphous silicon/silicon nitride/amorphous silicon, silicon dioxide/silicon nitride, silicon nitride/silicon dioxide, silicon nitride/silicon dioxide/silicon nitride, or silicon dioxide/silicon nitride/silicon dioxide. This is not an exhaustive list for the composition of antifuse material layer 24, and those of ordinary skill in the art will be able to substitute other appropriate materials.

An upper antifuse electrode 26 is formed over the antifuse material layer 24. This upper electrode 26 may be formed from a material such as TiW, Ti, TiN, or TiW:N and thus also serves as a barrier layer to prevent contamination of the antifuse material from atoms in overlying the metal layer. The stacked structure comprising antifuse material layer 24 and upper antifuse electrode 26 are patterned and defined using conventional processing technology and spacers 28 are formed at the edges of the stacked structure. Spacers 28 may be formed by depositing and etching back an oxide layer.

Finally, an upper metal interconnect layer 30 is formed over the upper antifuse electrode 26. Spacers 28 act to ease the conformality problem which would otherwise exist at the edges of the stacked structure.

Referring now to FIGS. 2a-2e, cross-sectional views are shown of the antifuse of FIG. 1 after completion of certain of the steps in the fabrication process in order to illustrate the fabrication process. Referring first to FIG. 2a, the structure is shown after formation of the lower electrode 14, interlayer dielectric 16 and antifuse via 18, conductive layer 20, and planarizing layer 22. Lower electrode 14 may be a first metal interconnect layer and is preferably formed from TiW/AlSiCu/TiW to a thickness of about 3,000 angstroms, 4,500 angstroms, and 1,000 angstroms, top layer to bottom layer, respectively. Interlayer dielectric 16 will typically be a layer of PECVD silicon dioxide having a thickness of about 8,000 angstroms and a typical via 18 may have dimensions of 0.8 microns by 0.8 microns. Conductive material 20 preferably comprises a TiW layer having a thickness of between about 2,000 to 6,000 angstroms, preferably about 3,000 angstroms.

As will be understood by those of ordinary skill in the art, spin-on glass (SOG) is a commonly-used planarizing layer. It is a self-planarizing film that thins down over high points and fills deep pockets or height differential steps. It is applied as a liquid to the wafer and spreads out over the surface of the wafer as the wafer is spun. According to a presently preferred embodiment of the invention, the SOG planarizing layer is deposited to a thickness of between about 1,000 to 4,000 angstroms, preferably about 2,500 angstroms. A double spin step may be used, if necessary, to achieve adequate planarization.

FIG. 2b shows the structure resulting after the planarizing layer 22 has been etched back to be even with the surface of interlayer dielectric 16. For an SOG planarizing layer, a standard oxide-type etch, such as CHF.sub.3 gas is used to etch back 4,000 angstroms of the SOG layer with a 40% overetch.

Next, as shown in FIG. 2c, the TiW conductive layer 20 is etched back using a standard TiW type etching process. As presently preferred, a CF.sub.4 /O.sub.2 or SF.sub.6 /Ar gas chemistry etch may be utilized to etch bach the Ti W layer 3,000 angstroms with a 30% overetch. This will leave the material in via 18 planarized level with the top surface of the interlayer dielectric 16. In situations involving deep or high aspect-ratio vias, a first SOG etch-back step may be followed by a second spin-on application and a second etch-back step to completely fill the void left by the incomplete filling of via 18 with conductive material 20.

Referring now to FIG. 2d, the antifuse structure is shown after formation and definition of antifuse material layer 24 and upper electrode 26. As previously mentioned, antifuse material layer 24 may be formed from a variety of materials and thicknesses, depending upon the desired programming and other electrical characteristics desired for the finished antifuse. As previously stated, upper electrode 26 may be formed from a material such as TiW, Ti, TiN, or TiW:N and thus also serves as a capping or barrier layer to prevent contamination of the antifuse material from atoms in overlying the metal layer. A typical thickness for upper electrode 26 may be between about 500 to 3,000 angstroms, preferably about 3,000 angstroms. FIG. 2d shows the structure resulting after the stack of layers 24 and 26 have been defined by conventional masking and etching steps and the masking layer has been removed.

Referring now to FIG. 2e, spacers 28 have been formed around the periphery of the stack of layers 24 and 26 in order to minimize any step coverage problems for the second metal interconnect layer which will next be formed over the upper antifuse electrode 26. The spacers are preferably formed from a layer of silicon dioxide which is deposited to a thickness of about 4,000 angstroms and then etched back to leave the spacers 28. Those of ordinary skill in the art will be familiar with processing steps for forming spacers.

The antifuse shown in FIG. 2e is essentially complete. A final step in the fabrication process usually comprises forming a second metal interconnect layer 30 in contact with the upper electrode 26, although those of ordinary skill in the art will recognize that an insulating layer may be formed over the upper antifuse electrode 26 and a contact via may be formed therein to make contact to the upper electrode 26 from an overlying conductive layer. Such skilled persons will also recognize that the formation of the second metal layer is preceded by formation of inter-metal contact vias. The finished structure is depicted in FIG. 1.

The antifuse according to the first embodiment of the present invention may be fabricated with two masks, one to create the via 18 and one to define the stacked antifuse material layer 24 and upper electrode 26. The antifuse of this embodiment of the invention eliminates the topography problems encountered in metal-to-metal antifuses, including depositing the antifuse material layer in the via 18 and dealing with the step coverage issues which cause non-uniform breakdown. The antifuse of the present invention also eliminates locating the antifuse stack on top of the first metal layer where the planarization of the interlayer dielectric and the etch of the first metal interconnect layer become issues.

The antifuse according to this embodiment of the invention has a very low capacitance due to the small area where the bottom of the antifuse is in contact with the via TiW. This means that it will have a lower leakage and allow higher speed and lower power requirements in products containing it.

Referring now to FIG. 3, a second embodiment of an antifuse structure according to the present invention is shown in cross-section. Like the antifuse illustrated in FIG. 1, the antifuse of FIG. 3 is formed over a substrate 12 and a lower electrode 14 which may comprise a metal interconnect layer in an integrated circuit. An interlayer dielectric 16 is formed and an antifuse via 18 is formed in therein by conventional masking and etching techniques. A layer of conductive material 20 is formed in antifuse via 18 and a planarizing layer is formed in the void remaining in the antifuse via 18 after the conductive layer 18 has been formed therein.

Unlike the embodiment of FIG. 1, wherein the conductive layer 20 and the planarizing layer are planarized to the upper surface of the interlayer dielectric 16, the conductive layer in the antifuse of FIG. 3 is first defined prior to application of the SOG planarizing layer. As a result, when the planarizing layer is etched back, spacers 32 are formed at the edges of conductive layer 20. A stack comprising antifuse material layer 24 and upper electrode 26 are disposed over the defined conductive layer 20 and spacers 32. This stack is defined and spacers 34 are formed at the edges of the stack. A second metal interconnected layer 30 is preferably disposed over the upper antifuse electrode.

Referring now to FIGS. 4a-4e, cross-sectional views are shown of the antifuse of FIG. 3 after completion of certain of the steps in the fabrication process in order to illustrate the fabrication process. The layer thicknesses and material employed in the antifuse of FIG. 3 may be the same as those employed in the antifuse of FIG. 1.

Referring first to FIG. 4a, the structure is shown after formation of the lower electrode 14, interlayer dielectric 16 and antifuse via 18. Conductive layer 20 has been formed and defined using conventional deposition, masking and etching steps, and planarizing layer 22 has been placed on the surface of the structure and etched back to form a surface planar with the upper surface of conductive layer 20. The etch-back process also advantageously forms spacers 32 at the edges of conductive layer 20. In situations involving deep or high aspect-ratio vias, a first SOG etch-back step may be followed by a second spin-on application and a second etch-back step to completely fill the void left by the incomplete filling of via 18 with conductive material 20.

FIG. 4b shows the structure resulting after the stack comprising antifuse layer 24 and upper electrode 26 have been formed and defined using conventional deposition, masking, and etching steps. In FIG. 4b, the masking layer for defining the stack has already been removed.

Next, as shown in FIG. 4c, spacers 34 are formed at the edges of the stack structure, preferably by using the known technique of first depositing and then etching back a silicon dioxide layer. The presence of spacers 34 improve the step coverage when later depositing second metal interconnect layer 30. The finished structure, after deposition and definition of second metal layer 30, is depicted in FIG. 3.

The antifuse according to the second embodiment of the present invention may be fabricated with three masks, one to create the via 18, one to define the conductor layer 20, and one to define the stacked antifuse material layer 24 and upper electrode 26. The antifuse of this embodiment of the invention also eliminates the topography problems encountered in metal-to-metal antifuses, including depositing the antifuse material layer in the via 18, dealing with the step coverage issues which cause non-uniform breakdown, and eliminating placement of the antifuse stack on top of the first metal layer where the planarization of the interlayer dielectric and the etch of the first metal interconnect layer become issues.

Referring now to FIG. 5, an antifuse structure according to a third embodiment of the invention is shown in cross-sectional view. Like the antifuse illustrated in FIGS. 1 and 3, the antifuse of FIG. 5 is formed over a substrate 12 and a lower electrode 14 which may comprise a metal interconnect layer in an integrated circuit. An interlayer dielectric 16 is formed and an antifuse via 18 is formed in therein by conventional masking and etching techniques. A layer of conductive material 20 is formed in antifuse via 18 and a planarizing layer 22 is formed in the void remaining in the antifuse via 18 after the conductive layer 20 has been formed therein. An antifuse material layer 24 is disposed over the planarized surface. The stacked structure comprising antifuse material layer 24 and conductive material 20 are patterned and etched using conventional processing techniques. The edges of the antifuse material layer 24 are aligned to the edges of the conductive material layer and are aligned to one another. Oxide spacers 34 are formed at the edges of the conductive material layer and the antifuse material layer. The upper electrode 26 and the second metal interconnect layer 30 are disposed over the antifuse material layer 24 and spacers 34.

Referring now to FIGS. 6a-6e, cross-sectional views are shown of the antifuse of FIG. 5 after completion of certain of the steps in the fabrication process in order to illustrate the fabrication process. The layer thicknesses and material employed in the antifuse of FIG. 5 may be the same as those employed in the antifuses of FIG. 1 and FIG. 3.

Referring first to FIG. 6a, the structure is shown after formation of the lower electrode 14, interlayer dielectric 16 and antifuse via 18. Conductive layer 20 has been formed using conventional deposition steps, and planarizing layer 22 has been placed on the surface of the structure and etched back to form a surface planar with the upper surface of conductive layer 20. In situations involving deep or high aspect-ratio vias, a first SOG etch-back step may be followed by a second spin-on application and a second etch-back step to completely fill the void left by the incomplete filling of via 18 with conductive material 20.

Referring now to FIG. 6b, the antifuse material layer 24 is deposited and stack comprising antifuse layer 24 and conductive layer 20 have been formed and defined using conventional deposition, masking, and etching steps. In FIG. 6b, the masking layer for defining the stack has already been removed and it can be seen that the edges of antifuse layer 24 and conductive layer 20 are aligned.

Next, as shown in FIG. 6c, spacers 34 are formed at the edges of the stack structure, preferably by using the known technique of first depositing and then etching back a silicon dioxide layer. The presence of spacers 34 prevent the conductive layer 20 from short circuiting to the upper electrode 26 and improve the step coverage when later depositing second metal interconnect layer 30.

Referring now to FIG. 6d, upper electrode 26 is deposited over the exposed surface in contact with antifuse material layer 24. The spacers 34 facilitate step coverage over the stack of conductive layer 20 and antifuse material layer 24. The finished structure, after deposition and definition of second metal layer 30, is depicted in FIG. 5.

The antifuse according to the third embodiment of the present invention may be fabricated with two masks, one to create the via 18, and one to define the conductor layer 20 and antifuse material layer 24. The antifuse of this embodiment of the invention also eliminates the topography problems encountered in metal-to-metal antifuses, including depositing the antifuse material layer in the via 18, dealing with the step coverage issues which cause non-uniform breakdown, and eliminating placement of the antifuse stack on top of the first metal layer where the planarization of the interlayer dielectric and the etch of the first metal interconnect layer become issues.

Referring now to FIG. 7, an antifuse structure according to a fourth embodiment of the invention is shown in cross-sectional view. Like the antifuse illustrated in FIGS. 1, 3, and 5, the antifuse of FIG. 7 is formed over a substrate 12 and a lower electrode 14 which may comprise a metal interconnect layer in an integrated circuit. An interlayer dielectric 16 is formed and an antifuse via 18 is formed in therein by conventional masking and etching techniques. A layer of conductive material 20 is formed in antifuse via 18 and a planarizing layer is formed in the void remaining in the antifuse via 18 after the conductive layer 20 has been formed therein.

The structure of the antifuse of FIG. 7 is substantially different from the other antifuse structures of the previously-disclosed embodiments of the present invention. An additional conductive layer 36, preferably formed from TiW, is disposed over the planarized conductive layer 20 and aligned therewith. An additional dielectric layer 38, preferably formed from silicon dioxide to a thickness of between about 1,000 to 4,000 angstroms, preferably about 2,000 angstroms, is disposed over the stack of layers 20 and 36 and the interlayer dielectric 16. A second antifuse via 40 communicates with the additional conductive layer 36, and an antifuse material layer 24 is disposed in the via 40. An upper electrode 26 is aligned with the edges of antifuse material layer 24. Spacers 42 are disposed at the edges of the stack of layers 24 and 26, and a second metal interconnect layer 30 is disposed over the top of the structure. Because of the additional oxide layer 38 and via structure 40, the antifuse of FIG. 7 has a smaller capacitance in its unprogrammed state than do the antifuses of FIGS. 3 and 5.

Referring now to FIGS. 8a-8e, cross-sectional views are shown of the antifuse of FIG. 7 after completion of certain of the steps in the fabrication process in order to illustrate the fabrication process. The layer thicknesses and materials employed in the antifuse of FIG. 7 may be the same as those employed for corresponding structures in the antifuses of FIGS. 1, 3, and 5.

Referring first to FIG. 8a, the structure is shown after formation of the lower electrode 14, interlayer dielectric 16 and antifuse via 18. Conductive layer 20 has been formed using conventional deposition steps, and planarizing layer 22 has been placed on the surface of the structure and etched back to form a surface planar with the upper surface of conductive layer 20. As with the previous embodiments, a first SOG etch-back step may be followed by a second spin-on application and a second etch-back step to completely fill the void left by the incomplete filling of via 18 with conductive material 20 in situations involving deep or high aspect-ratio vias. An additional conductive layer 36, preferably comprising a layer of TiW having a thickness of between about 500 angstroms to 3,000 angstroms, preferably about 1,000 angstroms, is deposited over the planarized surface of the conductive layer 20 and the composite stack is defined using conventional masking and etching techniques. FIG. 8a shows the structure resulting after removal of the masking layer used to define the edges of conductive layer 20 and additional conductive layer 36.

Referring now to FIG. 8b, an additional dielectric layer 38 is formed over the structure depicted in FIG. 8a. An additional antifuse via 40 is formed in additional dielectric layer 38. FIG. 8b depicts the structure after the mask used to form additional via 40 has been removed.

Next, as shown in FIG. 8c, antifuse material layer 24 and upper electrode 26 are deposited and defined using conventional semiconductor processing techniques. FIG. 8c depicts the structure after the masking layer used to define the edges of antifuse material layer 24 and upper electrode 26 has been removed.

Referring now to FIG. 8d, an oxide layer is deposited over the exposed surface and is etched back to form spacers 42. After the spacers have been formed, second metal interconnect layer 30 is formed and defined using conventional techniques. The finished structure, after deposition and definition of second metal layer 30, is depicted in FIG. 7.

The antifuse according to the fourth embodiment of the present invention may be fabricated with four masks, one to create the via 18, one to define the stack comprising layers 20 and 36, one to form via 40, and one to define the stack comprising layers 24 and 26. The antifuse of this embodiment of the invention has a capacitance less than that of the embodiments of FIGS. 3 and 5 and also eliminates the topography problems encountered in metal-to-metal antifuses, including depositing the antifuse material layer in the via 18, dealing with the step coverage issues which cause non-uniform breakdown, and eliminating placement of the antifuse stack on top of the first metal layer where the planarization of the interlayer dielectric and the etch of the first metal interconnect layer become issues.

Referring now to FIG. 9, a fifth embodiment of the antifuse of the present invention is shown in cross-sectional form. The antifuse of FIG. 9 is similar to the antifuse of FIG. 1 in that the planarization of the conductive layer 20 in antifuse via 18 is performed in the same manner. FIGS. 2a-2c illustrate this portion of the process for the antifuse of FIG. 9.

Referring now to FIG. 10a, an additional conductive layer 36 is formed over the planarized structure. This layer has the same composition as its counterpart in the embodiment of FIG. 7. Antifuse material layer 24 and upper electrode 26 are then deposited over additional conductive layer 36. The stack comprising layers 36, 24, and 26 is then defined using conventional masking and etching steps. FIG. 10a shows the structure resulting after the masking layer for defining the stacked structure has been removed.

Referring now to FIG. 10b, spacers 44 are formed by depositing a layer of silicon dioxide and etching it back to leave spacers at the edges of the stack comprising layers 36, 24, 26. The next step comprises forming and defining second metal interconnect layer 30 using conventional semiconductor fabrication processes. The finished antifuse structure is depicted in FIG. 9.

Variations of the antifuse structures herein include structures wherein a layer of a material such as TiW over the planarized surface prior to formation of subsequent layers. These embodiments are equivalent to the disclosed embodiments.

Those of ordinary skill in the art will recognize that, although the disclosure of the present invention has been made in terms of first and second metal interconnect layers, and that the terminology used in the claims has been consistent therewith, the present invention relates to antifuses disposed between metal layers generally, and is equally applicable to antifuses disposed between any metal layers, for example, the first and second, second and third, and first and third metal layers in a three metal layer structure. Thus the words "first" and "third" are not to be restricted in meaning by the number of metal layers in a particular integrated circuit containing antifuses fabricated according to the present invention. In addition, such skilled persons will recognize that the capping layers separately referred to herein may in some cases comprise one layer of multi-layer metal interconnect layers which are known in the art.

While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.