Method of Selectively Etching Silicon Dioxide Dielectric Layers on Semiconductor Wafers

This invention relates generally to methods of utilizing and etching SiO.sub.2 in the processing of semiconductor wafers.

At some point in the processing of semiconductor wafers, it is common to need to etch one dielectric layer selectively relative to an underlying dielectric layer. This is typically accommodated by utilizing chemically different dielectric layers, such as an oxide and a nitride, and utilizing a wet acid or other chemistry which enables etching of the overlying material relative to the underlying material. One drawback with such techniques is that typically the two different dielectrics do not have the same thermal coefficient of expansion. This can create undesired stress in the resulting structure where remaining adjoined layers of an oxide and a nitride exist.

Silicon dioxide can be provided atop a wafer in both doped and undoped forms. Example dopants include phosphorus and boron, which can be utilized to produce phosphosilicate glass (PSG), borosilicate glass (BSG) and borophosphosilicate glass (BPSG). Such dopants can improve step coverage, diffusion barrier properties, stress reduction, and improve flow characteristics enabling dielectric flow at lower temperatures. Additionally, doped and undoped silicon dioxide has very similar thermal expansion coefficients.

It would be desirable to develop a wet etching chemistry that would enable etching of doped silicon dioxide selectively relative to undoped silicon dioxide.

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

FIG. 1 is a diagrammatic section of a semiconductor wafer at a processing step in accordance with the invention.

FIG. 2 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 1.

FIG. 3 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 2.

FIG. 4 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown by FIG. 3.

This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws "to promote the progress of science and useful arts" (Article 1, Section 8).

In accordance with the invention, a method of utilizing and etching SiO.sub.2 in the processing of semiconductor wafers comprises the following steps:

providing a layer of undoped SiO.sub.2 atop a wafer;

providing a layer of doped SiO.sub.2 atop the layer of undoped SiO.sub.2 ; and

wet etching the layer of doped SiO.sub.2 selectively relative to the undoped layer of SiO.sub.2 utilizing an acid solution, the acid solution comprising a mixture of at least two different mineral acids provided in a selected ratio relative to one another, one of the mineral acids being HF.

The undoped SiO.sub.2 can be deposited or provided by any known technique. The doped SiO.sub.2 can be any of borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or others. The invention has been reduced to practice utilizing undoped SiO.sub.2 deposited by decomposition of tetraethylorthosilicate (TEOS) followed by TEOS densification, with the doped SiO.sub.2 comprising borophosphosilicate glass having six weight percent phosphorus and three weight percent boron.

It is expected that the other of the mineral acids could comprise any variety of mineral acid or combinations of mineral acids. In the context of this document, "mineral acid" has its standard definition of an inorganic acid. The invention has been reduced to practice utilizing other mineral acids of H.sub.2 SO.sub.4, HCl and HNO.sub.3. HNO.sub.3, however, provides a disadvantage of not providing selectivity relative to silicon during the etch. Accordingly where silicon is or will be exposed by etch of the doped oxide, HNO.sub.3 would typically not be an acid of choice. Example other preferred mineral acids include H.sub.3 PO.sub.4, HBr, HI, HClO.sub.4, and HIO.sub.4, or mixtures thereof.

The preferred volumetric ratio of other mineral acids in the acid solution to HF in the acid solution is from 20:1 to 110:1, with 45:1 to 65:1 being most preferred. The invention was reduced to practice utilizing a ratio of 55:1. For ratios toward the 110:1 point, selectivity is expected to be high, while etch rate is expected to be low. At a ratios toward the 20:1 point, etch rate is expected to be high, while selectivity will be reduced.

The preferred solution temperatures for etching are expected to fall between 20.degree. C. and 50.degree. C., with about 35.degree. C. being most preferred. Lower bath temperatures are expected to provide better selectivity, and a slower etch rate, while higher bath temperatures are expected to provide poorer selectivity and a higher etch rate.

An example etch solution with which the invention was reduced to practice comprised 840 ml H.sub.2 SO.sub.4, 960 ml H.sub.2 O, 30 ml HF, and 60 ml acetic acid. The H.sub.2 SO.sub.4 solution was comprised of 97% H.sub.2 SO.sub.4. The HF solution comprised 49% by volume HF in H.sub.2 O. This thus provided in the etching solution a volumetric ratio of H.sub.2 SO.sub.4 :HF of 55:1. Acetic acid is a known prior art component in wet acid etching which provides bath stabilization and extends bath life. Such does not constitute a part of this invention, nor is it necessary in the invention. Bath temperature was maintained at 35.degree. C. during etching. Such chemistry was determined to etch borophosphosilicate glass (six weight percent phosphorus, three weight percent boron) at a rate of 108 Angstroms per second, while etching densified TEOS at a rate of 17 Angstroms per second, thus providing a selectivity ratio of 6.3 to 1. Corresponding etch rates were determined utilizing HCl and HNO.sub.3 in place of H.sub.2 SO.sub.4.

An example implementation utilizing the above described technology is shown and described with reference to FIGS. 1-4 for formation of cell capacitor storage nodes. FIG. 1 illustrates a semiconductor wafer fragment 10 having a pair of word lines 12, 14 and a field oxide region 16 provided over a bulk substrate 18. Field oxide 16 would comprise undoped SiO.sub.2. Word lines 12, 14 are as well shown surrounded by undoped SiO.sub.2, provided in the form of spacers 20 and caps 22. Such would typically be deposited by decomposition of TEOS, followed by well known densification techniques.

Referring to FIG. 2, a layer 24 of BPSG is applied.

Referring to FIG. 3, a layer 26 of photoresist is applied, patterned and a dry etch conducted through BPSG layer 24 to open a desired capacitor contact 28 to an active area (not shown) in substrate 18.

Referring to FIG. 4, the wafer would then be dipped in a wet acid solution in accordance with the invention, with photoresist 26 still in place, to effect an isotropic etch of the BPSG layer. Such which will be selective to the undoped TEOS SiO.sub.2 and field oxide, and photoresist. Thereafter, the photoresist layer is removed, producing the FIG. 4 construction. The illustrated and enlarged cavity 30 which is produced can be utilized for a cell storage node capacitor.

In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.