US 5,295,092 AGrant
Semiconductor Read Only Memory
Issue Date:1994-03-15
•3 Claims
•6 Drawing Sheets
Abstract
A semiconductor read only memory of this invention includes a plurality of word lines disposed in parallel. The read only memory has a plurality of units. Each of the plurality of units includes: a first bit line which crosses the word lines; a plurality of first virtual ground lines disposed substantially in parallel with the first bit line, each of the plurality of first virtual ground lines having a first end and a second end; a plurality of second virtual ground lines corresponding to the plurality of first virtual ground line, each of the plurality of second virtual ground lines having a first end and a second end; second bit lines, each provided between two adjacent ones of the plurality of second virtual ground lines, each of the second bit lines having a first end and a second end; memory cell columns, each constituted by a plurality of memory cells connected in parallel between one of the second virtual ground lines and one of the second bit lines adjacent thereto; and bank select switching elements for selecting one of the memory cell columns. In the read only memory, the second ends of the plurality of first virtual ground lines are respectively connected to the second ends of the second virtual ground lines, and the first ends of the second bit lines are respectively connected to the bank select switching elements.
Metadata
Assignee
- Sharp Kabushiki Kaisha
Inventor
- Yasuhiro Hotta
Application Information
Application Number:US 0071978
Filing Date:1993-01-21
Priority Date:1992-01-21
Art Unit:251
Classifications
IPC:
G11C 1300G11C 1140
Field of Search:
36551;182;94;104
Patent Drawings (6 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a semiconductor read only memory, and more particularly to a semiconductor read only memory in which MOSFETs constituting memory cells are connected in parallel.
2. Description of the Related Art
FIG. 4 shows an equivalent circuit of a semiconductor read only memory (hereinafter, sometimes referred to simply as "a ROM") which is conventionally and widely used. This ROM is a lateral ROM constructed in such a manner that memory cells 3 of MOSFETs are connected in parallel with respect to a plurality of bit lines 2 which cross word lines 1. Conventionally, each of the bit lines 2 is made of metal (hereinafter, referred to as a metal bit line). Alternatively, a diffused layer may function as a bit line (hereinafter, referred to as a diffusion bit line).
In order to dispose memory cells more densely, a hierarchical system (hereinafter, referred to as a hierarchical bit line system) has been proposed (Japanese Patent Application No. 63-75300), as is shown in FIG. 5. In the system, main bit lines Mb.sub.l, Mb.sub.l+1, . . . , etc. and sub-bit lines Sbm.sub.2l, Sbm.sub.2l+1, . . . , etc. are hierarchically provided In the hierarchical bit line system, each of the memory cells Mm.sub.21.n is connected between two adjacent sub-bit lines Sbm.sub.21 and Sbm.sub.2l-1. The plurality of memory cells Mm.sub.2l.k (1.ltoreq.k.ltoreq.n) of each row are connected to a common word line WL.sub.k. The memory cells Mm.sub.21.n are alternately assigned into two groups of odd-numbered banks such as Bm.sub.2l-1 and even-numbered banks such as Bm.sub.2l. For the selection of these banks, bank select MOSFETs Q0.sub.m.21, QE.sub.m.2l, . . . , etc. are provided on both ends of the sub-bit lines, respectively. Bank select lines B0.sub.m and BE.sub.m are connected to these bank select MOSFETs, respectively. The main bit lines Mb.sub.l, Mb.sub.l+1, . . . , etc. are connected to sense amplifiers such as SA.sub.l, or connected to GND via MOSFETs such as Q.sub.l+1.
In the ROM with the hierarchical bit line system, the wired pitch of the main bit lines can be made double as compared with the conventional lateral ROM shown in FIG. 4. The ROM with the hierarchical bit line system can advantageously reduce the parasitic capacitance on bit lines, and especially when the diffusion bit lines are used, the wiring resistance on bit lines can be greatly reduced
However, when the diffusion bit lines are used in the hierarchical bit line system shown in FIG. 5, there arises a problem in that the diffusion resistance greatly varies depending on the position of a memory cell in a bank, which is described below, so that the value of discharge current for the read of information greatly varies depending on the position of the memory cell.
There is another problem in that since the value of the diffusion resistance is large and hence the value of the discharge current is small, such a ROM is not suitable for a high-speed read operation.
For example, a case where information is read out from a memory cell Mm.sub.2l-1.1 by setting the bank select line B0.sub.m High, the other bank select line BE.sub.m Low, and the word line WL.sub.1 High is considered. In this case, a control signal VG for a transistor Q.sub.1 (not shown) connected to the main bit line Mb.sub.l is made Low. A control signal VG for a transistor Q.sub.l-1 connected to the adjacent main bit line Mb.sub.l-1 is made High. As a result, the main bit line Mb.sub.l-1 is connected to the GND. The circuit in the above-mentioned state is shown in FIG. 6. A discharge current i flows through a path formed by the main bit line Mb.sub.l, the bank select MOSFET Q0.sub.m.2l-1, the sub-bit line Sb.sub.m2l-1 the memory cell Mm.sub.2l-1.1, the sub-bit line Sb.sub.m2l-2, a bank select MOSFET Q0.sub.m.2l-2, and the main bit line Mb.sub.l-1, in this order. The total value of diffusion resistance of the sub-bit lines Sbm.sub.2l-1 and Sbm.sub.21-2 in this path is 2r, where r indicates the diffusion resistance between respective two memory cells. The total diffusion resistance value varies depending on the position of the selected memory cell, and the possible largest value of the total diffusion resistance is 2nr.
As described above, in the ROM shown in FIG. 5, the value of diffusion resistance greatly varies depending on the position of a memory cell from which information is read out. Moreover, the discharge current flows through three transistors, so that the ROM shown in FIG. 5 has a poor discharge ability as compared with a system without bank select MOSFETs (in such a system, the discharge current flows through only one transistor).
Summary of the Invention
The semiconductor read only memory of this invention includes a plurality of word lines disposed in parallel. The semiconductor read only memory has a plurality of units. Each of the plurality of units includes: a first bit line which crosses the word lines; a plurality of first virtual ground lines disposed substantially in parallel with the first bit line, each of the plurality of first virtual ground lines having a first end and a second end; a plurality of second virtual ground lines corresponding to the plurality of first virtual ground line, each of the plurality of second virtual ground lines having a first end and a second end; second bit lines, each provided between two adjacent ones of the plurality of second virtual ground lines, each of the second bit lines having a first end and a second end; memory cell columns, each constituted by a plurality of memory cells connected in parallel between one of the second virtual ground lines and one of the second bit lines adjacent thereto; and bank select switching elements for selecting one of the memory cell columns, wherein the second ends of the plurality of first virtual ground lines are respectively connected to the second ends of the second virtual ground lines, and the first ends of the second bit lines are respectively connected to the bank select switching elements.
In one embodiment of the present invention, the bank select switching elements may be MOSFETs.
In another embodiment of the present invention, memory cells may be MOSFETs.
Thus, the invention described herein makes possible the advantage of providing a ROM capable of reading at a high speed while provided with memory cells densely disposed.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.
Brief Description of the Drawings
FIG. 1 is a circuit diagram showing part of a ROM in one example of the present invention.
FIG. 2 shows a layout of an example having diffusion bit lines according to the present invention.
FIG. 3 is a circuit diagram schematically showing the current flow when information is read out from a memory cell in the example according to the present invention.
FIG. 4 is a circuit diagram showing a prior art ROM.
FIG. 5 is a circuit diagram showing a prior art ROM with a hierarchical bit line system.
FIG. 6 is a circuit diagram schematically showing the current flow when information is read out from a memory cell in the prior art ROM shown in Figure 5.
Description of the Preferred Embodiments
FIG. 1 shows part of a ROM in one example of the present invention. FIG. 2 shows a pattern on the surface of a semiconductor substrate in this example. The ROM of this example basically adopts a hierarchical bit line system. The bit lines are constituted by sub-bit lines SB.sub.1, SB.sub.2, . . . , etc., and main bit lines MB.sub.1, MB.sub.2, . . . , etc. Impurity diffused layers (hereinafter, referred to as "diffused layers") formed in a silicon substrate function as the sub-bit lines. Metal (aluminum) interconnections which are disposed on an interlevel insulating film (not shown) formed on the silicon substrate function as the main bit lines. As compared with the resistance of each of the sub-bit lines SB.sub.1, SB.sub.2, . . . , etc., the resistance of each of the main bit lines MB.sub.1, MB.sub.2, .., etc. can be substantially disregarded. The main bit lines MB.sub.1, MB.sub.2, . . . , etc. are connected to sense amplifiers (not shown in FIGS. 1 and 2), respectively.
To each of the main bit lines (e.g., MB.sub.1), four sub-bit lines (e.g., SB.sub.1, SB.sub.2, SB.sub.3, and SB.sub.4) are connected at one of their ends, respectively, via switching elements described below. Virtual sub-ground lines SG.sub.1, SG.sub.2, . . . , etc. of diffused layers are arranged in an alternate manner with the sub-bit lines SB.sub.1, SB.sub.2, . . . , etc. Virtual main ground lines MG.sub.1, MG.sub.2, . . . , etc. with metal (aluminum) interconnections are provided on the interlevel insulating film (not shown) The virtual sub-ground lines SG.sub.1, SG.sub.2, . . . , etc. are directly connected to the virtual main ground lines MG.sub.1, MG.sub.2, . . . , etc., respectively, via contact holes CG (FIG. 2) formed in the interlevel insulating film.
As is shown in FIG. 2, the memory cells used in this example are MOSFETs (memory cell transistors). Portions of the diffused layers functioning as the sub-bit lines SB.sub.1, SB.sub.2, . . . , etc. and the virtual sub-ground lines SG.sub.1, SG.sub.2, . . . , etc. also function as source/drain regions of the memory cell transistors. More specifically, portions of the sub-bit lines SB.sub.1, SB.sub.2, . . . , etc. also function as the drain regions of the memory cell transistors. Portions of the virtual sub-ground lines SG.sub.1, SG.sub.2, . . . , etc. also function as the source regions of the memory cell transistors. The word lines WL.sub.il -WL.sub.in which cross the sub-bit lines SB.sub.1, SB.sub.2, . . . , etc. and the virtual sub-ground lines SG.sub.1, SG.sub.2, . . . , etc. are used as the gate electrodes of the memory cell transistors. For example, the gate electrodes of a plurality of memory cells which belong to a row k (1.ltoreq.k.ltoreq.n) are part of the common word line WL.sub.ik.
On one side of the sub-bit lines SB.sub.1, SB.sub.2, SB.sub.3, and SB.sub.4, bank select MOSFETs BS0.sub.1, BS0.sub.2, BS0.sub.3, and BS0.sub.4 are connected thereto, respectively. More specifically, as is shown in FIG. 2, in each of the bank select MOSFETs BS0.sub.1, BS0.sub.2, BS0.sub.3, and BS0.sub.4, one end of the corresponding one of the sub-bit lines SB.sub.1, SB.sub.2, SB.sub.3, and SB.sub.4 functions as one of the source and drain regions thereof, and a diffused region DB.sub.1 where the sub-bit lines SB.sub.1, SB.sub.2, SB.sub.3, and SB.sub.4 are connected to the main bit line MB.sub.1 functions as the other one of the source and drain regions thereof. Bank select lines BSELi.sub.01, BSELi.sub.23, BSELi.sub.45, and BSELi.sub.67 also function as the gate electrodes of the bank select MOSFETs BS0.sub.1, BS0.sub.2, BS0.sub.3, and BS0.sub.4.
On the other side of the sub-bit lines SB.sub.1, SB.sub.2, SB.sub.3, and SB.sub.4, no elements such as bank select MOSFETs are provided.
In the ROM having the above-mentioned structure, a case where information is read out from a memory cell Mm.sub.2k (1.ltoreq.k.ltoreq.n) which is connected to the word line WL.sub.ik, the sub-bit line SB.sub.2, and the virtual sub-ground line SG.sub.2 is considered. In this case, the bank select line BSELi.sub.23 is set High, and the other bank select lines BSELi.sub.01, BSELi.sub.45, and BSELi.sub.67 are set Low. The word line WL.sub.ik which is connected to the memory cell Mm.sub.2k to be selected is set High, and the virtual sub-ground line SG.sub.2 which is connected to the source region of the MOSFET of the memory cell Mm.sub.2k is connected to the ground.
A discharge current i in this case flows in such a manner as is shown in FIG. 3. The discharge current i flows through a path formed by the main bit line MB.sub.1, the bank select MOSFET BS0.sub.2, the sub-bit line SB.sub.2, the memory cell Mm.sub.2k, the virtual sub-ground line SG.sub.2, and the virtual main ground line MG.sub.2, in this order. The discharge current i finally reaches the ground. When diffusion resistances of the sub-bit line SB.sub.2 and the virtual sub-ground line SG.sub.2 are respectively denoted as R1 and R2, the total resistance value in this case is expressed by R1+R2. The diffusion resistances R1 and R2 are represented by kr and (n-k)r, respectively, where r indicates the diffusion resistance between memory cells. Therefore, the total diffusion resistance is a constant of nr, independent of the position of the selected memory cell.
As described above, the total diffusion resistance of the sub-bit lines and the virtual subground lines through which the discharge current flows is always constant independent of the position of the memory cell from which information is to be read out. Accordingly, if the position of the selected memory cell is changed, the value of the discharge current i is always constant.
In order to perform a stable read operation at a high speed, a difference in discharge current value between two binary states of the selected memory cell should be made larger. Specifically, in a 0 state, the selected memory cell is in an on state. In a 1 state, the selected memory cell is in an off state, i.e., in a normally off state. Accordingly, it becomes possible to operate stably at a high speed by increasing the value of the discharge current in the 0 state.
In the conventional ROM with the hierarchical bit line system, as is shown in FIG. 6, the value of the discharge current is determined by the conductive resistance of the selected memory cell, the conductive resistances of the two bank select MOSFETs QO.sub.m.2l-2 and QO.sub.m.2l-1, and the diffusion resistances of the sub-bit lines Sb.sub.m2l-1 and Sbm.sub.2l-2 (as described above, since the largest diffusion resistance value of each sub-bit line is nr, the total diffusion resistance of the subbit lines becomes 2nr).
On the other hand, in the ROM of this example, the value of the discharge current i is determined by the conductive resistance of the selected memory cell, the conductive resistance of the single bank select MOSFET BS0.sub.2, and the diffusion resistances of the sub-bit line SB.sub.2 and the virtual sub-ground line SG.sub.2 (the total diffusion resistance of R1+R2 corresponds to nr). The total diffusion resistance of the sub-bit line SB.sub.2 and the virtual sub-ground line SG.sub.2 can be nr which is half of the largest value 2nr of the total diffusion resistance in the conventional ROM with the hierarchical bit line system. As a result, the value of the discharge current i can be made larger.
Since the discharge current i flows through only two transistors (i.e., the bank select MOSFET and the memory cell), the total conductive resistance can be reduced by a conductive resistance of one bank select MOSFET as compared with the conventional ROM with a hierarchical bit line system. As a result, the value of the discharge current can be made much larger, and a high-speed read can be realized. Moreover, as the result that the discharge current becomes larger and the S/N ratio becomes larger, the operation margin can be broader, thereby attaining a stable operation.
In the above example, the case of the mask ROM is described. Alternatively, the present invention can be applied to another type of semiconductor read only memory in which a plurality of memory cells are arranged in a matrix, such as an EPROM, or an E.sup.2 PROM.
Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed.
Claims
What is claimed is:
1. A semiconductor read only memory including a plurality of word lines disposed in parallel, said read only memory having a plurality of units, each of said plurality of units comprising: a first bit line which crosses said word lines; a plurality of first virtual ground lines disposed substantially in parallel with said first bit line, each of said plurality of first virtual ground lines having a first end and a second end; a plurality of second virtual ground lines corresponding to said plurality of first virtual ground line, each of said plurality of second virtual ground lines having a first end and a second end; second bit lines, each provided between two adjacent ones of said plurality of second virtual ground lines, each of said second bit lines having a first end and a second end; memory cell columns, each constituted by a plurality of memory cells connected in parallel between one of said second virtual ground lines and one of said second bit lines adjacent thereto; and bank select switching elements for selecting one of said memory cell columns, wherein said second ends of said plurality of first virtual ground lines are respectively connected to said second ends of said second virtual ground lines, and said first ends of said second bit lines are respectively connected to said bank select switching elements.
2. A semiconductor read only memory according to claim 1, wherein said bank select switching elements are MOSFETs.
3. A semiconductor read only memory according to claim 1, wherein said memory cells are MOSFETs.
Patent Citations (2)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5031139 | 1991-07-01 | Sinclair | |
| JPX3-179775 | 1991-08-01 |
Non-Patent Literature (2)
- Ser. No. 07/781,630 to Yasuhiro Hotta dated Oct. 22, 1991.
- Okada, M., et al., "16Mb ROM Design Using Bank Select Architecture", 1988 Symposium On VLSI Circuits, Digest of Technical Papers, Aug. 22-25, 1988, Tokyo, pp. 85-86.