US 5,287,525 AGrant
Software Controlled Power Shutdown in an Integrated Circuit
Issue Date:1994-02-15
•4 Claims
•2 Drawing Sheets
Abstract
Power shutdown of an integrated circuit such as a data acquisition system is implemented by software command. In one embodiment of a data acquisition system, an 8 bit data input word for configuring the operation of the data acquisition system includes two word length bits which define the length of data output words. One combination of the word length bits is utilized to command power shutdown. A decoder within the integrated circuit identifies the power shutdown command and generates a power shutdown signal (PS) to minimize power consumption when the circuit is not in operation.
Metadata
Assignee
- Linear Technology Corporation
Inventors
- Sammy S. Lum
- William C. Rempfer
Application Information
Application Number:US 0104779
Filing Date:1993-01-28
Priority Date:1989-11-29
Art Unit:238
Classifications
IPC:
G06F 100G06F 132
Field of Search:
395364365371750;575707226;22766
Patent Drawings (2 sheets)
Description
Background of the Invention
This invention relates generally to the control of power in an electronic integrated circuit such as a data acquisition system (DAS), and more particularly the invention is directed to control of power without the need for a dedicated circuit pin.
A data acquisition system such as the Linear Technology Corporation LTC1290 single chip data acquisition system contains a serial I/O successive approximation A/D converter. The device uses switch capacitor technology to perform either 12 bit unipolar or 11 bit plus sign bipolar A/D conversions. An 8 channel input multiplexer can be configured for either single ended or differential inputs, or combinations thereof. An on-chip sample and hold is included for all single ended input channels. When the circuit is idle, it can be powered down in applications where low power consumption is desired.
The circuit is packaged in a 20 lead ceramic DIP. Heretofore, control of power shutdown in such electronic circuits have required a dedicated package pin. Alternatively, external control has been used by actually disconnecting the power source from the circuit.
The present invention is directed to controlling and implementing a power shutdown from within the circuit but without the need for a dedicated pin.
Summary of the Invention
An object of the invention is control of power shutdown within an integrated circuit without the use of dedicated package pins.
A feature of the invention is the use of software to control power down in an integrated circuit.
Briefly, selected bits in an input data word are utilized to control power shutdown. In a data acquisition system such as the LTC1290, an input data word is used to configure the circuit as to MUX address, mode of operation, and word length. The two bits used for word length establish the output word length as 8 bits, 12 bits, or 16 bits. In accordance with the invention the 2 bits also control power shutdown with a decoder in the circuit responding to the 2 bit code generating a power shutdown (PS) signal which inhibits the comparator circuitry of the DAS.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.
Brief Description of the Drawings
FIG. 1 and FIG. 2 are functional diagrams of power shutdown control in accordance with prior art.
FIG. 3 is a functional diagram of power shutdown control in accordance with the present invention.
FIG. 4 is a more detailed functional diagram of the power shutdown of FIG. 3.
Description of the Preferred Embodiment
FIG. 1 and FIG. 2 are functional diagrams illustrating power shutdown control of packaged integrated devices such as data acquisition systems in accordance with the prior art. In FIG. 1 the packaged DAS is provided with a pin labeled PS which receives an external signal for controlling power shutdown. As noted above, the use of a dedicated pin in a packaged circuit is undesirable due to the limited number of pins available for power, control, and data inputs. In FIG. 2, the control of power shutdown is effected by selectively connecting and disconnecting an external power supply to the power input terminal V+. However, this generally requires additional external hardware and circuitry.
FIG. 3 is a functional diagram of software controlled power shutdown in accordance with the present invention. In an integrated circuit such as the LTC1290 data acquisition system, an input data word is clocked into the DAS to configure the circuit for operation (e.g. channel selection, unipolar versus bipolar, and word length). A dedicated bit combination is used to place the DAS in power shutdown where the circuit can run at a greatly reduced power supply thus minimizing power drain on batteries. Importantly, a separate dedicated pin is not required, and external hardware is obviated.
FIG. 4 is a more detailed functional diagram of the circuitry of FIG. 3 for the LTC1290 DAS. The 8 bit data word is clocked into the DIN input after a chip select signal is recognized by the circuitry. The first four bits of the input word assign the MUX configuration for the requested conversion. The first bit, SGL/DIFF, determines a differential mode or a single ended mode, and the odd/sign (O/S) bit along with the select one (S1) and select two (S2) bits complete the MUX address. The unipolar/bipolar (UNI) bit determines whether a conversion will be unipolar or bipolar, and the MSBF bit establishes MSB first or LSB first sequence of output data. The WL1 and WL0 word length bits determine the output word length and also are utilized for power shutdown in accordance with the following table:
The input data word is clocked into the input shift register 20 and then applied to a decoder 22. The input word is decoded and a power shutdown (PS) signal is generated as shown in the above table. The PS signal is applied to N channel transistors MN1, MN2, and MN3 in an auto zeroing comparator shown generally at 24. The PS signal goes high and switches S1-S3 are opened thereby forcing all of the outputs of the inverters high. When the switches S1-S3 are closed, the supply current is maximum. With the inverter outputs forced high there is no current drain. Accordingly, during normal operation the PS signal remains low and is reset by the chip select bar (CS) after power shutdown has been select requested.
The use of a software word to control power shutdown in an integrated circuit such as a data acquisition system eliminates the need of a dedicated pin and obviates the need of external hardware. While the present invention has been described with reference to a specific embodiment, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A method for providing an internal power shutdown signal in an integrated circuit in response to a multi-bit circuit configuration word received by said integrated circuit, said integrated circuit being enabled to receive said configuration word upon receipt of a chip select signal, wherein said circuit configuration work includes at least one configuration bit used by said integrated circuit to configure said integrated circuit for operation, said method comprising the steps of: (a) serially clocking said circuit configuration word into said integrated circuit, said circuit configuration word including at least one word length bit for defining lengths of output words produced by said integrated circuit; (b) decoding said at least one configuration bit of said circuit configuration word into a first data value and configuring said integrated circuit into an operative mode in accordance with said first data value and said chip select signal; (c) decoding said at least one word length bit of said configuration word into a second data value and comparing said second data value with a predefined value representative of a power shutdown command; (d) generating a power shutdown signal on the basis of said comparison of said second data value with said predefined power shutdown command, said power shutdown signal being reset by the chip select signal received by said integrated circuit; and (e) shutting down power in response to generation of said power shutdown signal.
2. The method as defined by claim 1 wherein said integrated circuit is a data acquisition system, said circuit configuration word is an 8 bit input data word.
3. An apparatus for providing an internal signal for power shutdown in an integrated circuit which receives a multi-bit circuit configuration word, said integrated circuit being enabled to receive said configuration word upon receipt of a chip select signal, wherein said circuit configuration word includes at least one configuration bit used by said integrated circuit to configure said integrated circuit for operation, comprising: means for clocking said circuit configuration word into said integrated circuit, said circuit configuration word including at least one word length bit for defining lengths of output words produced by said integrated circuit; means for decoding said at least one configuration bit and said at least one word length bit of said circuit configuration word into first and second data values, respectively, and for comparing said second data value with a predefined value representative of a power shutdown command; means for configuring said integrated circuit into an operative mode in accordance with said first data value and said chip select signal; and means for generating a power shutdown signal for said integrated circuit on the basis of said comparison of said second data value with said predefined value representative of a power shutdown command wherein said power shutdown signal is reset by the chip select signal received by said decoding means.
4. Apparatus as defined by claim 3 wherein said integrated circuit is a data acquisition system.
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