Circuit for Measuring Current in a Power MOS Transistor

The present invention relates to measurement of current in a power transistor, and more particularly in a power MOS transistor, constituted by a plurality of parallel elementary cells.

FIG. 1 shows one of the most conventional circuits for measuring current in a power transistor MO. This circuit consists in arranging a measurement resistor R.sub.S between the power transistor terminal connected to voltage V.sub.S (the source) and the reference potential. The other terminal of the power transistor is connected to a high voltage through a load R.sub.L wherein flows a current I.sub.L, identical in that case to the current in the power transistor. The measurement of voltage V.sub.S across resistor R.sub.S gives an indication of the current value.

This circuit exhibits several drawbacks.

The first drawback lies in the fact that resistor R.sub.S is constantly in series with the power MOS transistor and causes an increase in the dissipated power which is not negligible since resistor R.sub.S must have a sufficient value so that the voltage across its terminals is detectable.

Another drawback of this circuit is that resistor R.sub.S is liable to vary with temperature or differ from one manufacturing batch to another in a way independent of the possible variations of the power MOS transistor characteristics. As a result, one obtains an inaccurate determination of its value and therefore of the current being measured.

In order to avoid the first drawback, prior art circuits such as the one illustrated by FIG. 2 have been used. In this figure, the power MOS transistor M0 is shown The upper terminal (drain) of transistor M0 is connected to a positive supply terminal through the load R.sub.L, the supply of which is to be controlled. The series connection of a transistor M1 and a resistor R.sub.S is arranged in parallel with the power transistor M0, the gates of transistors M0 and M1 being interconnected to voltage V.sub.GS. It is clear that the first drawback is avoided, but the second drawback, that is, the possible fluctuations of resistor R.sub.S independent of the fluctuations of the other circuit elements is not eliminated.

Thus, the invention provides a process for measuring current in a power transistor which permits removal of the possible variations resulting from temperature or differences in the manufacturing process between resistor characteristics and MOS transistor characteristics.

To achieve this object and others, the invention provides a circuit for measuring current in a power MOS transistor. The circuit comprises second and third transistors in series with each other, being of the same type and same technology but having a smaller surface than the power transistor and arranged in parallel with the latter, these two series transistors having their gates connected to the gate of the power transistor, and means for measuring current in the transistor connected to the reference electrode source of the power transistor.

According to another embodiment of the invention, the current measuring means comprise a fourth MOS transistor connected as a current mirror with the third one.

According to a further embodiment of the invention, the drain of the third MOS transistor is connected to the noninverting input of an operational amplifier, the inverting input of which is connected to the drain of the fourth MOS transistor, the gate of which is connected to the gate of the third MOS transistor, the output of the operational amplifier being connected to the gate of a fifth transistor connected in series with the fourth transistor across the terminals of a supply source, the lower terminal of the fourth transistor being connected to the reference potential.

The foregoing and other objects, features and advantages of the invention will be apparent from the following detailed description of a preferred embodiment as illustrated in the accompanying drawings wherein:

FIGS. 1 and 2, already described, illustrate the prior art; and

FIG. 3 schematically shows a circuit according to the invention.

In the various figures, same reference labels designate identical or analogous elements.

In the circuit of FIG. 3, two series connected transistors M1 and M2 are arranged in parallel on with transistor M0. The gates of transistors M0, M1 and M2 are interconnected. The drains of transistors M0 and M1 are connected as well as the sources of transistors M0 and M2 which are set to the reference voltage potential, for example the ground.

Transistors M1 and M2 are of the same type as the power transistor M0. If transistor M0 is a power transistor of the multicell DMOS-type, transistors M1 and M2 are constituted by a small number of cells identical to the cells constituting transistor M0. In a practical example, transistor M0 may include 3,600 cells, transistor M1, 7 cells, and transistor M2, 14 cells.

If the voltage V.sub.GS is considered to be sufficiently high so that each transistor operates in its linear region, all these transistors will have resistances in the ON state strictly proportional to their number of cells when gate/source voltages are identical. It is be noted that the gate/source voltage of transistor M1 is slightly lower than the gate/source voltage of the other transistors since the source of transistor M1 is at a higher voltage than the sources of the other transistors. The source of transistor M1, instead of being directly connected to the reference voltage (the ground), is connected to the drain of transistor M2 and thence to ground. Thus, the gate/source voltage of transistor M1 is in fact V.sub.GS (M0) minus the drain/source voltage drop across the terminals of transistor M2. However, this voltage drop is in practice about a few hundreds millivolts whereas the voltage V.sub.GS is chosen to be about 10 volts. Therefore, one can consider that the proportionality between the values of internal resistances in the conductive state of MOS transistors and their number of cells is a valid approximation for this circuit. In all cases, simulations made by users have shown that this result was obtained with an error lower than 5% and remained within this range whatever the variations in temperature and manufacturing technology may be, since the three transistors M0, M1 and M2 similarly vary with variations in temperature and technology.

It is possible to use the above described circuit for detecting if voltage V.sub.S exceeds a determined threshold corresponding for example to a load shorting. This voltage V.sub.S will be simply compared with a reference voltage through a comparator.

It is also possible to use this circuit for measuring current. For this purpose, an additional circuit will preferably be used such as shown in the righthand portion of FIG. 3 and comprising an operational amplifier OA and additional MOS transistors M3 and M4.

The amplifier OA receives on its non-inverting input the voltage to be measured, namely the drain voltage of transistor M2. The inverting input of the operational amplifier OA is connected to the reference voltage through an additional MOS transistor M3 of the same type as transistors M0, M1 and M2. The output of amplifier OA is connected to the gate of a MOS transistor M4, the drain of which is connected to a supply voltage VCC and the source is connected to the inverting input of amplifier OA.

With this circuit, the voltage on the inverting input tends to become equal to the voltage on the non-inverting input and therefore the current in transistor M3 (which will also be the current flowing through transistor M4) is equal to the current flowing through transistor M2 if these two transistors are identical. These currents are proportional to the number of cells constituting these transistors if the latter are distinct. The measurement current I.sub.M flowing through transistors M4 and M3 is:

where R0-R3 designate the resistances in the ON state of transistors M0-M3.

Thus, the ratio between the measurement current and the current in the power transistor only depends upon the ratio of the ON-resistances of the respective transistors constituted by identical cells. Therefore, this ratio is constant and substantially equal to the ratio of the number of cells constituting each transistor.

The invention encompasses all practical variants and modifications which will appear to those skilled in the art. Also, the circuit according to the present invention can be combined with other conventional circuits, for example circuits designed to cancel offset of the operational amplifier OA.