Photoelectric Converting Apparatus Having an Analog Memory

1. Field of the Invention

The present invention relates to a photoelectric converting apparatus and, more particularly, to a photoelectric converting apparatus in which a first signal output from a photoelectric conversion unit is stored and the first signal is output in correspondence to a second signal which is output from the photoelectric conversion unit.

2. Related Background Art

In recent years, a video camera using a solid-state image pickup device as an image input device has widely been used. It is considered that this is because the solid-state image pickup device has largely contributed to the realization of the small size, light weight, and low costs of the video camera. Although almost all of the video cameras for public use require color images, the solid-state image pickup device of a single plate is a main stream from viewpoints of the realization of small size, light weight, and low costs. In the case of obtaining a color image by using the single plate type solid state image pickup device, in many cases, a chrominance signal is obtained by adhering mosaic color filters to the solid-state image pickup device. In the case of obtaining an image signal by using such color filters, when considering only the signal of one horizontal line, all of the chrominance signals do not always exist. Therefore, color information which does not exist on the horizontal line is obtained from the horizontal line which is one line before.

FIG. 1 is a schematic constructional diagram showing an example of a construction of a conventional solid-state image pickup device.

As shown in the diagram, by inputting R/B outputs OR/OB of a solid-state image pickup device 7 to a delay element 8, a signal which is one horizontal period before a branch point a on the inputting side is always output to a branch point b on the outputting side of the delay element 8. Therefore, by switching means 10 and 11, signals of R, G, and B are always obtained.

There is also a configuration where a CCD type is mainly used as a delay element 8 and the delay element 8 is formed together with the solid-state image pickup device 7 onto the same chip.

However, in the above conventional solid-state image pickup device, when a CCD type delay element is used as a delay element, if a sensor unit is constructed by an element other than the CCD type, the manufacturing method becomes complicated, resulting in increase in costs. On the other hand, in the case of the CCD type, since the random access cannot be executed, there is a problem such that outputs of the delay elements cannot help being extracted in accordance with the serial inputting order.

It is an object of the present invention to provide a photoelectric converting apparatus which is suitably used for the above solid-state image pickup device.

According to a preferred embodiment of the invention, a photoelectric converting apparatus comprises a photoelectric conversion unit, switching means, capacitor means, and an analog memory which can be accessed at random and stores a first signal from the photoelectric conversion unit, wherein the first signal is output from the analog memory in correspondence to a second signal which is output from the photoelectric conversion unit.

Therefore, the switching means and the capacitor means are provided on the outputting side of the photoelectric conversion unit, the analog memory which can be accessed at random is connected to the outputting side of the photoelectric conversion unit, the first signal which is output from the photoelectric conversion unit is stored into the analog memory, and the stored first signal is output from the analog memory at a desired timing (for instance, simultaneously) in correspondence to a second signal which is output from the photoelectric conversion unit.

By using the analog memory, the photoelectric conversion unit and the analog memory can be also formed onto the same semiconductor substrate. For instance, if the photoelectric conversion unit and the analog memory are constructed by MOS type transistors or the like, they can be formed by the same process. Therefore, the apparatus can be easily manufactured and the apparatus in which the photoelectric conversion unit and the analog memory have the same characteristics can be obtained.

FIG. 1 is a schematic diagram showing an example of a construction of a conventional solid-state image pickup device;

FIG. 2A is a schematic circuit constructional diagram of the first embodiment of a photoelectric converting apparatus according to the invention;

FIG. 2B is a timing chart for explaining the operation of the photoelectric converting apparatus;

FIG. 3 is an explanatory diagram showing a construction of pixels of the photoelectric conversion unit;

FIG. 4 is a schematic constructional diagram of the second embodiment of a photoelectric converting apparatus of the invention;

FIG. 5 is a schematic circuit constructional diagram of the third embodiment of a photoelectric converting apparatus of the invention;

FIG. 6 is a timing chart for explaining the operation of the photoelectric converting apparatus of the third embodiment; and

FIG. 7 is a schematic constructional diagram of a solid-state image pickup device to which the invention is applied.

An embodiment of the present invention will be described in detail hereinbelow with reference to the drawings.

FIG. 2A is a schematic circuit contructional diagram of the first embodiment of a photoelectric converting apparatus of the invention.

In the diagram, reference numeral 1 denotes a photoelectric conversion unit to output an electric signal corresponding to the incident light. The unit 1 includes a plurality of photoelectric convertion elements. Reference numeral 2 indicates a shift register to drive the photoelectric conversion unit 1 and an analog memory 3. H.sub.O to H.sub.N represent output lines of the shift register; Analog memory 3 comprises a switch and a capacitor. A signal output line L.sub.1 of the photoelectric conversion unit 1 and a memory output line L.sub.2 of the analog memory 3 are also provided.

In the analog memory 3, C.sub.1 to C.sub.N denote the accumulation capacitors each for temporarily holding and storing a signal which is output to the signal output line L.sub.1. T.sub.11 to T.sub.1N denote switches such as MOS transistor or the like for turning on/off the signal output line L.sub.1 and the accumulation capacitors C.sub.1 to C.sub.N by output pulses O.sub.1 to O.sub.N which are output to the outputted lines H.sub.1 to H.sub.N of the shift register 2. L.sub.3 and L.sub.4 indicate memory output lines to output memory outputs; T.sub.21 and T.sub.2N denote switches such as MOS transistors or the like to turn on/off the accumulation capacitor C.sub.1 to C.sub.N and the memory output lines L.sub.3 and L.sub.4 by the output pulses MO.sub.0 to MO.sub.N-1 which are output from the output lines H.sub.0 to H.sub.N-1 of the shift register 2; T.sub.3 and T.sub.4 sample and hold MOS transistors to sample and hold the signals on the memory output lines L.sub.3 to L.sub.4 ; .phi..sub.3 and .phi..sub.4 gate pulses to control the turn on/off operations of the sample and hold MOS transistors T.sub.3 and T.sub.4 ; T.sub.1 and T.sub.2 resetting MOS transistors to reset the memory output lines L.sub.3 and L.sub.4 ; .phi..sub.1 and .phi..sub.2 gate pulse to control the on/off operation of the resetting MOS transistors T.sub.1 and T.sub.2.

The operation of the photoelectric converting apparatus will now be described hereinbelow with reference to FIGS. 2B and 3.

FIG. 2B is a timing chart for explaining the operation of the photoelectric converting apparatus.

FIG. 3 is an explanatory diagram showing a construction of pixels in the photoelectric conversion unit.

In FIG. 3, reference numerals 41 to 4N and 51 to 5N indicate pixels in one horizontal period.

It is now assumed that after the output signals corresponding to the incident light had been output to the output line L.sub.1 from the pixels 41 to 4N in the photoelectric conversion unit 1, they were held and stored into the accumulation capacitors C.sub.1 to C.sub.N in the analog memory 3.

When the shift register 2 starts operating and the pulse MO.sub.0 is supplied from the output line H.sub.0, the switch T.sub.21 is turned on and a signal O.sub.L3 corresponding to the pixel 41 accumulated in the capacitor C.sub.1 is output to the output line L.sub.3. When the pulse O.sub.1 is then supplied to the output line H.sub.1 and the pulse .phi..sub.3 is supplied to the sample and hold MOS transistor T.sub.3, a signal O.sub.L1 of the pixel 51 is output from the photoelectric conversion unit 1 to the output line L.sub.1, the switch T.sub.11 is turned on, and the signal corresponding to the pixel 51 is accumulated into the capacitor C.sub.1. On the other hand, since the switch T.sub.22 is also turned on, a signal O.sub.L4 corresponding to the pixel 42 accumulated in the capacitor C.sub.2 is output to the output line L.sub.4. Since the sample and hold MOS transistor T.sub.3 is ON, the signal O.sub.L3 corresponding to the pixel 41 which has been output to the output line L.sub.3 is taken out as an output signal O.sub.L2 from the output line L.sub.2.

Transistor T.sub.3 and T.sub.4 define a selecting means for selecting the outputs L.sub.3 or L.sub.4 in accordance with signals .phi.3 and .phi.4, respectively.

Then, when the resetting pulse .phi..sub.1 is supplied, the output line L.sub.3 is reset. After that, when the pulse O.sub.2 is supplied from the shift register 2 to the output line H.sub.2 and the sampling and holding pulse .phi..sub.4 is supplied, the signal O.sub.L1 corresponding to the pixel 52 is output from the output signal line L.sub.1 and the signal corresponding to the pixel 52 is accumulated into the capacitor C.sub.2 through the switch T.sub.12. At this time, the signal O.sub.L3 corresponding to the pixel 43 accumulated in the capacitor C.sub.3 is output to the output line L.sub.3. The signal O.sub.L4 corresponding to the pixel 42 which has been output to the output line L.sub.4 is transmitted through the sample and hold MOS transistor T.sub.4 and is output as an output signal O.sub.L2 to the output line L.sub.2. Then, the resetting pulse .phi..sub.2 is supplied and the output line L.sub.4 is reset. Capacitors C.sub.1, C.sub. 3, . . . C.sub.n-1, which output their signals on L.sub.3 define a first group of capacitors, and capacitors C.sub.2, C.sub.4, . . . C.sub.n, which output their signals on L.sub.4, define a second group of capacitors.

By repeating the operations similar to the above hereinafter, the signals O.sub.L1 and O.sub.L2 which are shifted by one horizontal period are simultaneously continuously output from the output lines L.sub.1 and L.sub.2.

FIG. 4 is a schematic constructional diagram of the second embodiment of a photoelectric converting apparatus of the invention.

The same parts and components as those shown in FIG. 2A are designated by the same reference numerals.

Reference numeral 4 indicates a photoelectric conversion unit to output a signal corresponding to the input image and also simultaneously output an output signal in a state in which no incident light is irradiated. L.sub.5 indicates an output line to output a dark output. After the photoelectric conversion unit 4 generated an output S+N (including a noise signal N) corresponding to image information S to the output line L.sub.1, the unit 4 resets the pixels for one horizontal period and drives so as to output a dark output N. The dark output (noise output) N is delayed by one horizontal period than the image output (signal+noise output) S+N.

At this time, therefore, if the analog memory 3 is driven in a manner similar to the first embodiment, the image output (signal+noise output) S+N which was delayed by one horizontal period is output from the memory output line L.sub.2. Therefore, by executing a subtraction the dark output N from the image output S+N, fixed pattern noises of the photoelectric conversion unit 4 can be eliminated.

FIG. 5 is a schematic circuit constructional diagram of the third embodiment of a photoelectric converting apparatus of the invention.

The same parts and components as those shown in FIG. 2A are designated by the same reference numerals.

In the diagram, reference numeral 5 denotes an analog memory; 6 indicates a memory control pulse generating circuit; and M.sub.1 to M.sub.N memory control pulses.

FIG. 6 is a timing chart for explaining the operation of the photoelectric converting apparatus.

It is now assumed that the photoelectric conversion unit 1 output the output signals corresponding to the incident light from the pixels 41 to 4N of one horizontal period to the output line L.sub.1 and the signals 41 to 4N are simultaneously accumulated into the capacitors C.sub.1 to C.sub.N and, thereafter, the output signals corresponding to the incident light are output from the pixels 51 to 5N of the next line including the defective pixels 51 and 52.

As shown in FIG. 6, before the signals corresponding to the defective pixels 51 and 52 are output from the photoelectric conversion unit 1 to the output line L.sub.1, the signals of the pixels 41 and 42 are read out of the accumulation capacitors C.sub.1 and C.sub.2 to the output lines L.sub.3 and L.sub.4 by output pulses O.sub.M1 and O.sub.M2 from output lines M.sub.1 and M.sub.2 of the memory control pulse generating circuit 6. When the signal of the pixel 51 is output to the output line L.sub.1, by turning on the sample and hold MOS transistor T.sub.3, the signal O.sub.L3 of the pixel 41 is output as an output signal O.sub.L2 to the output line L.sub.2. In a manner similar to the above, when the signal of the pixel 52 is output, the signal O.sub.L4 of the pixel 42 is also output as an output signal O.sub.L2 to the output line L.sub.2. In this manner, the defective pixel can be corrected at an arbitrary timing.

FIG. 7 is a schematic diagram of a solid-state image pickup apparatus to which the invention is applied.

In the diagram, an image pickup device 201 in which photo sensors are arranged like an area executes a television scan by a vertical scanning unit 202 and a horizontal scanning unit 203.

A signal generated from the horizontal scanning unit 203 is output as a standard television signal through a processing circuit 204.

Driving pulses .phi..sub.HS, .phi..sub.H1, .phi..sub.H2, .phi..sub.VS, .phi..sub.V1, .phi..sub.V2. and the like of the vertical and horizontal scanning units 202 and 203 are supplied from a driver 205. The driver 205 is controlled by a controller 206.

As described in detail above, according to the photoelectric converting apparatus of the invention, the first signal which is output from the photoelectric conversion unit is stored into the analog memory and the first signal stored can be output from the analog memory at a desired timing in correspondence to the second signal which is output from the photoelectric conversion unit.

On the other hand, by using the analog memory, the photoelectric conversion unit and the analog memory can be also formed onto the same semiconductor substrate. For instance, if the photoelectric conversion unit and the analog memory are constructed by MOS type transistors or the like, they can be formed by the same process. Therefore, the apparatus can be easily manufactured and the apparatus in which the sensor unit and the memory unit have the same characteristics can be obtained. There is a large effect such that a system in which the small size, low costs, and multifunctions are realized can be accomplished.