US 5,278,084 AGrant
Method of Manufacturing a Semiconductor Device
Issue Date:1994-01-11
•11 Claims
•5 Drawing Sheets
Abstract
A method for manufacturing BiCMOS semiconductor devices in which an oxide layer formed on the surf ace of a semiconductor substrate for the purpose of facilitating formation of spacers adjacent to sidewalls of the gates of the MOS transistors thereof is only partially removed, by using a dry etching process, to thereby leave a residual oxide layer, which is then removed, by using a wet etching process, to thereby form the spacers. Alternatively, all portions of the oxide layer except a portion thereof overlying the base-emitter region of the bipolar transistor of the BiCMOS device is removed, thereby precluding the necessity of etching the oxide layer away at the base-emitter junction. In either case, the DC forward current gain Hfe and linearity of the bipolar transistor of the BiCMOS device are enhanced.
Metadata
Assignee
- Samsung Electronics Co., Ltd.
Inventors
- Yong J. Lee
- Duk M. Yi
- Young O. Kim
- Gyu C. Kim
Application Information
Application Number:US 8802122
Filing Date:1992-05-08
Priority Date:1991-05-09
Art Unit:114
Classifications
IPC:
H01L 21265
Field of Search:
43714835734;59;228;235;56;57DIG. 9;DIG. 13134
Patent Drawings (5 sheets)
Description
Background of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of integrating both bipolar and CMOS transistors on the same substrate.
The present trend towards miniaturization and increased operating speeds of electronic products, has necessitated the development of multi-functional semiconductor devices having both bipolar and CMOS transistors fabricated on a single semiconductor chip. This technology is commonly referred to as BiCMOS.
BiCMOS devices generally have a lightly doped drain (LDD) structure in order to prevent an undesirable drop in the breakdown voltage thereof due to injection of hot electrons generated by the NMOS transistors thereof. The LDD structure is generally obtained by the below-described process.
More particularly, after the gate electrodes of the PMOS and NMOS transistors are formed, an oxide layer of 2000-3000 .ANG. is formed by means of a chemical vapor deposition (CVD) technique, and then removed by means of a dry etching technique, such as reactive ion etching (RIE), until the surface of the semiconductor substrate is exposed, to thereby form spacers adjacent to the sidewalls of the gate electrodes. The regions beneath the spacers are protected from subsequent ion implantation which is carried out to form the drain regions. The regions beneath the spacers are lightly doped by diffusion, thereby increasing the breakdown voltages at the edge of the drain junctions.
The above-described process for forming LDD structures in BiCMOS devices suffers from the following drawbacks and shortcomings. More particularly, the step of dry etching to remove the oxide layer for forming the spacers produces damages such as dislocation on the surface of the substrate. Further, the degree of oxide removal is variable and non-uniform across the surface of the wafer in which the BiCMOS devices are formed, due to the inherent uniformity limitations of the dry etching equipment. These problems with dry etching render the base-emitter junctions in BiCMOS devices unstable, thereby degrading the reliability thereof, and further, causing non-linearity of the DC forward current gain Hfe of the bipolar transistors thereof.
As is evident from the foregoing, there presently exists a need for a method of manufacturing a BiCMOS device which overcomes the above-described drawbacks and shortcomings of the presently available BiCMOS manufacturing technology. The present invention fulfills this need.
Summary of the Invention
The present invention encompasses, in a first preferred embodiment, a method for manufacturing a BiCMOS semiconductor device in which an oxide layer formed over the entire surface of a semiconductor substrate, for the purpose of facilitating the formation of spacers adjacent to sidewalls of the gates of the MOS transistors thereof, is only partially removed, by using a dry etching process, preferably a reactive ion etching process, to thereby leave a residual oxide layer. Then, the residual oxide layer is removed by using a wet etching process, to thereby form the spacers adjacent to the sidewalls of the gates. Alternatively, in a second preferred embodiment of the present invention, all portions of the oxide layer except a portion thereof overlying the base-emitter region of the bipolar transistor of the BiCMOS device is removed, thereby precluding the necessity of etching the oxide layer away at all at the base-emitter junction. In either case, with the method of the present invention, the prior art problems of damages, such as dislocation, and nonuniformity of oxide layer removal, are eliminated, thereby resulting in enhanced DC forward current gain Hfe and linearity for the bipolar transistor of the BiCMOS device.
Brief Description of the Drawings
The various features and advantages of the present invention may be more readily understood with reference to the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:
FIGS. 1A to 1I are cross-sectional views depicting successive manufacturing steps of the first preferred embodiment of the present invention; and,
FIGS. 2A to 2E are cross-sectional views depicting successive manufacturing steps of a second preferred embodiment of the present invention.
Detailed Description of the Invention
With reference now to FIGS. 1A to 1I, there can be seen a step-by-step illustration of a BiCMOS manufacturing process according to a first preferred embodiment of the instant invention. Although various specific process parameters and other details of implementation are set forth in the following description, it should be immediately recognized that the present invention is not limited thereto. Rather, the present invention, in its broadest aspect, resides in the basic methodology employed to manufacture a BiCMOS device, not the particular details of implementation thereof, as these details will vary according to the application and environment in which the method of the present invention is utilized, in a manner well-known to the those of ordinary skill in the semiconductor process art.
Referring specifically now to FIG. 1A, after sequentially forming a first pad oxide layer 3, a first nitride layer 5, and a photoresist layer 7 on the entire surface of a P-type semiconductor substrate 1 having, e.g., a resistivity of 2-20 .OMEGA..cm and an orientation of {100}, a predetermined part of the first pad oxide layer 3, is exposed, e.g., by a conventional photolithography process. Next, first and second ion implantation regions 9, 11 are formed as Nt buried layers on the exposed part of the first pad oxide layer 3 by the ion implantation of N-type impurities, such as arsenic with a dose of 1.times.10.sup.15 .about.5.times.10.sup.15 ion/cm.sup.2 at an energy of about 100 KeV.
With reference to FIG. 1B, after removing the photoresist layer 7, a second oxide layer 13 is formed by thermal oxidation of the exposed part of the first pad oxide layer 3 by using the first nitride layer 5 as a mask. During thermal oxidation, the impurities in the first and second ion implantation regions 9, 11 are diffused and formed first and second N+ buried layers 15, 17, respectively. Then, after removing the nitride layer 5, a third ion implantation region 19 is formed by ion implantation of P-type impurities, such as boron with a dose of 1.times.10.sup.13 .about.5.times.10.sup.13 ion/cm.sup.2 at an energy of about 80 KeV, in order to form a P+ buried layer in the substrate 1 under the first pad oxide layer 3, by using the second oxide layer 13 as a mask.
With reference to FIG. 1C, the impurities in the third ion implantation region 19 are diffused and form a third P+ buried layer 21. After removing the first and second oxide layers 3 and 13, an epitaxial layer 30 of, e.g., about 1.5 .mu.m is formed. Subsequently, first, second, and third wells 23, 25, and 27 are formed. The first and second wells 23 and 25 are formed by ion implanting and thermal processing of N-type impurities, such as phosphorous with a dose of 1.times.10.sup.12 .about.3.times.10.sup.12 ion/cm.sup.2 at an energy of 180 KeV, and the third well 27 is formed by ion implantation of P-type impurities such as boron. Next, a third pad oxide layer 29 is formed on the surface of the first, second, and third wells 23, 25, and 27.
With reference to FIG. 1D, a field oxide layer 31 for isolating active regions is formed, e.g., by conventional local oxidation of silicon (LOCOS). Subsequently, N-type impurities such as phosphorous are implanted into a predetermined part of the second well 25, e.g., with a dose of 3.times.10.sup.15 .about.5.times.10.sup.15 ion/cm.sup.2 at an energy of about 100 KeV, followed by thermal processing, to form a collector region 33 of a bipolar transistor C and to remove the third pad oxide layer 29.
With reference to FIG. 1E, a gate oxide layer 35 of 200-500 .ANG. and gates 37 of 2000-3000 .ANG. are formed on predetermined parts of the first and third wells 23, and 27. The gates 37 are preferably formed of polycrystalline silicon, or metal silicide. Next, N-type impurities are ion-implanted in the first and third wells 23 and 27, e.g., with a dose of 1.times.10.sup.13 .about.5.times.10.sup.13 ion/cm.sup.2 at an energy of about 65 KeV. By using the gates 37 as a mask, fourth and fifth ion implantation regions 39 and 41 are formed for the LDD structure of MOS transistors A, B. Subsequently, an oxide layer 43 of 2000-3000 .ANG. is formed over the entire structure by a method such as chemical vapor deposition (CVD) or low temperature oxidation (LTO).
With reference to FIG. 1F, the oxide layer 43 is partially removed, e.g., by a dry etching method such as reactive ion etching (RIE), until only a thickness of 200-500 .ANG. thereof remains as a residual oxide layer 45. If the oxide layer 43 is completely removed by the dry etching method, as is done with current BiCMOS technology, damage such as dislocation is produced on the surfaces of the wells 23, 25, and 27.
With reference to FIG. 1G, the residual oxide layer 45 is removed, e.g., by a conventional wet etching method, to expose the first, second, and third wells 23, 25, and 27. In this manner, spacers 47 are formed adjacent to the sidewalls of the gates 37. Since the residual oxide layer 45 is removed by a wet etching method, rather than by dry etching, no damage, such as dislocation, is caused to the surface of the wells 23, 25, and 27. Also, as the oxide layer 43 is removed by the dry etching method, such as RIE, except for the residual oxide layer 45, before the residual oxide layer 45 is removed by the wet etching method, the residual oxide layer 45 can be removed uniformly everywhere, independent of the position of the substrate 1 on the host wafer (not shown). Next, a first oxide interlayer 49 of 500-1500 .ANG. is formed on the surface of the entire structure, e.g., by conventional chemical vapor deposition (CVD) or low temperature oxide deposition (LTO), and sixth and seventh ion-implantation regions 51 and 53 are formed by ion-implantation of impurities such as BF.sub.2 and arsenic into the first and third wells 23 and 27, respectively, e.g., with a dose of 3.times.10.sup.15 .about.5.times.10.sup.15 ion/cm.sup.2 at a proper energy, by using the gates 37 as a mask. During the forming of the sixth ion-implantation region 51, an eighth ion-implantation region 55, for the base region of a bipolar transistor C, is simultaneously formed in the second well 25. A ninth ion-implantation region 57 is formed in the second well 25 by the ion-implantation of P-type impurities, such as boron with a dose of 1.times.10.sup.13 .about.2.times.10.sup.13 ion/cm.sup.2 at an energy of about 80 KeV.
With reference to FIG. 1H, a predetermined part of the first -oxide layer 49 where the emitter region of the bipolar transistor C is to be subsequently formed (as described below), is removed, e.g., by a conventional photolithography process. In this step, the predetermined part of the first oxide layer 49 is preferably removed by the RIE method, to expose the second well 25, and the exposed part of the second well 25 is again dry-etched, e.g., by a plasma method. In this manner, damage such as dislocation from the surface of the second well 25 which is exposed during the removal of the first oxide layer 49 by the reactive ion etching (RIE) step, can be removed by the subsequent plasma dry etching step. Next, after a polycrystalline silicon layer (of which only a post-etching portion 59 is shown) is deposited on the first oxide layer 49, N-type impurities such as arsenic, for an emitter source, are ion-implanted into the entire surface thereof, e.g., with a dose of 5.times.10.sup.15 .about.8.times.10.sup.15 ion/cm.sup.2. An emitter contact region 59 is formed by patterning the polycrystalline silicon layer, and then, source and drain regions 61 of a PMOS transistor A, source and drain regions 63 of an NMOS transistor B, and a base region of a bipolar transistor C are formed by diffusion. In this step, the N-type impurities doped in the emitter contact region 59, such as arsenic, are diffused into a predetermined portion of the base region 66 to thereby form an emitter region 67. Thus, the base-emitter junction of the emitter region 67 in the base region 65 are stably formed, thereby improving the DC forward current gain characteristics Hfe of the resultant bipolar transistor C.
With reference to FIG. 1I, a second oxide layer 69 is formed over the entire structure, e.g., by a chemical vapor deposition (CVD) or high temperature oxide deposition method (HTO). Subsequently, a passivation layer 71 is formed by depositing phospho-silicate glass (PSG) or borophospho-silicate glass (BPSG) over the entire surface of the second oxide layer 69, and contact holes 70 are formed, e.g., by a conventional photolithography process. Finally, a metal conductivity layer 73 is formed through the contact holes 70, to complete the BiCMOS device D1.
With reference now to FIGS. 2A-2E, there can be seen a step-by-step illustration of a BiCMOS manufacturing process according to a second preferred embodiment of the present invention. It should be appreciated that the prefatory statements made hereinabove in connection with the first preferred embodiment depicted in FIGS. 1A-1I apply equally with respect to the second preferred embodiment depicted in FIGS. 2A-2E.
In order to avoid duplicative disclosure, the description of the method of the second preferred embodiment of the present invention will begin with the step (depicted in FIG. 2A) corresponding to the step in the method of the first preferred embodiment of the present invention depicted in FIG. 1E, since all preceding steps may suitably be carried out in the same manner as described previously in connection with the first preferred embodiment, as illustrated in FIGS. 1A-1D.
Referring specifically now to FIG. 2A, a gate oxide layer 35 of 200-500 .ANG. and gates 37 of 2000-3000 .ANG. are sequentially formed on predetermined parts of the first and third wells 23 and 27. The gates 37 are formed of polycrystalline silicon or metal silicide. Next, fourth and fifth ion implantation regions 39 and 41 are formed by ion implantation of P-type and N-type impurities, such as boron and phosphorous, respectively, into the first and third wells 23 and 27, e.g., with a dose of 1.times.10.sup.13 .about.5.times.10.sup.13 ion/cm.sup.2 at a proper energy, by using gates 37 as a mask, in order to form the lightly doped drain structure of the MOS transistors A and B. Subsequently, base region 65 of the bipolar transistor is formed in the surface of the second well 25, which is formed by ion-implantation of P-type impurities, such as boron, e.g., with a dose of 1.times.10.sup.13 .about.2.times.10.sup.13 ion/cm.sup.2 an energy of 80 KeV. Then, an oxide layer 43 of 2000-3000 .ANG. is formed over the entire structure by a chemical vapor deposition (CVD) or low temperature oxidation method (LTO).
With reference to FIG. 2B, the oxide layer 43, except for the portion thereof disposed above the base region 65, is removed, e.g., by a conventional photolithography process. Next, a portion of the oxide layer 43 corresponding to the extrinsic base region of the bipolar transistor C is removed, e.g., by a reactive ion etching method, such as RIE or the like. During this step, spacers 47 are formed adjacent to the sidewalls of the gates 37.
With reference to FIG. 2C, sixth and seventh ion-implantation regions 51 and 53 are formed by ion-implantation of P-type impurities, such BF.sub.2, and N-type impurities, such as phosphorous, into the first and third wells 23 and 27, e.g., with a dose of 3.times.10.sup.15 .about.5.times.10.sup.15 ion/cm.sup.2 at a proper energy, by using the gates 37 as a mask. While forming the sixth ion-implantation region 51, an eighth ion-implantation region 55, for forming the extrinsic base region of a bipolar transistor C, is formed in the exposed part of the base region 65, in order to reduce the contact resistance with the metals formed thereafter.
With reference to FIG. 2D, after a first oxide layer 49 of 500-1500 .ANG. is deposited, the predetermined part of the emitter region of the bipolar transistor C is exposed, e.g., by a conventional photolithography process. Then, after a polycrystalline silicon layer (of which only a post-etching portion 59 is shown) is deposited on the surface of the first oxide layer 49, N-type impurities such as arsenic are ion-implanted into the entire surface thereof, in order to form the impurities source for the emitter of the bipolar transistor C. After an emitter contact region 59 is formed by patterning the polycrystalline silicon layer, the source and drain region 61 of the PMOS transistor A, the source and drain region 63 of the NMOS transistor B, and the extrinsic base region 66 of the bipolar transistor C are formed by diffusion. Next, N-impurities coated at the emitter contact region 59 are diffused to form an extrinsic emitter region 67.
With reference to FIG. 2E, a second oxide layer 69 and a passivation layer 71 are formed by coating the entire structure with phospho-silicate glass (PSG) or borophospho-silicate glass (BPSG). Finally, after contact holes 70 are formed, e.g., by a conventional photolithography process, a metal conductivity layer 73 is formed, to thereby complete the BiCMOS device D2.
It can now be appreciated that the BiCMOS device manufacturing method of both the first and second preferred embodiments of the present invention provides several important advantages over presently available BiCMOS technology. More particularly, the spacers 47 adjacent to the sidewalls of the gates 37 of the MOS transistors A and B are formed by a two-step oxide layer etching technique which ensures uniform removal of the oxide layer 43 and prevents damage, such as dislocation, to the base-emitter junction of the bipolar transistor C.
Although two preferred embodiments of the present invention have been described in detail, it should be clearly understood that many variations and/or modifications of the basic inventive concepts herein taught which may appear to those skilled in the pertinent art will fall within the spirit and scope of the present invention, as defined in the appended claims.
Claims
What is claimed is:
1. A method for manufacturing a BiCMOS semiconductor device, comprising the steps of: ion implanting impurities of a first conductivity type in spaced-apart first and second regions of a semiconductor substrate of a second conductivity type, to thereby provide first and second ion implantation regions of a first conductivity type; diffusing impurities of said first conductivity type into said first and second ion implantation regions in such a manner as to form first and second buried layers of said first conductivity type; ion implanting impurities of said second conductivity type in a third region of said semiconductor substrate disposed between said first and second regions, to thereby provide a third ion implantation region of said second conductivity type; diffusing impurities of said second conductivity type into said third ion implantation region in such a manner as to form a third buried layer of said second conductivity type; forming an epitaxial layer on the surface of said first, second, and third buried layers; forming first and second well regions of said first conductivity type in said epitaxial layer and in alignment with said first and second buried layers, respectively; forming a third well region of said second conductivity type in said epitaxial layer in alignment with said third buried layer; forming a patterned field oxide layer over first predetermined portions of said first, second, and third well regions; forming a patterned gate oxide layer over second predetermined portions of said first and third well regions; forming a collector region of said first conductivity type in said second well region; forming gate electrodes on said second predetermined portions of said first and third well regions; forming an oxide layer over the entire surface of a first resultant structure obtained by all of the preceding steps; partially removing said oxide layer by using a dry etching process, to thereby leave a residual oxide layer over the entire surface of said first resultant structure; removing said residual oxide layer by using a wet etching process, to thereby form spacers adjacent to sidewalls of said gate electrodes; forming source regions of said second conductivity type in each of said first and third well regions; forming drain regions of said first conductivity type in each of said first and third well regions; forming a base region of said second conductivity type in said second well region; forming a base oxide layer on a second resultant structure obtained by all of the preceding steps; forming an emitter and emitter contact region in a predetermined portion of said base region; forming an oxide interlayer on said base oxide layer; forming a passivation layer on said oxide interlayer; forming contact holes through said passivation layer, said oxide interlayer, and said base oxide layer, at locations such as to expose said source, drain, base, collector, and emitter contact regions; forming a conductive wiring layer through said contact holes; and, wherein first and second MOS transistors of opposite conductivity types are provided in said first and third well regions, and a bipolar transistor is provided in said second well region, such that the ultimate resultant structure obtained by all of the preceding steps comprises a BiCMOS semiconductor device.
2. The method as set forth in claim 1, wherein said dry etching process comprises a reactive ion etching process.
3. The method as set forth in claim 1, wherein said residual oxide layer has a thickness of approximately 200-500 angstroms.
4. The method as set forth in claim 3, wherein said oxide layer has thickness of approximately 2000-3000 angstroms.
5. The method as set forth in claim 1, further comprising, after said forming gate electrodes step and before said forming an oxide layer step, the following steps: ion implanting impurities of said first conductivity type into said third well region in such a manner as to form a lightly doped drain structure therein; and, ion implanting impurities of said second conductivity type into said first well region in such a manner as to form a lightly doped drain structure therein.
6. A method for manufacturing a BiCMOS semiconductor device, comprising the steps of: ion implanting impurities of a first conductivity type in spaced-apart first and second regions of a semiconductor substrate of a second conductivity type, to thereby provide first and second ion implantation regions of a first conductivity type; diffusing impurities of said first conductivity type into said first and second ion implantation regions in such a manner as to form first and second buried layers of said first conductivity type therebeneath; ion implanting impurities of said second conductivity type in a third region of said semiconductor substrate disposed between said first and second regions, to thereby provide a third ion implantation region of said second conductivity type; diffusing impurities of said second conductivity type into said third ion implantation region in such a manner as to form a third buried layer of said second conductivity type therebeneath; forming an epitaxial layer on the surface of said first, second, and third buried layers; forming first and second well regions of said first conductivity type in said epitaxial layer and above said first and second buried layers, respectively; forming a third well region of said second conductivity type in said epitaxial layer and above said third buried layer; forming a patterned field oxide layer over predetermined portions of said first, second, and third well regions to define windows for facilitating introduction of dopants, in subsequently-recited steps, which will constitute active areas of transistors to be formed in said first, second, and third well regions; forming a collector region of said first conductivity type in said second well region; forming gate electrodes on a central portion of the surface of said first and second wells; forming a base region of said second conductivity type in said second well region; forming an oxide layer over the entire surface of a first resultant structure obtained by completion of all of the preceding steps; removing all of said oxide layer except for a first portion thereof disposed above said base region, and forming spacers adjacent to sidewalls of said gate electrodes, wherein said first portion of said oxide layer has a first opening provided therein; forming source regions of said second conductivity type in each of said first and third well regions; forming drain regions of said first conductivity type in each of said first and third well regions; introducing impurities of said second conductivity type through said first opening provided in said first portion of said oxide layer, to thereby form a highly-doped extrinsic base region in said base region; forming a base oxide layer over the entire surface of a second resultant structure obtained by completion of all of the preceding steps; forming a second opening through said base oxide layer and said first portion of said oxide layer, laterally displaced from said first opening; introducing impurities of said first conductivity type into said second opening to form an emitter contact region in said second opening, and diffusing said introduced impurities to form an emitter region in said base region laterally displaced from said extrinsic base region; forming an oxide interlayer on said base oxide layer; forming a passivation layer on said oxide interlayer; forming contact holes through said passivation layer, said oxide interlayer, and said base oxide layer, at locations such as to expose said source, drain, extrinsic base, collector, and emitter contact regions; forming a conductive wiring layer through said contact holes; and, wherein first and second MOS transistors of opposite conductivity types are provided in said first and third well regions, and a bipolar transistor is provided in said second well region, such that the ultimate resultant structure obtained by completion of all of the preceding steps comprises a BiCMOS semiconductor device.
7. The method as set forth in claim 6, wherein said forming source regions, forming drain regions, and forming extrinsic base regions steps are performed concurrently.
8. The method as set forth in claim 6, wherein said first conductivity type is N-type and said second conductivity type is P-type.
9. The method as set forth in claim 6, further comprising the step of depositing a polysilicon layer on the surface of the base oxide layer, after execution of said forming a second opening step.
10. The method as set forth in claim 9, further comprising the step of removing all portions of said polysilicon layer except a portion thereof which fills said second opening, after execution of said depositing a polysilicon layer step and before execution of said introducing impurities of said first conductivity type into said second opening step.
11. The method as set forth in claim 6, further comprising, after said forming gate electrodes step and before said forming a base region step, the following steps: ion implanting impurities of said first conductivity type into said third well region in such a manner as to form a lightly doped drain structure therein; ion implanting impurities of said second conductivity type into said first well region in such a manner as to form a lightly doped drain structure therein; and, wherein said gate electrodes serve as a mask during the above-recited ion implanting steps.