Multisignal Synchronizer With Shared Last Stage

The present invention relates to N-stage synchronizers. More particularly, the present invention relates to N-stage synchronizers for use with multi-source signals.

Computer systems often operate together. To do so, they are connected through an interface. This interface may have a synchronizer to ensure that the signals generated by one system are synchronized in the time domain with signals of a second system so that communications between the two systems is effected.

When conventional synchronization methods have been used, the synchronized signals, in many cases, could not be input to the destination system because the proper set-up and hold time limitations could not be met since such destination systems had critical timing limitations for such synchronized signals. This becomes even more complicated if the synchronous signals have multiple asynchronous sources. More specifically, each of the multiple asynchronous sources that were used to generate the synchronous signal has its own synchronizer and the output of these synchronizers are input to an OR gate. The OR gate function delayed the synchronous signal even more and made meeting the set-up and hold time requirements even more difficult.

A synchronizing circuit of the type just described is shown in FIG. 1 generally at 100. The multiple asynchronous sources for generating synchronous signal 124 are ASYNC SOURCE A signal 102, ASYNC SOURCE B signal 110, and ASYNC SOURCE C signal 116. The synchronization of each of these asynchronous source signals is carried out by a two step synchronizer consisting of two D-type flip-flops. ASYNC SOURCE A signal 102 is synchronized by series connected flip-flops 104 and 108, ASYNC SOURCE B signal 110 by series connected flip-flops 112 and 114, and ASYNC SOURCE C signal 116 by series connected flip-flops 118 and 120. All of these flip-flops are clocked by the destination system clock signal 106.

The outputs of last stage flip-flops 108, 114, and 120 are input to OR gate 122. Each of these output signals has been synchronized in the time domain of the destination system. The output of OR gate 122 is synchronous signal 124 which is synchronized in the time domain of the destination system except for the delays associated with carrying out the OR function.

To minimize the delays caused by the OR function, ideally, the last stage flip-flops 108, 114, and 120 of the respective synchronizers are placed as physically close to the destination system as possible. This assists in reducing the capacitance between the systems and, thus, the time necessary to assert and de-assert the synchronized signal. However, this method of reducing delays becomes difficult when each of the multiple sources has its own synchronizer because only the OR gate, such as OR gate 122, can be placed next to the destination system because of physical constraints of any system implementing a circuit such as that shown in FIG. 1. Moreover, the greater the number of multiple sources, the greater the distance the last stages of the separate synchronizers will be from the destination system. The lengthening of the distance that the last stage flip-flops are from the destination system also adds to the timing of synchronous signal 124 and makes meeting the set-up and hold time requirements even more difficult.

This same problem exists in a bit-sliced integrated circuit. For example, a particular pin of the circuit may assume several functions depending on its assigned "personality", and each of these functions may require an on-chip synchronizer. The timing problem described above will then occur with respect to the timing delays associated with the OR function and the last stages of the synchronizers of the number of multiple sources being able to be in close proximity to an output driving pin.

The present invention overcomes these and other problems as set forth in the remainder of the specification and referring to the attached drawings.

The present invention is a N-stage synchronizer for providing a synchronous signal, which is derived from multiple sources which are asynchronous with the time domain of a destination system. The synchronizer reduces the delays associated with the synchronization process caused by an OR function. The synchronizer of the present invention also reduces the problems associated with meeting the critical timing requirements at the destination system, such as set-up and hold timing.

The N-stage synchronizer of the present invention generates a synchronous signal from multiple asynchronous sources. Each source signal is asynchronous with the destination clock domain. The synchronizer has at least a separate first synchronizer stage for each of the multiple asynchronous sources.

Because the clock domain of the input source signals can be of a sufficiently different rate from that of the destination clock domain, an input source signal could be missed, or seen by more than one synchronizer. An edge detector for each source signal ensures that each source signal is not lost if there is an alignment of clock pulses.

The OR function is performed between two stages of the N-stage synchronizer and preferably between the last two stages which results in a shared last stage. There are time delays associated with the OR function being performed before the last stage, but this only affects the reliability of the synchronizer slightly by taking away some of set-up time from the last stage. This is outweighed by the fact that the last stage can be placed close to the destination system thus reducing capacitance and, hence, the time necessary to assert or de-assert the synchronous signal. Furthermore, the final synchronous signal is generated quicker than it would be generated using prior art methods.

The present invention will be described in detail in the remaining portion of the specification making references to the drawings.

FIG. 1 is a prior art synchronizer for generating a synchronous signal that is derived from multiple asynchronous sources.

FIG. 2 is the synchronizer of the present invention for generating a synchronous signal that is derived from multiple asynchronous sources.

FIG. 3 is a timing diagram for the synchronizer of the present invention that is shown in FIG. 2.

The present invention is a N-stage synchronizer that has a shared last step that is used for generating a synchronous signal that is derived from multiple asynchronous sources.

Referring to FIG. 2, the N-stage synchronizer of the present invention is shown generally at 200. FIG. 2 only shows two stage synchronizer 200, however, it is understood that synchronizer 200 may have many more stages.

DATA.sub.-- RDY signal 232 is derived from multiple data ready signals from sources asynchronous to destination system clock signal 220. These are DATA1.sub.-- RDY signal 202, DATA2.sub.-- RDY signal 204, and DATA3.sub.-- RDY signal 206. It is understood that there may be any number of asynchronous source signals from which DATA.sub.-- RDY signal 232 is derived.

The data line (not shown) is a path external to the synchronizer of the present invention. Each data package is sequential on the data line. A data package may be 128 bits wide, however, the bit size is not limiting with respect to the present invention. The data ready signals 202, 204, and 206 are asserted at fixed intervals based on the clock domain of the source system. There is a data ready signal associated with each data package. DATA.sub.-- RDY signal 232 is asserted whenever it is valid to accept data from the data line into the destination system, as determined by the present invention.

According to the present invention, there is an edge detector associated with each data ready source signal. As shown in FIG. 2, these are edge detectors 214, 216, and 218. DATA 1.sub.-- RDY signal 202 is input to the clock input of edge detector 214, DATA 2.sub.-- RDY signal 204 is input to the clock input of edge detector 216, and DATA 3.sub.-- RDY signal 206 is input to the clock input of edge detector 218. The input to the data input of each of the edge detectors is a TRUE signal. As shown, TRUE signal 208 is input to the data input of edge detector 214, TRUE signal 210 is input to the data input of edge detector 216, and TRUE signal 212 is input to the data input of edge detector 218. The output of edge detector 214 is EDGE.sub.-- CATCH.sub.-- A signal 306 which is input to the D input of flip-flop 222, the output of edge detector 216 is EDGE.sub.-- CATCH B signal 308 which is input to the D input of flip-flop 224 and the output of edge detector 218 is EDGE.sub.-- CATCH.sub.-- C signal 310 which is input to the D input of flip-flop 226. Each of the edge detectors is cleared by the signal output from the inverting output of a stage flip-flop associated with a particular edge detector.

Edge detector 214, 216, and 218 may be used to detect the rising or falling edge of a signal. However, in FIG. 2, preferably each edge detector is used to detect the rising edge of the input source signal.

First stage flip-flop 222 is clocked by destination system clock signal 220. Flip-flop 222 is clocked on an edge of clock signal 220, and the output of flip-flop 222 is the first input to OR gate 228. Preferably, flip-flop 222 is a D-type flip-flop.

First stage flip-flop 224 also is clocked by destination system clock signal 220. When clocked, the output of flip-flop 224 is the second input to OR gate 228. Preferably flip-flop 224 also is a D-type flip-flop.

In a similar fashion, first stage flip-flop 226 is clocked by destination system clock signal 220. The output of flip-flop 226 is the third input to OR gate 228. This flip-flop also is preferably a D-type flip-flop.

OR gate 228 performs the OR function with regard to the three input signals. There is time delay associated with OR gate 228 performing its OR function. This delay has a slight impact on the set-up time for the last stage. This delay, however, is overshadowed by the advantages the present invention provides.

These advantages are that since the OR function is performed before the last step, last stage flip-flop 230 may be placed closer to the destination system. This reduces the capacitance and, therefore, the time needed to assert or de-assert for DATA.sub.-- RDY signal 232. As such, a synchronous signal 232 is provided in less time. The only recognizable sacrifice is a slight decrease in reliability, which in reality is not enough to warrant concern for the proper operation of the synchronizer of the present invention.

The output of OR gate 230 is input to the data input of last stage flip-flop 230. Because the OR function precedes the last stage, this last step is shared by all of the asynchronous source signals. The output of last step flip-flop 228 is DATA.sub.-- RDY signal 232. The last stage flip-flop, preferably is a D-type flip-flop. The added delay caused by the OR function being after the last stage is eliminated.

The present invention can include more than the two levels of synchronization shown in FIG. 2. Where there are multiple levels of synchronization, the OR gate can be placed anywhere in the circuit after the edge detectors, as long as it is not placed after the last synchronization stage.

Referring now to FIG. 3, the timing diagram for the operation of the synchronizer of the present invention as shown in FIG. 3 is illustrated.

Clock signal 302 is the clocking signal for the source domain, and, therefore, is the clocking signal for DATA1.sub.-- RDY signal 202, DATA2.sub.-- RDY signal 204, and DATA3.sub.-- RDY signal 206. In the representative embodiment, each data package is two source clock periods in length and the data ready signal for each data package is asserted three source clock periods prior to when the data package is ready. The timing relationship between the data package and the assertion of the corresponding data ready signal is known, and depends on the number of stages of synchronization to take place according to the present invention. The more stages of synchronization, the earlier the data ready signal must be asserted. In the representative embodiment, there is one source clock period between each data package.

When DATA1.sub.-- RDY signal 202 is asserted at t1, TRUE signal 208, which is input to the data input of edge detector 214, is asserted. This will cause EDGE.sub.-- CATCH.sub.-- A signal 306 to be asserted at t1. EDGE.sub.-- CATCH.sub.-- A signal 306 will be de-asserted on the next rising edge of destination system clock signal 220 because the signal output from the inverting output of flip-flop 222 will clear edge detector 214.

FFIA signal 312, which is output from flip-flop 222, will be asserted at the de-assertion of EDGE.sub.-- CATCH.sub.-- A signal 306. FFIA signal 312 will be asserted for one clock period of the destination system clock. As shown in FIG. 3, FFIA signal 312 will be asserted from after t2 to just before t4.

DATA.sub.-- RDY signal 232 will be asserted one destination system clock period after FFIA signal 312 is asserted, which is just before t4. The DATA.sub.-- 1 package is ready at t4. On the next rising edge of the destination system clock signal, during t5, the DATA.sub.-- 1 package is obtained by the destination system and DATA.sub.-- RDY signal 232 is de-asserted.

This same type of operation takes place with regard to the destination system obtaining the DATA.sub.-- 2 package and the DATA.sub.-- 3 package. Therefore, the same processing functions are performed with regard to DATA2.sub.-- RDY signal 204, edge detector 216, EDGE.sub.-- CATCH.sub.-- B signal 308, flip-flop 224, and FFIB signal 314; and DATA3.sub.-- RDY signal 206, edge detector 218, EDGE.sub.-- CATCH.sub.-- C signal 310, flip-flop 226, and FFIC signal 316. Accordingly, the DATA.sub.-- 2 package is obtained during t8 and the DATA.sub.-- 3 package is obtained during t10.

As can be seen in FIG. 2, the DATA.sub.-- 2 package is not lost, even though it is ready at t7 and it is followed immediately by the rising edge of the destination system clock signal which will cause the DATA.sub.-- 2 package to be obtained by the destination system.

The above process guarantees that each input signal 202, 204 and 206 is synchronized into exactly one synchronizer output pulse, regardless of the length of the input source signal. As such, the output signal, DATA.sub.-- RDY signal 232 will be asserted for exactly one cycle for each input source signal that is asserted. For example, if DATA1.sub.-- RDY signal 202 and DATA2.sub.-- RDY signal 204 shared the same synchronizer, then the pulses would align in such a manner that DATA2.sub.-- RDY signal 204 would be lost and only one pulse on the synchronizer output would exist. The present invention avoids the problem by using a separate edge detector, edge detectors 214, 216, and 218, with each of the each of the source inputs 202, 204 and 206.

The terms and expressions which are employed herein are used as terms of expression and not of limitation. And, there is no intention, in the use of such terms and expression, of excluding the equivalents of the features shown, and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention.