Circuit Arrangement for Detection of an Erroneous Selection Signal Supplied to Selection Means

The invention relates to a circuit arrangement for detection of an erroneous selection signal supplied to a selection means.

In a conventional circuit arrangement of this type, an erroneous selection signal supplied to a selection circuit can be detected by adding a parity bit to a selection signal at a selection signal generating circuit and conducting a parity check for the selection signal by a parity check circuit provided on the input side of the selection circuit.

However, such a conventional circuit arrangement has a disadvantage that when a fault occurs at any of the selection signal generating circuit and the parity check circuit, error detection of selection signals is not properly performed.

According to an aspect of the invention, there is provided a circuit arrangement which comprises: selection means for selecting one of a plurality of input signals on the basis of selection information; transfer means for transferring said selection information to said selection means; fault detection information generating means which receives said selection information via said transfer means to produce fault detection information having a predetermined relationship with said selection information; and fault detection means which receives said selection information directly without passing through said transfer means and examines whether or not the received selection information has a predetermined relation with the fault detection information from said generating means.

Other features and advantages will become apparent from the following description when taken in conjunction with the accompanying drawings in which:

FIG. 1 is a circuit diagram of an embodiment of the invention;

FIG. 2 is a block diagram of one of circuits 10-l-10-n, 12 and 13 shown in FIG. 1;

FIG. 3 shows a truth table of a decoder 3 shown in FIG. 1; and

FIG. 4 shows a truth table of the circuits 12 and 13.

Referring now to FIG. 1, an embodiment of the invention comprises: flip-flops 1 and 2; a decoder 3 connected to the output terminals of the flip-flops 1 and 2; an exclusive OR gate 4 having a first input terminal connected to the output terminal of the flip-flop 1 and a second input terminal; an exclusive OR gate 5 having a first input terminal connected to the output terminal of the flip-flop 2 and a second input terminal; an OR gate 6 having a first input terminal and a second input terminal connected to the output terminals of the gates 4 and 5, respectively; n selection circuits 10-l to 10-n (n is a positive integer) each of which is supplied with corresponding four bits out of four data of n bits each, D.sub.1 (b.sub.11 to b.sub.n1), D2(b.sub.12 to b.sub.n2), D.sub.3 (b.sub.13 to b.sub.n3) and D.sub.4 (b.sub.14 selection circuit 12 having an output terminal connected to the second input terminal of the gate 4; and a selection circuit 13 having an output terminal connected to the second input terminal of the gate 5.

Referring to FIG. 2, one 10-i(1.ltoreq.i.ltoreq.n) of the selection circuits 10-1 to 10-n comprises an AND gate 101 having a first input terminal F1 given the i-th bit b.sub.i1 of the data D.sub.1 and a second input terminal S1 connected to an output terminal SD.sub.O of the decoder 3, an AND gate 102 having a first input terminal F2 given the i-th bit b.sub.12 of the data D.sub.2 and a second input terminal S2 connected to an output terminal SD.sub.1 of the decoder 3, an AND gate 103 having a first input terminal F3 given the i-th bit b.sub.i3 of the data D.sub.3 and a second input terminal S3 connected to an output terminal SD.sub.2 of the decoder 3, an AND gate 104 having a first input terminal F4 given the i-th bit b.sub.i4 of the data D.sub.4 and a second input terminal S4 connected to an output terminal SD.sub.3 of the decoder 3, and an OR gate 105 which performs the logical add operation of the outputs of the gates 101 through 104.

The flip-flops 1 and 2 hold a pair of selection indication signals S0 and S1. The signals S0 and S1 are given to the decoder 3, which in turn produces a logical "1" signal from one of the output terminals SD.sub.0 through SD.sub.3 in accordance with a truth table shown in FIG. 3.

The circuits 12 and 13 have the structure identical to that of the selection circuit 10-i shown in FIG. 2. In the circuit 12, however, the first input terminals F1 through F4 of the gates 101 through 104 are constantly applied with signals of logical levels "0", "0", "1" and "1", respectively. In the circuit 13, on the other hand, they are constantly applied with signals of logical levels "0", "1", "0" and "1", respectively. As a result, if no fault occurs in any portions of the circuitry shown in FIG. 1, the relationship among the signals S0 and S1 and output signals U1 and U2 produced from the circuits 12 and 13 becomes the one shown in the truth table in FIG. 4. Under such a relationship, if all the portions are normal, the gate 6 always produces a logical "0" signal. On the other hand, if a fault occurs in the decoder 3, for example, and thus the logical "1" signal is not produced from the correct output terminal, the relationship shown in the table of FIG. 4 is not satisfied, and a logical "1" signal is produced from the gate 6, which means the occurrence of a fault. In this manner, malfunction relating to the selection signals S0 and S1 can be detected.