Semiconductor Memory Device Having an Internal Signal Detector

The present invention relates to a semiconductor memory device, and more particularly to an internal signal detector for detecting any defects from each internal circuit in the semiconductor memory device.

Recently, there has been an increased demand for semiconductor memory devices that are capable of having high integration and high storage capacity. As semiconductor memory devices are increasingly integrated to obtain greater storage capacity, the number of defects among the memory circuits concomitantly increases to contribute to a low yield in the productivity of these semiconductor memory devices. In order to address problems of defects and low yield, the defect memory circuit of the semiconductor memory devices must be detected.

However, it is very difficult to detect the defective circuit or element thereof in a highly integrated semiconductor memory device over 1 mega byte or 4 mega byte. Moreover, even if the defects are detected, their detecting time is too long.

FIG. 1 shows an internal signal (or circuit) detector of a prior art. The circuit of FIG. 1 detects the defects of an internal signal by using a probing method. The probing method is used to detect the defects and to check the potential characteristic by erecting a probe on a transistor or a pad of the integrated circuit. First and second signal generators 3 and 4 in the chip generate the signals indicating the operational characteristic of circuits or elements thereof in a chip. Although the circuit of FIG. 1 comprises two signal generators, a plurality of signal generators can be included also. First and second probes 1 and 2 are located on the surface of chip, to detect the internal signal signifying the defective element of the chip. In the following, the detecting operation of the internal signal signifying the defective elements of the chip will be described. The first and second transmission probes 1 and 2 are erected on lines connecting the first signal generator 3 and the second signal generator 4; the transmission lines receive signals S.sub.1 and S.sub.2 generated by the first and second signal generators 3 and 4. Thereafter, whether the signals S.sub.1 and S.sub.2 detected between the first and second signal generators 3 and 4 are normal or not is checked by operation of the first and second probes and 2. However, this process, i.e., to obtain the potential value of each node through the physical or electrical probing operation, takes a considerably long debugging time in order to detect the defects. Further, since the higher density is provided to the integrated circuit, the internal circuit becomes more complicated. Accordingly the debugging time increases substantially.

It is therefore an object of the invention to provide a semiconductor memory device which can reduce a debugging operation time.

In accordance with the present invention, the semiconductor memory device having a plurality of first and second signal generators, which are connected by given transmission lines to each other, comprises an internal signal detector including a plurality of latch circuits, connected to the lines, for latching the voltages applied to the transmission lines, and a plurality of registers connected to the latch circuits, for producing the voltages latched onto the latch circuits to the exterior surface of a chip. The internal signal detector can easily be arranged on the vacant space in the chip.

These and other objects of this invention will become apparent to those skilled in the art upon consideration of the accompanying drawing, in which:

FIG. 1 shows a block diagram illustrating an internal signal detector of a prior art;

FIG. 2 shows a block diagram illustrating an internal signal detector according to the present invention;

FIG. 3 shows an embodiment of FIG. 2; and

FIG. 4 shows a timing diagram of FIG. 3 during the debugging operation.

Referring to FIG. 2, a plurality of latch circuits 30a to 30i are arranged in parallel to one another and connected to a plurality of transmission lines l.sub.1 to l.sub.i, which extend from the first signal generators 10a to 10i to the second signal generators 20a to 20i, where predetermined signals are generated from the first and second signal generators. A plurality of shift registers 40a to 40i are connected to the latch circuits 30a to 30i. A clock A controls the latch circuits 30a to 30i and determines the latched time of the voltages applied to the transmission lines l.sub.1 to l.sub.i. A clock B, as a signal supplied from the outside of a chip, controls the shift registers 40a to 40i. The voltages latched onto the latch circuits 30a to 30i are sequentially produced to the outside of the chip through the shift registers 40a to 40i. Therefore, the shift registers 40a to 40i can read the latched voltages by the clock B, bit by bit.

Referring to FIG. 3, the internal signal detecting circuit included in a semiconductor memory device having the first and second signal generators 10 and 20, has a plurality of first transfer transistors MA.sub.1 to MA.sub.i, a plurality of latch circuits 30a to 30i and a plurality of second transfer transistors MB.sub.1 to MB.sub.i, and a differential operation amplifier 40. the first and second signal generators are connected to each other by a plurality of transmission lines l.sub.1 to l.sub.i. The first transfer transistors MA.sub.1 to MA.sub.i are connected to the transmission lines l.sub.1 to l.sub.i through one stages of channels thereof, respectively. And the first transfer transistors MA.sub.1 to MA.sub.i are operated by a first control signal .phi.A. The latch circuits 30a to 30i are connected through input stages thereof to the other stages of the channels of the first transfer transistors MA.sub.1 to MA.sub.i. The latch circuits latch the voltages applied to the transmission lines l.sub.1 to l.sub.i. The second transfer transistors MB.sub.1 to MB.sub.i are connected, through one stages of channels thereof, to the output stages of the latch circuits 30a to 30i, and are operated by second control signals .phi.B.sub.1 to .phi.B.sub.i. In brief, the first transfer transistors are serially connected to the second transfer transistors through the latch circuits, respectively. The shift register 40 is connected through an input stage thereof to the other stages of the channels of the second transfer transistors MB.sub.1 to MB.sub.i. And the shift register 40 produces the voltages latched to the latch circuits 30a to 30i, into the outside of a chip. In the above construction, the first and second transfer transistors MA.sub.1 to MA.sub.i to MB.sub.1 to MB.sub.i employ NMOS transistors. The function of the circuit in accordance with the above construction as shown in FIG. 3 is the same as that of FIG. 2.

The operational characteristic of FIG. 3 will be described with reference to FIG. 4 illustrating the debugging timing. It should be noticed that the second control signals .phi.B.sub.1 to .phi.B.sub.i, with a given time interval, are applied sequentially to the second transfer transistors MB.sub.1 to MB.sub.i.

The signals of the first and second signal generators are applied to the transmission lines l.sub.1 to l.sub.i, respectively. The first control signal .phi..sub.A of a logic "high" state is applied to the first transfer transistors MA.sub.1 to MA.sub.i, turning on the first transfer transistors MA.sub.1 to MA.sub.i. Then the signals .phi.l.sub.1 to .phi.l.sub.i in transmission lines l.sub.1 to l.sub.i are latched onto the latch circuits 30a to 30i through the channels of the first transfer transistors MA.sub.1 to MA.sub.i. Thereafter, in dependence upon the sequential application of the second control signals .phi.B.sub.1 to .phi.B.sub.i to the second transfer transistors MB.sub.1 to MB.sub.i, the differential operational amplifier 40 sequentially receives each signal of the latch circuits through the channels of the second transfer transistors MB.sub.1, to MB.sub.i, to produce the signals .phi.l.sub.1 to .phi.l.sub.i to the outside of the chip. For instance, in case the signals .phi.l.sub.1 and .phi.l.sub.2 of transmission lines l.sub.1 and l.sub.2 are of logic "low" state; and if the first control signal .phi.A is enabled, the signals .phi.l.sub.1 and .phi.l.sub.2 are transferred to the latch circuits 30a and 30b, and latched thereunto. Then if the supplying of the first control signal .phi.A is stopped and the second control signals .phi.B.sub.1 and .phi.B.sub.2 are sequentially of logic "high" states, the latched signals onto the latch circuits 30a and 30b are sequentially transferred to the register 40, through the channels of the second transistors MB.sub.1 and MB.sub.2. The output of the differential operational amplifier 40 is successively transferred to the outside of the chip. Accordingly, it can be detected whether signals from the differential operational amplifier 40 are the same as initial signals of transmission lines l.sub.1 and l.sub.2 or not. Similarly, the spot, where signal l.sub.1 has a voltage of a logic "high" state, and signal l.sub.2 is logic "low" state, can be easily found, only if the time interval of the first and second control signals is controlled so that the first control signal .phi.A is enabled and the second control signals .phi.l.sub.1 and .phi.l.sub.2 are consecutively disabled after the signals .phi.l.sub.1 and .phi.l.sub.2 of logic "low" states are completely transferred to the latch circuits 30a and 30b. Also the spot, where the signals .phi.l.sub.1 and .phi.l.sub.2 are logic "high" states can be detected. As a result, by using the internal signal detector comprised of the latch circuits and register, the defects of the first and second signal generating circuits 10 and 20 can be easily detected at outside of the chip.

Therefore, the defects of the circuit in the chip can be easily checked by using a monitor, etc., for example. Further, the internal signal detector is suitably laid out on a vacant space, in the chip by in parallel, connecting an internal signal detector to the any transmission lines applied to a predetermined signal.

In the circuit of FIG. 3, first and second control signals .phi.A, .phi.B as one predetermined voltage and the sequentially generated voltage by using a delay circuit, are supplied from the inside or the outside of the chip. The first and second control signals can be easily applied to the first and second transfer transistors, respectively. Moreover, the latch circuits and shift register can be adjusted in appropriate number according to the layout of the chip.

As described above, the defects of the internal signal can be detected within a short time. Therefore, when, because of a complication of an internal circuit, it is difficult to know the operation of each circuit signal thereof, the internal signal detector according to the present invention is effective as if the probing is performed on a PCB (Printed Circuit Board) by analyzing data.

While the invention has been particularly shown and described with reference to the preferred embodiment of the present invention thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the spirit and scope of the present invention.