Microprocessor With an Exclusive Address Terminal for Selecting at Least One Part of a Peripheral Device

The present invention relates to a digital electronic circuit device with a CPU and, in particular, to a digital electronic circuit device provided with a CPU having multiplexed address/data terminals which are capable of outputting address signals and data signals by means of time-sharing.

Conventionally, in order to supply data and address signals from a CPU to a peripheral circuit, there are provided an external address latch and a multiplexed address/data bus connected with the CPU. The multiplexed address/data bus is used for transferring both data signals and lower address signals in a time-sharing manner with the address latch temporarily storing the lower address signals. Thus, a peripheral circuit receives upper address signals directly supplied from the CPU and lower address signals from the address latch.

During program development, a detachable external ROM is used as a program memory for a CPU when a program is likely to contain many bugs. After the program is finalized, the external ROM is connected in the conventional circuit device as described above.

A digital electronic circuit device first proposed by the inventor of the present invention (who was under an obligation to assign the subject matter of FIGS. 3 and 4 to the assignee of the present invention) is constructed as shown in FIG. 3. A multiplexed address/data bus 8 is connected between a peripheral element 3 and multiplexed address/data terminals A0.about.A7, D0.about.D7 of a CPU 1. An address bus 7 is connected between an address terminal A13 of the CPU 1, exclusively used for an address signal, and a chip-select terminal CS the peripheral element 3. An address latch 4 together with a detachable external ROM 2 (Electrically Programmable ROM) are connected to the multiplexed address/data bus 8, and an output-enable terminal OE of the address latch 4 is connected to the address terminal A13 of the CPU 1 through the address bus 7. After the address latch 4 has held lower address signals, given from the CPU 1 through the multiplexed address/data bus 8, for a required period, the latch 4 outputs the lower address signals to the external ROM 2 through an address bus 9. Latch 4 also outputs a part of the lower address signals to address terminals A0, A1 of the peripheral element 3, through an address bus 11. The external ROM 2 outputs its stored data signals to the multiplexed address/data bus 8, through a data bus 10 when the ROM 2 receives the lower address signals, outputted from the address latch 4 through the address bus 9, and upper address signals, outputted from exclusive address terminals A8.about.A12 of the CPU 1 through an address bus 6.

When a program for the CPU 1 is debugged, the external ROM 2 may be replaced by a masked ROM internal to a CPU, in which the revised program is written in a process of producing the CPU. The external ROM 2 can be removed without affecting other circuits. However, it is impossible to remove address latch 4 because the address bus 11, connected with the address terminals A0, A1 of the peripheral element 3, is connected with the multi-plexed address/data terminals A0.about.A7, D0.about.D7, through the address latch 4 and the multiplexed address/data bus 8.

FIG. 4 shows a digital electronic circuit device wherein the CPU 1 shown in FIG. 3 is replaced with a CPU 21 equipped inside with a masked ROM 22 and the external ROM 2 has been removed. The address latch 4 remains only for holding address signals to be supplied to the peripheral element 3. Consequently, it is difficult to decrease the number of circuit elements and the number of assembling processes, so that the digital electronic circuit device may not be produced at a lower cost.

Accordingly, it is an object of the present invention to provide a digital electronic circuit device capable of being produced with the least number of circuit elements and at greatly reduced cost.

In order to accomplish the above-mentioned object, the digital electronic circuit device according to the present invention comprises: central processing unit having plural terminals including a multiplexed terminal capable of outputting an address signal and a data signal in a time-sharing manner; peripheral device for receiving at least one of the address signal and data signal from the central processing means the peripheral, unit having a data terminal and an input terminal, an operational state of the peripheral device being changed in response to a signal inputted through the input terminal; first bus unit for connecting the multiplexed terminal with the data terminal; and second means for connecting the input terminal with a terminal of the plural terminals of the central processing unit other than the multiplexed terminal.

In the digital electronic circuit device having the foregoing construction, the second bus unit transfers a signal from a terminal of the plural terminals, other than the multiplexed terminal, directly to the input terminal of the peripheral device. The peripheral device is enabled and set to a required operational state by the signal supplied to the input terminal.

An external memory and an address latch are used while a program for the central processing means is likely to contain many bugs. The address latch temporarily stores an address signal supplied from the multiplexed terminal through the first bus unit. External memory, storing the program, is addressed based on the address signal stored in the address latch. Data signals or command signals from the external memory are supplied to the central processing unit, or the peripheral device, through the first bus unit.

After a program is debugged, the central processing unit may be fabricated with an internal masked memory storing the revised program. In this case, both the external memory and the address latch can be removed without affecting the peripheral device. Thus, the number of circuit elements can be decreased, making it possible to produce a digital electronic circuit device at a lower cost.

The above and other objects, features and advantages of the present invention will become more apparent from reading the following description of the preferred embodiments taken in connection with the accompanying drawings in which:

FIG. 1 is a block diagram showing a construction of an embodiment of a digital electronic circuit device according to the present invention;

FIG. 2 is a block diagram showing a digital electronic circuit device which has an external ROM and an address latch removed from the digital electronic circuit device shown in FIG. 1;

FIG. 3 is a block diagram showing a construction of a digital electronic circuit device proposed prior to the present invention; and

FIG. 4 is a block diagram showing a digital electronic circuit device which has an external ROM removed from the digital electronic circuit device shown in FIG. 3.

Referring to the accompanying drawings, an embodiment of the digital electronic circuit device according to the present invention will now be explained with reference to FIGS. 1 and 2.

As shown in FIG. 1, CPU 31 (central processing unit) is provided with multiplexed address/data terminals A0.about.A7, D0.about.D7 capable of outputting or receiving 8 bit lower address signals and 8 bit data signals in a time-sharing manner. Further the CPU 31 has exclusive address terminals A8.about.A12 for outputting 5 bit upper address signals and an exclusive address terminal A13 for outputting a one bit address signal. An expansion port 33 having three ports A, B, C is equipped as a peripheral element. The expansion port 33 is provided with exclusive address terminals A0, A1 for receiving 2 bit address signals, a chip-select terminal CS, and data terminals D0.about.D7 for outputting or receiving 8 bit signals. A multiplexed address/data bus 38 is connected between the multiplexed address/data terminals A0.about.A7, D0.about.D7 of the CPU 31 and the data terminals DO.about.D7 of the expansion port 33. An address bus 37 is connected between the address terminal A13 of the CPU 31 and the chip-select terminal CS of the expansion port 33.

When a program for the CPU 31 is likely to contain many bugs an external ROM 32 and an address latch 34 are used as shown in FIG. 1. The external ROM 32 is detachably connected to the multiplexed address/data bus 38 through a memory connector 41. The address bus 37 connects the address terminal A13 of the CPU 31 with an output-enable terminal OE of the address latch 34. The address latch 34 is adapted to output the lower address signals to the external ROM 32 through an address bus 39, after the address latch 34 has held the lower address signals, supplied through the multiplexed address/data bus 38, for a required period. The external ROM 32 outputs desired data signals to the multiplexed address/data bus 38 through a data bus 40 when receiving the lower address signals, outputted from the address latch 34 through the address bus 39, and the upper address signals, outputted from the address terminals A8.about.A12 of the CPU 31 through an address bus 36.

An address bus 35 connects two terminals A8, A9 of the address terminals A8.about.A12 of the CPU 31 with the address terminals A0, A1 of the expansion port 33. Further, in this embodiment, addresses .0..about.1FFF, presented by 14 bit address signals outputted from the multiplexed address/data terminals A0.about.A7, D0.about.D7 and the address terminals A8.about.A13, are allotted to the external ROM 32. Four addresses, 20XX, 21XX, 22XX and 23XX, presented by the 14 bit address signals are allotted to three ports A, B, C and a control word register (not shown) equipped inside the expansion port 33, respectively, wherein X presents an arbitrary number between .0. and F in hexadecimal. If address signals presenting address 20XX are outputted from the address terminals A0.about.A13 and the address terminals A0, A1 of the expansion port 33 receive 2 bit signals of "00" from the address terminals A8, A9, through the address bus 35, then the port A is selected among three ports A, B, C of the expansion port 33. Likewise, selection of port B or C is performed by 2 bit signals of "10" or "01" inputted to the address terminals A0, A1 of the expansion port 33. In addition, the control word register is selected by 2 bit signals of "11, inputted to the address terminals A0, A1, to store a command for setting an operational state of three ports A, B, C to either an input state or an output state.

The construction of the circuit device shown in FIG. 1 makes it convenient to replace the external ROM 32 by another external ROM storing a revised program for the CPU 31. When a program for the CPU 31 has been completed with few bugs, as shown in FIG. 2, the CPU 31 is replaced with a CPU 51 equipped internally with a masked ROM 52 storing the completed program. In addition, since the external ROM 32 is substituted by the masked ROM 52, the external ROM 32 and the memory connector 41 are removed. The address latch 34 is also removed because no output terminal of the address latch 34 is connected with the expansion port 33.

In a digital electronic circuit device shown in FIG. 2, the CPU 51, like the CPU 31, is provided with multiplexed address/data terminals A0.about.A7, D0.about.D7, and two groups of exclusive address terminals, A8.about.A12 and A13. Like the circuit device shown in FIG. 1, the multiplexed address/data bus 38 connects the multiplexed address/data terminals A0.about.A7, D0.about.D7 of the CPU 51 with the data terminals D0.about.D7 of the expansion port 33. The address bus 35 connects two terminals A8, A9 of the address terminals A8.about.A12 of the CPU 51 with the exclusive address terminals A0, A1 of the expansion port 33. The address bus 37 connects the address terminal A13 of the CPU 51 with the chip-select terminal CS the expansion port 33.

The CPU 51 has the multiplexed address/data terminals A0.about.A7, D0.about.D7. However, it outputs no address signal to the multiplexed address/data bus 38, through the multiplexed address/data terminals A0.about.A7, D0.about.D7, because the masked ROM 52 is inside the CPU 51. The other operations of the CPU 51 for controlling the expansion port 33 are similar to that of the CPU 31.

In the foregoing embodiment, the address bus 35 connects two terminals A8, A9 of the address terminals A8.about.A12 of the CPU 31 or the CPU 51 with the address terminals A0, A1 of the expansion port 33. Alternatively, the address bus 35 may connect the address terminals A0, A1 with any terminals of the CPU 31 or the CPU 51 other than the multiplexed address/data terminals A0.about.A7, D0.about.D7.

It should be understood that the present invention is not limited to the above description, but is subject to modifications, alterations and equivalent arrangements within the scope of the appended claims. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent from the above teachings that numerous modifications may be made thereto without departing from the spirit and scope of the invention.