Output Circuit of Semiconductor Memory Device

1. Field of the Invention

The present invention relates generally to output circuits of semiconductor memory devices and, more particularly, to an output circuit for providing data read from a storage element such as a dynamic random access memory (hereinafter referred to as DRAM) to an output terminal.

2. Description of the Background Art

FIG. 4 is a schematic block diagram showing an overall structure of a conventional DRAM. Referring to FIG. 4, address signals applied as an input to address input terminals A.sub.0 -A.sub.9 are stored in an address buffer 1 and then applied to a column decoder 2 and a row decoder 3. Column decoder 2 specifies a column address of a memory cell 5, while row decoder 3 specifies a row address of memory cell 5. Memory cell 5 responds to a read/write specifying input to read data from an addressed memory cell or write data into the memory cell. More specifically, when data reading is specified, data is read from a corresponding address through a sense refresh amplifier and I/O controller 4 and is then output through a data output buffer 8. When data writing is specified, data provided as an input to a data input buffer 7 is written through sense refresh amplifier and I/O controller 4 into a specified address in memory cell 5. A clock generating circuit 6 responds to a column address strobe signal CAS and a row address strobe RAS to generate a clock signal required therein.

FIGS. 5 and 6 are electric circuit diagrams each showing one example of the data output buffer shown in FIG. 4. FIG. 7 is an input/output waveform diagram of the data output buffers shown in FIGS. 5 and 6.

In a data output buffer 8a shown in FIG. 5, n channel transistors 82 and 83 are connected in series between a power source +V and ground, and a signal .phi..sub.1 determined on the basis of the data read from memory cell 5 shown in FIG. 4 is applied to an input of an inverter 81 and also a gate of n channel transistor 83. The signal inverted in inverter 81 is applied to a gate of n channel transistor 82. Data is output through an output terminal 84 from a connection point between a source of n channel transistor 82 and a drain of n channel transistor 83.

In a data output buffer 8b shown in FIG. 6, a p channel transistor 85 is provided in place of inverter 81 and n channel transistor 82 shown in FIG. 5.

In data output buffers 8a and 8b shown in FIGS. 5 and 6, a signal .phi..sub.1 is determined on the basis of the data read from memory cell 5, and when this signal .phi..sub.1 is input to data output buffers 8a and 8b, a signal Dout is output through output terminal 84. At this time, as shown in FIG. 7, the waveform of output signal Dout often becomes abnormal due to mismatching of impedance with an external circuit. Such a phenomenon is normally called a ringing.

As described above, in the conventional DRAM, the waveform abnormality (ringing) often occurs in output signal Dout, whereby troubles often occur in a system including such a DRAM. Especially, in recent years, there is a tendency that the number of output signals increases as 1 .fwdarw. 4 .fwdarw. 8 .fwdarw. 16 . . . with an increase in storage capacity and that allowable margins decrease with an increase in operation speed of the system. Thus, the ringing has become a great problem.

A principal object of the present invention is therefore to provide an output circuit of a semiconductor memory device in which ringing can be suppressed.

Briefly, the present invention is directed to an output circuit of a semiconductor memory device for providing data read from a storage element to an output terminal. In this output circuit, outputs of a plurality of switching circuitry are commonly connected to an output terminal; the magnitude of a load connected to this output terminal is determined on the basis of the gradient of leading edges of data provided to the output terminal; and the switching circuitry corresponding in number to the determined magnitude of the load are rendered conductive in response to application of the data read from the storage element.

Accordingly, in accordance with the present invention, if the number of the switching circuitry which are rendered conductive on the basis of the magnitude of the load is varied, a rise time and a fall time of an output waveform can be maintained at a constant time on the basis of impedance of an external load connected to the output terminal. Thus, such abnormality of output signals as ringing can be suppressed.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is an electric circuit diagram of one embodiment of the present invention;

FIG. 2 is a timing chart provided upon initial value setting;

FIG. 3A is a timing chart provided in the case where a load is large and an output signal Dout is distorted;

FIG. 3B is a timing chart provided in the case where a load is small and an output signal Dout rises early, so that ringing is produced;

FIG. 4 is a schematic block diagram of an overall structure of a conventional DRAM to which the present invention is applied;

FIGS. 5 and 6 are circuit diagrams of conventional data output buffers; and

FIG. 7 is an input/output waveform diagram of a conventional data output buffer.

An output circuit shown in FIG. 1 is incorporated in data output buffer 8 shown in FIG. 4. Referring to FIG. 1, a signal .phi..sub.1 determined on the basis of data read from a memory cell 5 is applied to a control circuit 9. Control circuit 9 includes an inverter 91 and NOR gates 9.sub.A, 9.sub.B and 9.sub.C. Signal .phi..sub.1 is inverted in inverter 91 and then applied to one input terminal of each of NOR gates 9.sub.A, 9.sub.B and 9.sub.C. Respective outputs .phi..sub.A -.phi..sub.C of NOR gates 9.sub.A, 9.sub.B and 9.sub.C are applied to respective gates of n channel MOS transistors Q.sub.A, Q.sub.B and Q.sub.C. Respective drains of n channel MOS transistors Q.sub.A, Q.sub.B and Q.sub.C are connected to a power source +V, and their respective sources are connected to an output terminal 84. An output signal Dout output through output terminal 84 is applied to comparison circuits 10.sub.A, 10.sub.B and 10.sub.C. A set signal .phi..sub.2 output from clock generating circuit 6 shown in FIG. 4 is applied to comparison circuits 10.sub.A, 10.sub.B and 10.sub.C. Also, comparison circuits 10.sub.A, 10.sub.B and 10.sub.C are supplied with reference voltages Vref.sub.A, Vref.sub.B and Vref.sub.C of different levels, respectively. Comparison circuits 10.sub.A, 10.sub.B and 10.sub.C make a comparison between gradient portions of leading edges of signal .phi..sub.1 and reference voltages Vref.sub.A -Vref.sub.C, respectively, so as to determine the magnitude of a load connected to output terminal 84 on the basis of the degree of the gradient. Respective outputs .phi..sub.A ', .phi..sub.B ' and .phi..sub.C ' of comparison circuits 10.sub.A, 10.sub.B and 10.sub.C are applied to respective other input terminals of NOR gates 9.sub.A, 9.sub.B and 9.sub.C.

A power-on reset circuit 12 detects the rise of a supply voltage Vcc and applies an initial value set signal .phi.3 to each of comparison circuits 10.sub.A, 10.sub.B and 10.sub.C and also to a register circuit 13. Register circuit 13 stores in advance initial values for comparison circuits 10.sub.A, 10.sub.B and 10.sub.C. Register circuit 13 responds to initial value set signal .phi.3 applied from power-on reset circuit 12 to apply initial value signals .phi..sub.4A, .phi..sub.4B and .phi..sub.4C to comparison circuits 10.sub.A, 10.sub.B and 10.sub.C, respectively. Comparison circuits 10.sub.A, 10.sub.B and 10.sub.C respond to initial value set signal .phi.3 to apply initial value signals .phi..sub.4A, .phi..sub.4B and .phi..sub.4C to NOR gates 9.sub.A, 9.sub.B and 9.sub.C, respectively.

FIG. 2 is a timing chart provided upon initial value setting according to one embodiment of the present invention; FIG. 3A is a timing chart provided when a load is large; and FIG. 3B is a timing chart provided when the load is small.

A detailed operation of one embodiment of the present invention will now be described with reference to FIGS. 1 to 3B. A description will first be made on an operation of setting an initial value with reference to FIG. 2. With a power source turned on, if power-on reset circuit 12 detects the rise of supply voltage Vcc as shown in FIG. 2(a), then circuit 12 generates an initial value set signal .phi..sub.3 of a logic high level to apply the same to comparison circuits 10.sub.A, 10.sub.B and 10.sub.C and register circuit 13 as shown in FIG. 2(b). Register circuit 13 responds to initial value set signal .phi..sub.3 to individually apply respective initial value data .phi..sub.4A, .phi..sub.4B and .phi..sub.4C shown in FIG. 2(c), (d) and (e) to respective comparison circuits 10.sub.A, 10.sub.B and 10.sub.C. Comparison circuits 10.sub.A, 10.sub.B and 10.sub.C respond to initial value set signal .phi..sub.3 to set initial value data .phi. .sub.4A, .phi..sub.4B and .phi..sub.4C. Since these initial value data .phi..sub.4A, .phi..sub.4B and .phi..sub.4C are in a logic high level ("H"), a logic high level ("H") and a logic low level ("L"), respectively, respective outputs .phi.'.sub.A, .phi.'.sub.B and .phi.'.sub.C of comparison circuits 10.sub.A, 10.sub.B and 10.sub.C attain respective logic levels of "H", "H" and "L" as shown in FIG. 3A(g), (h) and (i). NOR gates 9.sub.A, 9.sub.B and 9.sub.C make respective signals .phi..sub.A, .phi..sub.B and .phi..sub.C attain respective logic levels of "L", "L" and "H" as shown in FIG. 3A(d), (e) and (f). As a result, transistor Q.sub.C is rendered conductive. At this time, if the load connected to output terminal 84 is large, the rise of output signal Dout becomes dull as shown in FIG. 3A(b).

Output signal Dout is fed back to comparison circuits 10.sub.A, 10.sub.B and 10.sub.C. Then, if supplied with a signal .phi..sub.2 shown in FIG. 3A(c), comparison circuits 9.sub.A, 9.sub.B and 9.sub.C make a comparison between output signal Dout and reference voltages Vref.sub.A, Vref.sub.B and Vref.sub.C, respectively. Since output signal Dout is in a lower level than reference voltages Vref.sub.A, Vref.sub.B and Vref.sub.C, comparison circuits 9.sub.A, 9.sub.B and 9.sub.C cause signals .phi.'.sub.A, .phi.'.sub.B and .phi.'.sub.C to attain an "L" level.

In a normal operation cycle, if a logic high level signal .phi..sub.1 is applied as shown in FIG. 3A(a), then this signal .phi..sub.1 is inverted by inverter 91, to attain an "L" level. NOR gates 9.sub.A, 9.sub.B and 9.sub.C cause signals .phi..sub.A, .phi..sub.B and .phi..sub.C to attain an "H" level as shown in FIG. 3A(d), (e) and (f). Accordingly, transistors Q.sub.A, Q.sub.B and Q.sub.C are rendered conductive. As a result, output signal Dout rises sharply as shown in FIG. 3A(b).

Conversely, if the load connected to output terminal 84 is small, output signal Dout rises sharply as shown in FIG. 3B(b), so that ringing is produced. At this time, comparison circuits 10.sub.A, 10.sub.B and 10.sub.C compare between reference voltages Vref.sub.A, Vref.sub.B and Vref.sub.C and output signal Dout, respectively, and thus determine the relationship of Vref.sub.C <Vref.sub.B <Dout<Vref.sub.A. Accordingly, comparison circuits 10.sub.A, 10.sub.B and 10.sub.C cause signals .phi.'.sub.A, .phi.'.sub.B and .phi.'.sub.C to attain a logic low level ("L"), a logic high level ("H") and a logic high level ("H"), respectively, as shown in FIG. 3B(g), (h) and (i). When supplied with a logic high level signal .phi..sub.1, in a normal operation cycle, NOR gates 9.sub.A, 9.sub.B and 9.sub.C cause signals .phi..sub.A, .phi..sub.B and .phi..sub.C to attain a logic high level (" H"), a logic low level ("L") and a logic low level ("L"), respectively, as shown in FIG. 3B(d), (e) and (f). As a result, only transistor Q.sub.A is rendered conductive, so that the gradient of output signal Dout becomes gradual, resulting in elimination of ringing.

While three n channel MOS transistors Q.sub.A -Q.sub.C are used as transistors for outputting output signal Dout in the foregoing embodiment of FIG. 1, the number of these transistors is not limited to this, and two or more transistors may be employed and also p channel MOS transistors and n channel MOS transistors may be employed together. Alternatively, the transistors for use are not limited to MOS transistors, and bipolar transistors may be employed.

While comparison circuits 10.sub.A, 10.sub.B and 10.sub.C are supplied with external reference voltages Vref.sub.A, Vref.sub.B and Vref.sub.C, respectively in the foregoing embodiment, any voltages, the level of which can be determined in arbitrary time, may be applied.

In addition, while the countermeasure for ringing, which is taken when output signal Dout changes to a logic high level, has been described in the foregoing embodiment, the same ringing countermeasure is applicable to the case where output signal Dout changes to a logic low level.

As has been described heretofore, according to the embodiment of the present invention, since the number of transistors becoming conductive varies dependently on the magnitude of a load, a rise/fall time of an output waveform can be kept at a constant time on the basis of impedance of an external load connected to an output terminal, thereby enabling suppression of such abnormality of an output signal as ringing.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.