Variable Pulse Width Phase Detector

The present invention relates to phase detectors and more particularly to a phase detector for data recovery systems employing a variable frequency voltage controlled oscillator in a phase locked loop.

It is known that serial digital data communication receivers must be synchronized to the incoming serial data rate in order to properly recover the data. A circuit called a phase locked loop has been employed for this purpose. A phase locked loop is responsive to the data rate of the incoming serial data, and compares the timing of said incoming data to a clock pulse being generated by a voltage controlled oscillator (VCO) in the receiver. Whenever any difference in frequency or phase between these two signals is sensed, a phase error signal is generated which is used to resynchronize the VCO. Extreme stability, accuracy and speed of response to correct the VCO has become more important for the higher communications data rate of the fiber and microwave links. Several of these different types of communication links employ different data rates such as ESCON at 200 MHz and Fibre Channel Specification (ANSI X3T9.3) at 266.7 MHz. The portion of the phase locked loop which compares the incoming serial data to the VCO is called a phase detector. Prior art phase detectors could not be optimally operated over the wide frequency ranges of these applications and therefore required a different design for each application. The range of the prior art phase detectors was sensitive to frequency and pulse width so that they could not reliably operate at both the high and low frequencies in the frequency range of interest. Also, the acquisition frequency, i.e., the frequency over which lock could be reacquired if it were lost during operation, was limited.

It is the object of our invention to provide a novel phase shifter and a phase detection method and a phase detector having a constant gain region which is a fixed percentage of the period over the operative frequency range.

The above mentioned objectives are accomplished employing constant gain phase detection circuit having a wider constant gain region which is easy to implement in an integrated circuit form.

A feature of invention is the use of a plurality of the identical unit delay cells which are controllable by an analogue voltage.

A still further feature of my invention is the large range of frequencies over which it is operable.

FIG. 1 is a block diagram of prior art phase locked loops.

FIG. 2 is a block diagram of the phase locked loop of our invention.

FIG. 3 is a schematic of a unit delay of our invention.

FIG. 4 are curves explanatory of the function of the unit delay of FIG. 3.

FIG. 5 is a schematic of an embodiment of our phase detector invention.

FIG. 6 is a timing diagram of the embodiment of FIG. 5.

FIG. 7 is the circuit diagram of the unit delay of our phase detector.

With reference to FIG. 1, a simplified block diagram of a prior art phase locked loop is disclosed showing the phase detector 1' comparing the incoming serial data bit stream 5 to the bit clock from voltage controlled oscillator 3 on feedback connection 4. The phase detector develops a pair of control signals PUP and PDN which it sends to a low pass filter 2 via lines 6 and 6'. PUP and PDN stand for pump up and pump down which terms relate to charging a capacitor which stores the voltage to control the VCO. Output of the filter 2 on line 7 is sent to the VCO 3, to control it. Many schemes have been employed in the prior art and in general, the width of the constant gain region of the phase detectors, either in phase or amplitude were not constant as a function of frequency.

A block diagram of our novel phase detector 1, with reference to FIG. 2, is seen to include a pair of serially connected unit delays 20 and 21. The outputs 26 of the unit delay 21 is connected to the phase detector logic circuit 22. The output 26' of unit delay 20 is connected to the input of unit delay 21. The bit clock from VCO 3 is also connected to the phase detector logic circuit on line 4. The analogue output VCON, of the filter 2, in addition to the prior art connection 7 to the VCO, is sent via conductor 7' to the unit delays 20 and 21 on lines 25 to control their operation as will be explained subsequently. The outputs of the logic 22 are the outputs pump up (PUP) 23 and pump down (PDN) 24 connected to filter 2 as in the prior art.

With reference to FIG. 3 and FIG. 4, are disclosed the circuit block diagram of one half of the unit delay circuits 20 and 21 and the wave forms descriptive thereof. The box 30 is shown using a multiplexor symbol because the circuit in the box 30 performs a weighted addition of its inputs on input port 2 and input port 1 with the weight determined by the analogue feedback voltage VCON from the filter 2 applied to differential input 34. FIG. 4 shows how the weighting affects the overall delay of the unit delay circuit 20. FIG. 4 is an example and is drawn with the assumption that graphs 44 and 45 are the wave forms of data at the input ports 2 and 1 of the weighter/adder 30. Along the time axis, t.sub.d is the delay difference between weighter/adder ports inputs and t.sub.r is the rise time 0-100% of the data at port 1. The weighter/adder 30 as will be explained more fully subsequently, combines the voltage from ports 1 and 2 responsive to the analogue feedback VCON. The weighter/adder provides the function of multiplying the voltages at its two ports by a different factor and adding the result. Each port input contributes to the addition curve shown in graph 46 but the weighting multiplies the voltage at port one by A.alpha. and the voltage at port 2 by A(1-.alpha.) and then adds them together forming the addition curve shown in line 46. Assuming that A is a constant and .alpha., the weighting factor or modulation constant, satisfies 0.ltoreq..alpha..ltoreq.1, with reference to FIG. 4, it can be shown that: ##EQU1## Solving for t when V.sub.3 =0

Equation (4) shows that t.sub.x is a linear function of the modulation constant, .alpha., of the weighter/adder and that the slope of the rising edge of the combined curve is a combination of the voltage rise times at ports 1 and 2. This provides a variable delay depending on the value of the weighting factor.

Combinatorial logic of circuit 22 combines the bit clock, the serial bit stream 5' and 5", and the U and V output 56 and 57 of the final delay unit to derive the phase detector outputs PUP and PDN as disclosed in FIG. 5.

FIG. 5 is the logic diagram for the complete phase detector 1 of this invention including the two unit delay stages 20 and 21 and the combinatorial logic 22 to derive the PUP 23 and PDN 24. The truth table for the combinatorial logic 22 is shown in Table I.

With reference to the timing diagram of FIG. 6, the benefits of our invention become apparent. Curve 62 and 63 represents the time variation of the V output on line 57 of the unit time delay 21 and the output on lines 64 and 65 represent the U output pulses derived from line 56 output. The PUP and PDN pulses on lines 66 and 67 are the signals delivered to the filter 2, FIG. 2, which are used to correct the average voltage input to the VCO and the feedback to the phase detector. The essential and important feature of our invention is that the average of the sum of the time of PUP pulse and PDN pulse widths is one half of the VCO clock period, i.e., PUP+PDN always equals 1/2 of the clock period. This relationship is true for all frequencies over the entire large frequency range of operation of the VCO. The range of the phase detector of our invention is proportional to the ratio of the sum of pulse duration of PUP plus PDN to the time between the pulses. Since this ratio remains constant, the range is constant over frequency.

The constructional schematic details of one half of the unit time delay is disclosed in FIG. 7 in a bipolar transistor implementation. The transistors Q101, Q102 and Q103 are the buffer logic element 31 of FIG. 5. Transistors Q1, Q2 and Q11 are the buffer 32 and transistors Q3, Q4 and Q12 are the buffer 33. Each buffer contributes a delay on the order of 1 (or less) nanoseconds. Transistors Q5, Q6, Q7, Q8, Q9, Q10 and Q13 are weighter/adder circuit 30. The voltage VC-VCN across Q9 and Q10 causes these two transistors to change the amount of the total current they share and accordingly control the time delay of the output waveforms U and V of the weighter/adder as explained in conjunction with FIG. 3 and FIG. 4.

It is noted that this invention is not restricted to the particular embodiment of the phase detector disclosed but is intended to be of a scope defined by the claims. Also, while the phase detector of this invention is not limited to use with any particular type of VCO, a ring oscillator type VCO employing multiple, differential pair circuits with variable current source delay units is the most straight forward. A ring oscillator can be conveniently combined with the phase detector of this invention especially where the delay units are made from the same unit time delay cell design as the type disclosed in conjunction with this invention.