Low Power Multifunction Logic Array

The present invention relates to multifunctional and programmable digital logic integrated circuit devices.

Programmable logic devices (PLDs) form a well-known class of integrated circuits, including devices known as PALs and PLAs, which are used to provide the "glue" or logic for many electronic systems. U.S. Pat. Nos. 4,032,894; 4,124,899; 4,195,352; 4,609,986; 4,758,746; 4,847,612; 4,906,870; 4,942,319; and 4,963,768 exemplify the diversity of available PLD architectures, while illustrating the trade-offs that have been made between size, speed, power consumption and functional flexibility.

One element or component common to most PLDs is the programmable AND array. These AND arrays are generally constructed with two sets of intersecting conductive lines, referred to as input lines and product term lines, respectively. At the intersections or crossing points of input lines with product term lines are programmable switches in the form of fuses, EPROMs or EEPROMs. These switches connect selected input lines to selected product term lines. Usually the array is constructed so that the voltage on a product term line is pulled high, unless it is connected to an input line that happens to be in a low voltage state, in which case it is pulled low. A sense amplifier on an end of the product term line senses the voltage state of the line.

Power consumption in PLDs constructed with CMOS technology is made up of two components, one a continuous power consumption by the sense amplifiers which is independent of the use of the PLD (DC power), and the other, power which is only dissipated when a voltage is changing from low to high or high to low (AC power) AC power is used, not only by active gate elements, such as CMOS inverters on the input lines, and sense amplifiers, but most especially by the conductive lines themselves in the very act of charging or discharging the lines to bring them to a new voltage level Power used by the conductive lines is proportional to CV.sup.2 f, where C is the line capacitance, V is the voltage change from one state to the other, and f is the clock frequency In conventional AND array construction, with its many long conductive lines potentially switching at once, power consumption increases with the size, speed or functional flexibility of the device. Devices with programmable, rather than fixed, OR array constructions must make similar tradeoffs.

It is an object of the invention to provide a logic array architecture with lower power consumption.

It is another object of the invention to provide a programmable logic device (PLD) having a pair of logic arrays, outputs of one being connected to inputs of the other, where at least one of these arrays is programmable, which PLD is characterized by low power consumption.

These objects are met with a logic array architecture which replaces the two crossing sets of many long conductive lines, and their interconnecting switches and sense amplifiers with an arrangement of plural multibit memory elements, each having address inputs coupled to inputs of the array, and plural logic gates having inputs coupled to memory outputs. Outputs of the logic gates are coupled to outputs of the array. The memory elements are programmable by loading them with data bits, such that a specified bit is provided in a memory element's output in response to input signals received on its address inputs.

In one configuration, the inputs are organized in groups connected to decoder inputs of a set of decoders. Decoder outputs provide address signals to address inputs of the memory elements in accord with the combination of input signals received on the decoder inputs. The memory elements may be arranged in a matrix of rows and columns with each row of memory elements connected to a single decoder. Each logic gate would then be connected to only memory outputs from a single column of memory elements. Several stages of logic gates may be provided, with each gate of a first stage connected directly to a subset of memory elements in a column and each gate of a second stage connected to the outputs of the first stage of logic gates corresponding to a single column of memory elements. Logic gates may be AND, OR, NAND, NOR, XOR or XNOR gates. Programmable XOR gates may be provided on the outputs to provide selected inversion or noninversion of the output signals of the array. The arrays can have storage elements, such as registers or latches, at their inputs or outputs, or between memory outputs and logic gate inputs.

The logic array architecture may be used in a programmable logic device which is made up of two successive logic arrays, at least one of which is programmable. For example, the first array may be a programmable AND array built according to the low power architecture of the invention, and the second can be either a fixed array of OR gates or a programmable OR array. The programmable OR array can also be built according to the low power architecture of the invention. The outputs of the second array can feed back to inputs of the first or second array. At least some inputs to the second array can also be received from a source independent from the first array. Other arrangements are possible.

FIGS. 1a and 1b together form a schematic block diagram of a logic array of the present invention.

FIGS. 2a and 2b together form a schematic block diagram of a programmable logic device (PLD) of the present invention comprising the logic array of FIGS. 1a and 1b followed by a fixed OR array.

FIGS. 3a and 3b together form a schematic block diagram of a PLD of the present invention comprising the logic array of FIGS. 1a and 1b followed by a programmable OR array of similar construction to the logic array of FIGS. 1a and 1b.

FIGS. 4a and 4b together form a schematic block diagram of a PLD of the present invention illustrating a number of optional features.

FIG. 5 is a logic gate diagram of a portion of a decoder used in the logic array of FIGS. 1a and 1b and PLDs of FIGS. 2-4.

FIG. 6 is a logic gate diagram of two memory cells of a multibit memory element used in the logic array and PLDs of FIGS. 1-4.

FIG. 7 is a block diagram of a multibit memory element used in the logic array and PLDs of FIGS. 1-4 and having a single 8-bit memory without decoder and a pull-up component.

FIG. 8 is a block diagram of an alternative multibit memory element to that of FIG. 7 having two 8-bit memories without decoder, memory select means and a pull-up component.

With reference to FIGS. 1a and 1b, a logic array of the present invention includes a set of array inputs 11, here organized into groups of three. The array inputs 11 are connected to a set of decoders 13. Each of the decoders 13 has J inputs, where in this instance J=3, connected to the corresponding groups of array inputs 11. Each of the decoders 13 also has up to 2.sup.J outputs 15. In the present instance, each decoder 13 has eight outputs. As will be seen, each decoder output 15 may actually consist of two conductive lines, called word lines, one for reading and the other for writing operation.

A detail of a portion 13' of a decoder 13 is seen in FIG. 5. In general, a decoder 13 will have as many portions like portion 13' as it has outputs 15. Thus, in an eight output decoder 13 there would be eight portions constructed in a manner similar to the portion 13' shown. Portion 13' includes a logic AND gate 17 with three inputs 19. The number of inputs 19 is the same as the number J of inputs into the entire decoder 13. An inverter 21 may be present at one or more of the inputs 19 to AND gate 17. Each portion 13' of the decoder differs slightly from the others in which of the inputs 19, if any, has an inverter, such that the decoder as a whole has portions with every possible combination of inverted and noninverted inputs. The inputs 19 of each decoder portion 13' are connected to the group of corresponding inputs 11 to the decoder. Depending on the input signals applied to array inputs 11, and consequently to the decoder inputs 19, the output 23 of gate 17 of one of the decoder portions will be high. For example, the decoder portion 13' shown in FIG. 5 will provide a gate output 23 that is high only when the first and third input signals are high and the second input signal is low. The gate output 23 is connected to a read word line 25. A second AND gate 29 has a first input connected to gate output 23 and a second input connected to a write enable line 31. It provides an output to a write word line 33 whenever a write enable signal is applied to write enable line 31.

Returning to FIGS. 1a and 1b, the programmable elements in the logic array are a plurality of multibit memory elements 35. These memory elements 35 may be arranged in a matrix of rows and columns, as shown, with one row per group of inputs 11 with its decoder 13 and with one column per output bit. In such an arrangement, each decoder output 15, corresponding to a group of array inputs 11, traverses an entire row of memory elements 35, rather than simply being connected to just one memory element. As seen in FIG. 7, each memory element has a set of address inputs 37 and an output or read bit line 41. The address inputs 37 are connected to the set of decoder outputs 15, which outputs 15 then continue on to the next memory element 35 in that row. Each memory element 35 also has a write bit input 39 by which data bits may be loaded into the memory element 35 The write bit line 39 may be shared among an entire column of memory elements 35, since programming typically will occur no more than once when the array is turned on and can be done sequentially, bit by bit.

The memory elements 35 can be made of any nonvolatile memory, such as ROMs, EPROMs or EEPROMs, or alternatively can be made of a volatile memory, such as SRAMs, shift registers or latches. Nonvolatile memories are generally loaded only once when the device is first programmed, while volatile memories need to be reloaded each time the power is turned on, i.e. at run-time, since they lose their stored bits whenever the power is turned off. The source of the data bits to be loaded into these volatile memories can be either a nonvolatile memory on the chip or an external source. The source need not be fixed, but could also be selected at run-time, for example, by the state applied to one or more external contacts, such as pins, of the device or by the state of one or more memory cells.

A portion containing two memory cells 35' and 35" of one kind of multibit memory element 35 is shown in FIG. 6. A first memory cell 35' is addressed by a first pair of word lines 25' and 33' from a decoder 13 of the device, while a second memory cell 35" is addressed by a second pair of word lines 25" and 33" from the same decoder 13 of the device. The memory element 35 also includes a write bit line input 39 common to all of the memory cells 35', 35", etc. and a read bit line output 41 also common to all of the memory cells 35', 35", etc. The memory cells 35', 35", etc. in this example are latches made up of pairs of cross-coupled inverters 43' and 44', 43" and 44", etc. A data bit may be written into a memory cell 35' or 35" of the memory element 35 by applying a high logic level address signal to the corresponding write bit line 33' or 33", which activates a pass transistor 45' or 45" controlled by that write bit line, and simultaneously applying the data bit to the common write bit line 39. The data bit will be transferred from the write bit line 39 through the activated pass transistor 45' or 45" to the corresponding inverter pair 43' and 44', or 43" and 44". Reading a memory cell 35' or 35" is done by activating a corresponding pass transistor 47' or 47" by applying a high logic level address signal on the corresponding read word line 25' or 25" from the decoder 13 of the device The selected data bit is then transferred from the corresponding inverter pair 43' and 44' or 43" and 44" through the activated pass transistor 47' or 47" onto the read bit line 41. As seen in FIG. 7, charging of the read bit line 41 is assisted by a pull-up transistor 49. The output of the memory cell 35 on read bit line 41 is typically inverted by an inverter 51. If this is the case, the inversion should be taken into account when programming the memory element 35 with the desired logic.

Returning to FIGS. 1a and 1b, the outputs from memory elements 35 connect to inputs 53 of logic gates 55, here shown as AND gates. In order to minimize the cumulative length of all the conductive lines output from the memory elements 35, the rows of memory cells 35 are here grouped into threes so that each logic gate 55 has three inputs 53 connected to three memory elements 35 in a column of such elements. The outputs 57 of the logic gates 55 are in turn connected to a second stage of logic gates 59, the outputs 57 of each column of logic gates 55 being input into a single corresponding gate 59 of that column. If there are six rows of memory elements 35 grouped into two sets of three rows, each set having a row of first stage logic gates 55, then each of the second stage logic elements 59 will have two inputs 57.

The outputs 61 of the second stage logic gates 59 may connect to a row of programmable inverters in the form of XOR gates 63. A set of one-bit memories 60, such as EPROMs, provide one input to the XOR gates 63, while the outputs 61 provide the other input The outputs of XOR gates 63 form the outputs OUTPUT.sub.1, OUTPUT.sub.2, . . . , OUTPUT.sub.n of the logic array.

With reference to FIGS. 2a and 2b, a programmable logic device of the present invention comprises two arrays with the outputs 65 of one array feeding into the inputs of the second array. The first array, a portion of which is seen in FIGS. 2a and 2b, is programmable and is constructed exactly like the logic array in FIGS. 1a and 1b, having a plurality of inputs 11 coupled to address inputs of memory elements 35 and having logic gates 55 coupled to the read bit line outputs of memory elements 35. The outputs of logic gates 55 are in turn coupled to the inputs of logic gates 57. A programmable XOR gate 63 connects to the output of each logic gate 57. As in FIGS. 1a and 1b, the logic gates 55 and 57 are shown as AND gates. The second array, seen in FIG. 2b, is a fixed function array, here shown as an array of OR gates 67. The OR gates 67 have inputs 65 connected to the outputs of programmable XOR gates 63 in some specified manner. In the present instance, each OR gate has three inputs connected to three different XOR gates. The OR gate outputs 69 form the outputs of the second array.

With reference to FIGS. 3a and 3b, another programmable logic device of the present invention also comprises two logic arrays with the outputs 65 of one array feeding into the inputs of the second array. But in this embodiment the second array is programmable like the first array. Both arrays are constructed like the logic array shown in FIGS. 1a and 1b. As before, the first array has a plurality of inputs 11 coupled through a set of decoders to address inputs of a matrix of memory elements 35. Logic AND gates 55 and 57 couple to the read bit line outputs of the memory elements 35. Programmable XOR gates 63 selectively invert or leave uninverted the outputs of AND gates 57. In this embodiment, the second array also has a plurality of inputs 65 which are the outputs of the XOR gates 63. As with the first array, the inputs 65 are grouped in threes with each group being received by a decoder 71. Decoder 71 has N (=3) inputs and up to 2.sup.N (=8) outputs 73 and may be constructed as described above with reference to FIG. 5 so as to provide an address signal on one of its outputs 73. The outputs may each consist of two conductive lines, one a read word line and the other a write word line. The second array has a matrix of rows and columns of memory elements 75, each constructed like the memory elements 35 of the first array as in FIGS. 6 and 7. The read bit line outputs 77 of the memory elements 75 form the inputs to logic gates 79, here shown as OR gates, one column of memory elements 75 per logic gate 79. The OR gate outputs 81 may form the output of the second array, or a set of programmable XOR gates 83 may receive the OR gate outputs 81 and a select signal from a nonvolatile memory bit 80 as inputs to selectively invert or not invert the signals on outputs 81. In the latter case, the XOR gate outputs 85 may form the array outputs.

With reference to FIGS. 4a and 4b, a third programmable logic device of the invention illustrates a number of options other than those set forth in FIGS. 1-3. The inputs 91 to the first array may be external contacts of the integrated circuit device, such as pins, pads, leads or some other known form of contact. Likewise, the outputs 93 of the second array can be external contacts of the device. Alternatively, the programmable logic device may be a functional unit which is completely internal to another larger circuit, in which case some or all of the inputs and outputs of the arrays may be received from other elements within the larger circuit instead of from external contacts.

Outputs 95 of the second array can be fed back into the first array to form multilevel logic, such as arithmetic logic. In the present example, decoder 97 includes inputs that are connected to outputs 95 of the second array. If desired some inputs to the second array can be inputs 99 to the multifunction programmable logic device, that are fed directly to the second array to provide a faster pass with fewer levels of logic. As shown here, input 99 is connected to an external contact 101 of the device. Alternatively, input 99 could be received from another element in a larger integrated circuit. Outputs 103 of an array may also feed back to the inputs of the same array to form a kind of latch. For instance, as shown here, decoder 105 of the second array receives an input from an output 103 of the second array. Through memory element 107, the output 103 of the first column feeds back to an input of the same first column. Through memory element 109, the output 103 of the first column also feeds back to an input of the second column of the second array. The feedback can also be connected to some intermediate stage of the decoding tree, such as decoders 111 and 113.

The matrix of memory cells in an array need not be complete. For example, in the second array seen in FIG. 4b, decoders 105 and 111 address only two and three, respectively, of the four possible columns in the matrix.

The first array, a portion of which is seen in FIG. 4a, lacks a set of programmable XOR gates at the outputs 115 of the array. However, when the second array is programmable the lack of programmable XOR gates does not result in a loss of functional flexibility, since the XOR function can be implemented in the memory elements of the second array.

The arrays can have storage elements at their inputs and outputs. In FIG. 4b, four registers are shown by way of example. One register 116 is placed after the first level of memory 109 in the second array and three registers 118, 122 and 124 are at the output of the second array. The registers can be SR registers or D, T or JK flip-flops. They can also be replaced by latches, or the storage elements can be programmable as either registers or latches. Storage elements can also be programmable to be transparent. For example, in FIG. 4 two types of registers are shown. The first type, represented by registers 116, 118 and 122 has an associated architecture memory bit 120, such as an EPROM cell, which can be used to force those registers to be transparent, so that it can be logically removed from the data path. The second type, represented by register 124, does not have this architecture bit, so that it always functions as a register. Programming is typically independent for each register or latch, as shown here, although alternatively several registers could be programmed from a single memory bit. The registers 116, 118, 122 and 124 receive a clock input signal CK. Latches would receive an equivalent enable signal on an enable input. If there are several clocks or enable sources, the particular source received by a register or latch can be selectable by programming which of the several different clock or enable sources are to be directed toward the clock or enable input. Registers need not be placed at all possible sites. For example, FIG. 4b shows registers 118, 122 and 124 at only three of the four outputs of the second array, and registers 116 at the outputs of only one memory element 109. Alternatively, there could be registers or latches at outputs of an entire row or column of memory elements or of all memory elements. Finally, the output registers 118, 122 and 124 while commonly in the form of single bit registers, could also be multibit shift registers or memory arrays. With such multibit storage elements the same function can be formed on multiple sets of data. Alternatively, different functions can be interleaved in time on the same or different sets of data, as described before. The multibit storage elements can also be forced to be transparent by architecture memory bits 120, if desired.

With reference to FIG. 8, the memory elements can have multiple selectable behaviors by forming each memory element from two or more multibit memories 117 and 119. Both memories 117 and 119 receive common address inputs 121. Each memory 117 and 119 has a separate write bit line input 123 and 125 so that they can be loaded with different data bits, and each has a separate read bit line output 127 and 129. Selection of the memory to be read may be done by a word select signal on a line 131 connecting to pass transistors 133 and 135 on respective read bit lines 127 and 129. The signal provided to the selected line 127 or 129 is passed to inverter 137 and then to the memory element output 139. A pull-up transistor 141 aids charging of the selected line 127 or 129. The selection signal on line 131 can be provided from the state of one or more external contacts of the device, or one or more memory cells or registers on the device. If both arrays have one or more memory elements with multiple selectable behaviors, the selection can be done either simultaneously or independently for each array.

The devices of the present invention dissipate very little power when not switching and significantly less than equivalent PLAs or PALs when switching, without a speed penalty.