Double-Edge Triggered Memory Device and System

1. Field of the Invention

The invention relates to digital electronic circuits, and more particularly, to synchronous circuits in which logic states are updated periodically in response to a clock signal.

2. Description of Related Art

Digital circuits are often designed for a synchronous operation. That is, they are intended to be used with a clock signal, and every time an effective edge of the clock signal occurs, the values on the outputs of the circuit are updated. The effective edge may be defined as the rising edge of the clock signal for some systems, and in other systems it may be defined as the falling edge.

Synchronous logic circuits are made up of data storage elements and combinational logic elements. The data storage elements may be any of a variety of different types of flip-flops such as D flip-flops, JK flip-flops and clocked T flip-flops. In a D flip-flop, the output is updated to equal the value which is on the D input at the time that the effective edge of the clock pulse arrives. In a JK flip-flop, the output is updated in response to the values on the J and K inputs at the time the effective edge of the clock pulse arrives, according to the following rules: If J=0 and K=0, the output remains unchanged; if J=1 and K=1, the output compliments; if J.noteq.K, the output is updated to match the value on the J input. In a clocked T flip-flop, the output remains unchanged if the T input is 0 when the effective edge of the clock pulse arrives, and toggles if the T input is high when the effective edge of the clock pulse arrives. Other types of flip-flops may also be used, and different types of flip-flops may be used in the same system.

The synchronous design philosophy for digital circuits has been generalized and formalized into what is known as the state machine model. In this model, all storage elements in a machine (which may make up part or all of a larger apparatus) are thought of as forming a "present state vector" describing the state of the machine at any given time. More specifically, assuming each storage element stores and outputs a single bit of information, the values on the outputs of all the storage elements form the present state vector of the machine being modeled.

Also in the state machine model, each storage element has one or more data inputs. A D-type storage element, for example, has only one data input, whereas a JK-type storage element has two (J and K).

The state machine model also contains "next state" circuitry, which generates a "next state vector", for applying to the storage elements. The next state circuitry or logic is a purely combinational logic circuit which generates the next state vector outputs as a purely combinational function of one or more elements of the present state vector and/or one or more separate inputs to the machine. Each output of the combinational circuitry is connected to a respective one of the inputs of the storage cells. As used herein, the "next state vector" is made up of the set of values applied to the inputs of the storage cells, even if two or more of the next state vector values are applied to each storage cell (as in the case of JK storage cells). Also as used herein, the term "combinational" can refer to a circuit as simple as a conductor or as complex as a many-level sequence of logic gates. In the state machine model, the outputs of the machine are also generated by the combinational logic circuitry as a function of the present state and/or the separate input signals. Since the term "combinational" includes a simple conductor, this model includes machines in which the outputs come directly from the outputs of one or more of the storage elements, as well as machines in which the outputs are a combinational function of the present state vector, the next state vector, and/or external inputs to the machine.

Some systems are designed using level-triggered storage elements such as latches, instead of edge-triggered storage elements such as flip-flops. In some of these systems, certain latches are transparent when the clock signal is high and opaque when the clock signal is low, and other latches are transparent when the clock signal is low and opaque when the clock signal is high. These systems require careful design to ensure that no race conditions can occur in which a change in the output of a transparent latch element propagates through combinational circuitry back to the input of the latch before the latch becomes opaque on the next clock transition.

Synchronous logic design has been used effectively for an extraordinary number of simple and complex systems. In integrated circuit design, a system may be incorporated onto one or more integrated circuit chips with the clock signal provided from an external source along a printed circuit board trace. As clock frequencies have increased, however, it has become more difficult to provide such a high frequency clock signal to the various chips. The problem is magnified on printed circuit boards because the traces begin to exhibit significant reactance at these frequencies.

In order to address this problem, some systems incorporate a phase lock loop (PLL)-based frequency doubler on-chip. Thus if the system on the chip is intended to operate at 50 MHz, for example, the external circuitry need only provide a 25 MHz clock signal which is then doubled by the PLL in order to generate the clock signal for the storage cells on the chip. The use of PLLs is disadvantageous, however, since they typically require the addition of a capacitor and a resistor off-chip, thereby increasing the component count and pin usage.

According to the invention, roughly speaking, a synchronous machine is designed using a double-edge triggered memory cell which updates its output on both the rising and falling edges of a clock input.

The invention will be described with respect to particular embodiments thereof, and reference will be made to the drawings, in which:

FIG. 1 is a block diagram of a model of a synchronous state machine;

FIG. 2 is a logic level detail of one of the storage cells of FIG. 1;

FIG. 3 is a timing diagram illustrating the operation of the cell of FIG. 2;

FIGS. 4 and 6 are transistor-level schematics of D flip-flops which may be used in the cell of FIG. 2;

FIGS. 5 and 8 are transistor-level schematics of multiplexers which may be used in the cell of FIG. 2; and

FIG. 7 defines a symbol used in FIG. 6.

FIG. 1 shows a block diagram of a model for a synchronous state machine. It comprises two basic portions: one or more storage cells 12, and combinational logic circuitry 14. Each of the storage cells 12 has a Q output, a clock input, and at least one data input. The storage cells in FIG. 1 are shown as D-type storage cells, for which each cell has a single data input D. It will be understood, however, that other types of storage cells may be used in the model.

The Q outputs of each of the storage cells 12 is connected to a respective q.sub.l input to the combinational logic circuitry 14, and the D input of each of the storage cells 12 is connected to receive a respective d.sub.l output of the combinational logic circuitry 14. The combinational logic circuitry 14 further has a plurality of external inputs x.sub.l and generates a plurality of external outputs z.sub.l. The figure shows a total of n Q outputs being provided to the combinational logic circuitry 14 and the same number n outputs of the combinational logic circuitry 14 being provided back to the D inputs of the storage cells 12, but it will be understood that these two quantities need not be the same if some of the storage cells 12 are of a different type with a different number of data inputs. Similarly, FIG. 1 shows a total of l z.sub.l outputs, and m x.sub.l inputs. Since as used herein a combinational logic path can consist of a simple conductor, the model of FIG. 1 describes both the type of machine in which input signals are provided to the D inputs of the storage cells 12 either directly or via logic gates, and machines in which the z.sub.l outputs of the combinational logic circuitry 14 are provided either directly from the Q outputs of the storage cells 12 or via logic gates.

FIG. 2 shows a logic level diagram of one of the storage cells 12 of FIG. 1. It will be understood that the individual logic blocks depicted in FIG. 2 need not be separate logic blocks in actual implementation, since delay and/or space savings may be achievable by combining some of the functions of different ones of these logic blocks together.

As mentioned with respect to FIG. 1, each storage cell 12 has a D input 30, a clock input 32 and a Q output 34. The D input 30 is connected to the D input of a conventional D flip-flop 36, and also to the D input of a conventional D flip-flop 38. The clock input 32 is connected to the clock input of the flip-flop 36, and via an invertor 40, to the clock input of the flip-flop 38. The Q output of flip-flop 36 (identified as Q.sub.A) is connected to the "0" input of a multiplexer 42, and the Q output of the flip-flop 38 (identified as Q.sub.B) is connected to the "1" input of the multiplexer 42. The output of invertor 40 is connected to the select ("S") input of the multiplexer 42, and the Q output of the multiplexer 42 is the Q output 34 of the storage cell 12. The flip-flops 36 and 38 are each rising edge-triggered flip-flops in this embodiment.

FIG. 3 is a timing diagram which may be used to understand the operation of the storage cell of FIG. 2. As shown in FIG. 3, assume that the clock signal arriving on line 32 (FIG. 2) is square wave having an alternating sequence of rising and falling edges. Furthermore, assume that a rising edge occurs in the clock signal at a time T.sub.1. At that time T.sub.1, assume that the signal on the D input 30 of the storage cell 12 is at a logic 0. Since both the clock and D signals are connected directly to the clock and D inputs of D flip-flop 36, the output of flip-flop 36 will change from its previous state to a logic 0 on the rising edge of the clock signal at T.sub.1. This is shown on the timing diagram line labeled Q.sub.A. As will be seen, the output Q.sub.A will not change again until the next rising edge at time T.sub.2.

At time T.sub.1.5, a falling edge of the clock signal arrives on line 32. This signal is inverted by invertor 40 and provided to the clock input of flip-flop 38, thereby causing the flip-flop 38 to-load in the value on the D input 30 at time T.sub.1.5. Again, assuming D is still at a logic 0 level at time T.sub.1.5, the output Q.sub.B of flip-flop 38 will change to logic 0 at time T.sub.1.5. This is reflected on the line labeled Q.sub.B on the timing diagram of FIG. 3.

Now assume that at some time after T.sub.1.5 and before the next rising edge of the clock signal at T.sub.2, the D input 30 to the storage cell 12 changes to a logic 1 and remains there until some time between T.sub.2 and T.sub.2.5. As shown in FIG. 3, this will be reflected in the Q.sub.A output of flip-flop 36 at time T.sub.2 and will not be reflected in the Q.sub.B output of flip-flop 38 at all since no falling edge of the clock signal 32 arrives while the D input is high.

At time T.sub.2.5, the clock signal 32 has a falling edge. The Q.sub.B output of flip-flop 38 does not change from a logic 0 at this time, since the D input 30 is now at a logic 0. At time T.sub.3, the D input 30 is still at a logic 0, thereby loading a 0 into flip-flop 36. The next falling edge of the clock signal 30 occurs at time T.sub.3.5, at which time the D signal 30 is high, and a logic 1 is loaded into the flip-flop 38 as shown on the Q.sub.B line of the timing diagram of FIG. 3.

This process continues with the Q. output of flip-flop 36 changing in response to the level that the D input 30 is at when each rising edge of the clock signal 32 arrives, and the output Q.sub.B changing in response to the level that the D input is at when each falling edge of the clock pulse 32 arrives.

As shown in FIG. 2, the select input S of multiplexer 42 is connected to the output of invertor 40 and therefore receives the same inverted clock signal that is provided to the clock input of flip-flop 38. Thus, whenever the clock signal 32 is high, the multiplexer 42 will provide the signal Q.sub.A on the Q output 34 of the storage cell 12, and whenever the clock signal 32 is low, the multiplexer 42 will provide the signal Q.sub.B on the Q output 34 of storage cell 12. Accordingly, between time T.sub.1 and time T.sub.1.5, when the clock signal 30 is high, the Q output of storage cell 12 changes to reflect the value which Q.sub.A is changing to at that time. Between time T.sub.1.5 and T.sub.2, the multiplexer selects Q.sub.B, which is also 0. Thus, as shown on the line labeled Q on the timing diagram of FIG. 3, the Q output 34 goes low at time T.sub.1 and stays low until time T.sub.2. Between times T.sub.2 and T.sub.2.5, the clock signal 30 is high, and the multiplexer 42 selects Q.sub.A onto the Q output 34. Since Q.sub.A is high at this time, Q also goes high at this time. Between times T.sub.2.5, and T.sub.3, the clock signal 32 is low and the multiplexer 42 selects Q.sub.B. Since Q.sub.B is low at this time, the Q output 34 also goes low.

At time T.sub.3, the clock signal 32 goes high again and the multiplexer 42 selects Q.sub.A. But since Q.sub.A goes low at T.sub.3, the Q output 34 of the storage cell 12 remains low until T.sub.3.5. At that time, the multiplexer 42 selects Q.sub.B which has just gone high. The Q output 34 therefore goes high at time T.sub.3.5.

It can be seen that the Q output 34 of the storage cell 12 can change on every half cycle of the clock signal 32, thus effectively doubling the frequency at which the state machine of FIG. 1 can operate relative to the frequency of the clock signal. It should be noted that the circuits which make up the flip-flops 36 and 38 and the multiplexer 42 should be designed carefully to minimize any switching transients which may occur.

FIG. 4 is a transistor level schematic diagram of a conventional "stacked invertor" type D flip-flop which may be used to implement the flip-flops 36 and 38 in FIG. 2. The operation of the circuitry of FIG. 4 is conventional and need not be explained herein.

FIG. 5 is a transistor level schematic diagram of a conventional "stacked invertor" type multiplexer which may be used to implement the multiplexer 42 shown in FIG. 2. The operation of the circuitry of FIG. 5 is conventional and need not be explained herein.

FIG. 6 is a transistor level schematic diagram of a conventional "pass gate" type flip-flop which may be used to implement the flip-flops 36 and 38 in FIG. 2. The operation of the circuitry of FIG. 6 is conventional and need not be explained herein. FIG. 7 illustrates the transistor makeup of the "pass gate" symbol used in FIG. 6.

FIG. 8 is a transistor level schematic diagram of a conventional "pass gate" type multiplexer which may be used to implement the multiplexer 42 of FIG. 2. The operation of the circuitry of FIG. 8 is conventional and need not be explained herein.

As previously mentioned, the structure of the storage cell 12 at the transistor level may be optimized by merging some of the functions of the various logic level components shown in FIG. 2.

The invention has been described with respect to particular embodiments thereof, and it will be understood that numerous modifications are possible within its scope.