Analog-to-Digital Conversion Method and Apparatus With a Controlled Switch for High-Speed Conversion

The present invention relates to analog-to-digital (AD) converters and more particularly to techniques for fabrication of multi-step AD converters and analog switches which are formed on MIS type or MOS type semiconductor integrated circuit devices, especially, the technique used for converting a high-speed analog signal such as a video signal into a digital signal in, for example, digital televisions, video cassette recorders and video tape recorders.

Two-step CMOS AD converters are disclosed in JP-A-63-157522, "A CMOS 40 MHz 8 b 105 mW Two-Step ADC" by N. Fukushima et al, ISSCC 89/WEDNESDAY, FEB. 15, 1989/WEST GRAND BALLROOM, pp. 14-15, "An 8-b 50-MHz 225-mW SUBMICRON CMOS ADC USING SATURATION ELIMINATED COMPARATORS" by T. Matsuura et al. IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp. 6.4.1.-6.4.4.

A presupposition required for correct conversion to be performed in the two-step or sub-flash ADC is that an analog signal to be converted into upper bit data is the same as an analog signal to be converted into a lower bit data. In other words, an analog signal to be sampled and held for comparison by means of upper sample-and-hold circuits must be the same as an analog signal to be sampling and held for comparison by means of lower sample-and-hold circuits.

Practically, however, the timing for an analog signal to be sampled by the upper sample-and-hold circuits cannot perfectly coincide with the timing for the analog signal to be sampled by the lower sample-and-hold circuits because of a difference in edge shift between sampling clocks due to unevenness in transfer characteristics and circuit constants. Therefore, there is a very slight difference between the timings for sampling by the upper sample-and-hold circuits and lower sample-and-hold circuits and even within this time difference, the analog signal such as a video signal whose level changes at a very high rate will change greatly in its level. Consequently, the level of the analog signal sampled and held for comparison by the upper sample-and-hold circuits and lower sample-and-hold circuits is different for the two types of sample-and-hold circuits and hence continuity between the upper bit data and lower bit data cannot be ensured, resulting in conversion errors.

An object of the invention is to provide a technique of performing highly precisely at a high speed the AD conversion to be effected by using the mutually separated upper bit data and lower bit data.

Another object of the invention is to provide a two-step AD converter (ADC) in which an input signal for AD conversion of the upper bit data coincides with an input signal for AD conversion of the lower bit data.

Still another object of the invention is to provide an analog signal sampling circuit capable of permitting high-speed operation of the multi-step ADC.

Still another object of the invention is to provide a video signal processing apparatus which can realize high-speed and highly precise AD conversion.

Still another object of the invention is to provide a compensator incorporated into a MIS sub-flash AD converter and operable to compensate for signal offset so as to realize high-speed and highly precise AD conversion.

According to the invention, an analog signal is applied to a plurality of AD converters to be processed into upper bit data and lower bit data so as to effect AD conversion of the analog signal by using the mutually separated upper bit data and lower bit data, and the application of the analog signal to the plurality of AD converters is collectively controlled by means of a common analog switch.

With the above construction, the AD conversion input for the upper bit data can accurately coincide with the AD conversion input for the lower bit data.

A cascade connection of transistors which is connected to the common analog switch can decrease or compensate for offset of the input signal.

FIG. 1 is a circuit diagram showing an embodiment of an AD converter to which the technique of the invention is applied;

FIG. 2 is a timing chart shorting an example of operation of the essential part of the AD converter shown in FIG. 1;

FIG. 3 is a circuit diagram showing another embodiment of the AD converter according to the invention;

FIG. 4 is a timing chart showing an example of operation of the essential part of the AD converter shown in FIG. 3;

FIG. 5 is a graph exemplifying the effect of a voltage offset compensator according to the invention;

FIG. 6 is a circuit diagram showing an example of construction of a video signal processing apparatus according to the invention; and

FIG. 7 is a circuit diagram showing a still another embodiment of the subflash AD converter according to the invention.

In the accompanying drawings, identical reference characters designate identical or like parts.

FIG. 1 shows an embodiment of an AD converter to which the technique characteristic of the present invention is applied. The circuit of the FIG. 1 converter may be formed on a semiconductor substrate of, for example, silicon signal crystal by using the known CMOS fabrication technique.

The AD converter shown in FIG. 1 is a two-step AD converter receiving an input analog signal Vin. The two-step AD converter comprises upper comparators 1-1 to 1-m, ganged into an upper comparator set designated by reference numeral 1, for comparing reference voltages VH-1 to VH-m corresponding to upper bit data DoH with the analog signal Vin in parallel, upper sample-and-hold circuits 2-1 to 2-m ganged into a set designated by reference numeral 2 and provided in association with the individual comparators to sample and hold, in respect to each comparator, the analog signal Vin applied for comparison to the comparators 1, an upper encoder 3 for encoding results of comparison at the upper comparators 1 into binary codes and holding the binary codes temporarily, lower comparators 4-1 to 4-n, ganged into a lower comparator set designated by reference numeral 4, for comparing reference voltages VL1 to VLn corresponding to lower bit data DoL with the analog signal Vin in parallel, lower sample-and-hold circuits 5-1 to 5-n ganged into a set designated by reference numeral 5 and provided in association with the individual comparators to sample and hold, in respect of each comparator, the analog signal Vin applied for comparison to the comparators 4, a lower encoder 6 for encoding results of comparison at the lower comparators 4 into binary codes, a reference voltage generator 7 for generating the reference voltages VH-1 to VH-m of upper comparators 1 and the reference voltages VL-1 to VL-n of lower comparators 4, an analog switch Sm, provided in common to the upper and lower sample-and-hold circuits 2 and 5, for collectively switching and controlling the analog signal Vin, about to branch and proceed to the upper and lower sample-and-hold circuits 2 and 5, in advance of the branching, and a control signal generator 8 for generating sampling clocks .phi.s2 and .phi.s5 of the sample-and-hold circuits 2 and 5 and a control clock .phi.m of the common analog switch Sm. On the basis of the output results of the upper comparators, the generator 7 sets the lower reference voltages for the two-step operation of sub-flash AD converter. Denoted by 81 are buffer circuits. By operating the upper comparators 1 and lower comparators 4 sequentially, a digitally converted output Dout measuring DoH+DoL corresponding to the analog signal Vin can be obtained from the upper encoder 3 and lower encoder 6.

Each of the upper sample-and-hold circuits 2-1 to 2-m includes a capacitor Ci of fixed capacitance, a switch S2 for applying the analog signal Vin to the capacitor Ci and a switch S21 for applying each of the reference voltages VH-1 to VH-m to the capacitor Ci. Similarly, each of the lower sample-and-hold circuits 5-1 to 5-n includes a capacitor Ci of fixed capacitance, a switch S5 for applying the analog signal Vin to the capacitor Ci and a switch S51 for applying each of the reference voltages VL-1 to Vl-n to the capacitor Ci. The switches S2 each constructed of MOS transistors are sequentially turned on by the sampling clock .phi.s2 from the control signal generator 8 complementarily with turn-on of the switches S21 each constructed of MOS transistors and similarly the switches S5 each constructed of MOS transistors are sequentially turned on by the sampling clock .phi.s5 from the control signal generator 8 complementarily with turn-on of the switches S51 each constructed of MOS transistors, so that the individual capacitors Ci are charged with the input analog signal Vin and discharged at the reference voltages VH-1 to VH-m or the reference voltages VL-1 to VL-n.

The capacitor Ci thus charged with the input analog signal Vin and discharged at the reference voltages VH-1 to VH-m or VL-1 to VL-n provides a residual potential polarity which in turn is compared with one of the reference voltages by each of the comparators 1-1 to 1-m or 4-1 to 4-n, producing a comparison output of binary logic which is "1" or "0".

On the basis of the results of comparison at the upper comparators 1, the reference voltage generator 7 performs the second step of setting the reference voltages VL-1 to VL-n of lower comparators 4 which are finer than the reference voltages VH-1 to VH-m.

The common analog switch Sm can be provided by connecting a p-channel MOS transistor and an n-channel MOS transistor in parallel as will be described later with reference to FIG. 3. The analog switch Sm responds to the control clock .phi.m from the control signal generator 8 to collectively switch and control the analog signal Vin, about to branch and proceed to the upper and lower sample-and-hold circuits 2 and 5.

The control signal generator 8 is so constructed as to generate, in addition to the sampling clocks .phi.s2 and .phi.s5 and control clock .phi.m described previously, a control signal not shown for sequence control of the upper comparators 1, lower comparators 4, upper encoder 3 and lower encoder 6.

FIG. 2 is a timing chart showing the operation of the essential part of the previously-described AD converter.

Firstly, when the sampling clocks .phi.s2 and .phi.s5 and control clock .phi.m are enabled as shown in FIG. 2 in the control signal generator shown in FIG. 1, the sampling switches S2 in the sample-and-hold circuits 2, the sampling switches S5 in the sample-and-hold circuits 5 and the common analog switch Sm are turned on, so that the capacitors Ci in the sample-and-hold circuits 2 and 5 are charged with a value corresponding to the level (voltage) of the analog signal Vin.

Subsequently, when the output control clock .phi.m of an analog switch driver 82 is disabled, the common analog switch Sm is turned off to simultaneously disconnect the capacitors Ci is the sample-and-hold circuits 2 and 5 from the analog signal Vin. Then, the output sampling clocks .phi.s2 and .phi.s5 of a delay circuit 84 are disabled with a slight delay (td) from the turn-off of the common analog switch Sm, thereby turning off the switches S2 and S5 for sampling in the sample-and-hold circuits 2 and 5.

Consequently, even if there is a slight difference in edge shift between the sampling clock .phi.s2 for upper sample-and-hold circuits 2 and the sampling clock .phi.s5 for lower sample-and-hold circuits 5, the capacitors Ci in the sample-and-hold circuits 2 and 5 can be charged substantially equally with a level (voltage) of analog signal Vin appearing at the time point that the common analog switch Sm was changed from on-state to off-state.

In this manner, the upper and lower comparators 1 and 4 can handle comparison of such a level of analog signal Vin as deemed to be sampled at substantially the same timing at which .phi.m is disabled. Thus, the AD conversion input for the upper bit data DoH and the AD conversion input for the lower bit data DoL can be applied at substantially the same timing.

As described above, the AD conversion to be effected by using the mutually separated upper bit data DoH and lower bit data DoL can be carried out highly precisely at a high speed while preserving continuity between the upper bit and the lower bit.

The switch Sm is connected in parallel with m switches S2 and n switches S5. Since on-resistance Rm of this switch Sm is connected in series with on-resistance Rs2 of each switch S2 or on-resistance Rs5 of each switch S5, the on-resistance Rm should preferably be small in order to ensure high-speed operation of the AD converter circuit and consequently it is preferable that parameters of channel dimension of MOS transistors constructing the analog switches be so selected as to satisfy Rm<10Rs2 and Rm<10Rs5. Accordingly, for the sake of effectively suppressing the size of the analog switch-circuit as a whole, it is preferable that these analog switches be related to each other in the ratio W/L between channel width W and channel length L of the MOS transistors as follows: ##EQU1## where Wm and Lm represent channel width and channel length of P- or N-channel MOS transistors of the analog switch Sm, Ws2 and Ls2 represent channel width and channel length of P- or N-channel MOS transistors of each upper analog switch S2, and Ws5 and Ls5 represent channel width and channel length of P- or N-channel MOS transistors of each lower analog switch S5.

FIG. 3 shows another embodiment of the AD converter of the invention.

This embodiment differs from the foregoing embodiment in that in addition to the previously-described construction, there is provided an offset compensator 9 which compensates for voltage offset due to inter-electrode capacitance of MOS transistors Mp1 and Mn1 forming the analog switch Sm. The compensator 9 includes a clocked CMOS inverter 91 having its input and output terminals connected to the output of the analog switch Sm.

As shown in FIG. 4, the clocked CMOS inverter 91 is disabled during normal operation (excepting the compensation period) so as not to interfere with the output of the analog switch Sm but immediately after the analog switch Sm changes from on-state to off-state, it responds to a trigger pulse .phi.p from a control signal generator 8' to be enabled momentarily. The trigger pulse .phi.p can be prepared by means of a combined delay and gate circuit 85 which utilizes the fall edge of the control clock .phi.m used to turn on/off the analog switch Sm.

In the clocked CMOS inverter 91, negative feedback operation due to the input and output terminals connected in common acts momentarily, with the result that electric charge is injected in a direction of dotted arrow 99 in FIG. 3 to cancel out electric charge transiently injected into the inverter 91 through inter-electrode capacitance between the gate and source/drain regions of the MOS transistors Mp1 and Mn1 constituting the analog switch circuit Sm.

Accordingly, as shown at arrow 55 in FIG. 5, for example, by selecting a suitable value of the width (duty) of the trigger pulse .phi.p, voltage offset due to the common analog switch Sm can be compensated for.

In this case, CMOS transistors Mp2, Mp3, Mn2 and Mn3 constituting the clocked CMOS inverter 91 are merely required to cancel out a small amount of electric charge transiently injected through a small inter-electrode capacitance between the gate and source/drain regions and therefore their occupation area can be far smaller than that of the MOS transistors Mp1 and Mn1 of the analog switch Sm undergoing compensation. In FIG. 4, in comparison with the on-duration of .phi.m, .phi.s2 and .phi.s5 being about several of tens of ns, the on-duration of .phi.p is sufficiently short, amounting to about several ns.

The compensator 9 applied to the AD converter as described above may also be applied to, for example, a switched capacitor in which a great number of analog switches each formed of MOS transistors are used.

The invention achieved by the present inventors has been described specifically by referring to the embodiments but obviously the present invention is not limited thereto and can be changed and modified in various ways without departing from the scope of gist of the invention.

For example, the transistors constituting the common analog switch Sm may be MIS (metal insulator semiconductor) transistors other than the MOS transistors.

FIG. 6 shows an apparatus according to another embodiment of the invention wherein a video signal undergoes signal processing through analog-to-digital conversion.

A video signal received from a video signal generator 60 is applied, together with a clock, to an integrated-circuited AD converter 62 to provide digital output signals Do to Dn. A digital signal processing circuit 64 delivers a signal representative of a result of processing.

Circles .largecircle. seen in FIG. 6 are used to indicate external terminals Vin (input terminal), Vs.sub.5 (terminal supplied with the ground level of the circuit), Vcc (terminal supplied with the power source level of the circuit), CLK (terminal applied with an external system clock) and Do to Dn (terminals of providing output data). Analog-to-digital circuits described in conjunction with the drawings of FIGS. 1, 3 and 7 also have external terminals in the same way.

In the foregoing description, the present invention has been described as being applied principally to the sub-flash AD converter which is the utilization field backgrounding the present invention but the invention is in no way limited thereto and may also be applied to a pipelined AD converter in which a plurality of set of flash AD converters are operated in parallel.

FIG. 7 shows the construction of a three-stage sub-flash AD converter by using like reference characters, some of which are prefixed with 7, to designate components like those in the FIG. 1 embodiment. Outputs of upper, medium and lower encoders 73, 76 and 79 are combined together to form a digital output Dout. A plurality of medium reference voltages VM-1 to VM-m applied to a plurality of medium sample-and-hold circuits, ganged into a set designated by reference numeral 75, are also applied to a second reference voltage generator 70-2 so as to be used for setting a plurality of lower reference voltages on the basis of a medium digital output DoM. It will be appreciated that the internal construction and function of the other components such as control signal generator 8, analog Sm and buffers 81 resembles that of the FIG. 1 embodiment.

The three-stage pipelined AD converter has the above construction and an AD converter of four or more stages can be constructed in accordance with the teachings of the above construction.

In any of the embodiments of FIGS. 1 and 7, the buffers 81 may be omitted.