Method of Forming Recessed Oxide Isolation

This invention relates generally to semiconductor devices, and more specifically to a process for the formation of electrical isolation structures in a semiconductor integrated circuit.

The semiconductor industry continually strives to increase device performance by reducing device dimensions and increasing device packing densities. For a given chip size, increasing the device packing density can be achieved by reducing the lateral distance separating active devices, which can be achieved with a reduction in isolation width. The desire to reduce isolation width, while maintaining the necessary electrical isolation between adjacent active devices, has led to the development of several different dielectric isolation schemes.

One form of dielectric isolation is Recessed Oxide Isolation (ROI). In this approach, a mask overlying a silicon substrate is patterned such that the substrate is exposed in regions where dielectric isolation is to be formed. The exposed silicon regions are then etched, forming trenches in the substrate. During trench formation, unexposed portions of the silicon substrate are protected by an overlying mask. The trench regions are then thermally oxidized to form recessed oxide isolation regions. Thus, in this approach the mask serves both as an etch barrier during trench formation and as an oxidation barrier during trench oxidation. A composite mask of silicon dioxide and silicon nitride has been widely used for this dual purpose. However, a problem with this technique is that regions of silicon underneath edges of the silicon nitride mask are also oxidized due to lateral oxidation. This phenomenon, known as field oxide encroachment, results in the final width of the electrical isolation region being larger than is necessary. Thus, due to field oxide encroachment, a limited increase in device packing density can be achieved with ROI.

The desire to suppress field oxide encroachment has lead to the development of complicated process techniques that seal the sidewall of both the trench and the patterned composite mask in order to prevent or retard lateral oxidation, for example, as described by R. Fang in U.S. Pat. No. 4,398,992. In these techniques a film of silicon nitride or silicon dioxide is frequently used to form the sidewall oxidation seal. However, the additional stress generated by these sealing techniques during trench oxidation creates crystalline defects in the silicon substrate that degrade both device performance and reliability. Additionally, these complicated process techniques are difficult to control and frequently fail to reduce lateral oxidation. Accordingly, a need exists for a ROI process that effectively and reproducibly reduces lateral oxidation and provides stress relief during trench oxidation in order to prevent the generation of substrate defects.

The previously mentioned problems with existing ROI processes are overcome by the present invention. In one embodiment of the invention, electrical isolation is formed by providing a semiconductor substrate. A buffer layer is formed over the substrate. An oxidation resistant layer is formed over the buffer layer. The oxidation resistant layer is etched to define an isolation region of the substrate and to leave a portion of the oxidation resistant layer overlying the substrate. A disposable sidewall spacer is formed laterally adjacent to the sidewall of the oxidation resistant layer and a trench region is defined. The trench region is etched to form a trench. The disposable sidewall spacer is removed. A conformal layer of oxidizable material is deposited over the oxidation resistant layer, the trench sidewall, and the trench bottom surface. The conformal layer of oxidizable material is then oxidized to form electrical isolation in the isolation regions of the substrate. These and other features, and advantages, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to point out that the illustrations may not necessarily be drawn to scale, and that there may be other embodiments of the present invention which are not specifically illustrated.

FIGS. 1-12 illustrate, in cross-section, process steps in accordance with one embodiment of the invention.

FIGS. 13-16 illustrate, in cross-section, process steps in accordance with a second embodiment of the invention.

FIGS. 17-21 illustrate, in cross-section, process steps in accordance with a third embodiment of the invention.

FIGS. 1 through 12 illustrate, in cross-section, process steps in accordance with one embodiment of the invention wherein electrical isolation structures are formed in an integrated circuit. Shown in FIG. 1 is a portion 10 of an integrated circuit structure comprising a silicon substrate 12, a buffer layer 14, a silicon nitride layer 16, and a masking layer 18. Substrate 12 is preferably thermally oxidized to form buffer layer 14, which may have a thickness ranging from 10 to 100 nanometers. Alternatively, buffer layer 14 may be chemical vapor deposited silicon dioxide. Following the formation of buffer layer 14, nitride layer 16, which is oxidation resistant, is deposited by chemical vapor deposition onto buffer layer 14. In accordance with a preferred embodiment, nitride layer 16 is deposited with a thickness ranging from 50 to 200 nanometers. Silicon nitride layer 16 could also be substituted with another oxidation resistant material, such as oxynitride. After nitride layer 16 is formed, a masking layer 18 may be deposited over nitride layer 16. In accordance with a preferred embodiment, masking layer 18 is a chemical vapor deposited silicon dioxide.

The process continues, in a preferred embodiment, as shown in FIG. 2, with a selective anisotropic etch leaving portions of the buffer layer 20, nitride layer 22, and masking layer 24 overlying substrate 12, and defining an isolation region 26 of the substrate 12. The anisotropic etch proceeds in the vertical direction faster than in the horizontal thus yielding a straight buffer layer sidewall 28, as illustrated in FIG. 2.

Referring to FIG. 3, the process continues with a low pressure chemical vapor deposition of a silicon dioxide layer, which is very conformal, and which overlies nitride layer 22 and isolation region 26. After the conformal silicon dioxide layer is deposited, an anisotropic etch is performed to form a sidewall spacer 30 laterally adjacent to buffer layer sidewall 28, and covering a first portion 32 of isolation region 26, and to expose a second portion 34 of isolation region 26. The formation of sidewall spacers by depositing a layer of spacer material which conforms to the underlying contour, and then anisotropically etching is well known.

The process continues, in a preferred embodiment, as shown in FIG. 4, with a selective anisotropic etch of exposed second portion 34 to form a trench region 36 in substrate 12 having a trench bottom surface 38 and a trench sidewall 40. At this step it should be noted, that masking layer 24 may be optional if substrate 12 is etched with an etchant which is selective with respect to nitride layer 22. Additionally, trench region 36 may be doped using an ion implantation or diffusion step.

Following trench formation, sidewall spacer 30, which is disposable, is removed with an isotropic etch and first portion 32 of isolation region 26 is exposed. In this same step, buffer layer sidewall 28 is etched, a recess 42 is formed underneath an edge portion of nitride layer 22, because the etch is isotropic, and a portion 44 of substrate 12 is exposed. Additionally, remaining portions of masking layer 24 are also removed during this step, which results in the structure shown in FIG. 5. Recess 42 may have a lateral dimension ranging from 10 to 100 nanometers. In accordance with the preferred embodiment, a wet oxide etchant is used to remove sidewall spacer 30 and form recess 42. If disposable spacer 30 and buffer layer 20 are composed of materials that do not etch in the same etchant, then separate etching steps may be used to first remove sidewall spacer 30 and then etch buffer layer sidewall 28 to form recess 42. The resulting structure is the same as that shown in FIG. 5.

Once recess 42 is formed, a thin oxide layer 46 is formed on exposed portion 44, first portion 32 of isolation region 26, trench sidewall 40, and trench bottom surface 38, as shown in FIG. 6. In accordance with the preferred embodiment, exposed portion 44, first portion 32 of isolation region 26, trench sidewall 40, and trench bottom surface 38 are thermally oxidized to form a thin oxide layer 46 having a thickness ranging from 2 to 10 nanometers. Alternatively, thin oxide layer 46 may be a chemical vapor deposited silicon dioxide.

Referring to FIG. 7, the process continues with the deposition of a polysilicon layer 48, which is very conformal, and which overlies nitride layer 22, thin oxide layer 46, and substantially fills recess 42. Polysilicon layer 48 is preferably chemical vapor deposited with a thickness of about 50 nanometers. Alternatively, another material which is both oxidizable and conforms to the underlying contour, and which can be readily converted to a material useful for isolation, could be used.

After polysilicon layer 48 has been deposited, an oxidation is performed to grow a thick isolation oxide 50 within isolation region 26, as shown in FIG. 8. The oxidation process is preferably carried out in an oxidation furnace at about 900 to 1200 degrees Celsius in the presence of nitrogen and steam. In accordance with the preferred embodiment, the oxidation process completely consumes polysilicon layer 48 converting the layer to silicon dioxide, thus forming an oxidized conformal layer of polysilicon 52.

The process is completed with the removal of portions of oxidized conformal layer 52, nitride layer 22, and buffer layer 20, as shown in FIG. 9. Transistors can then be formed in active regions separated by isolation oxide 50.

Shown in FIG. 10 is the structure of FIG. 8 with a relatively planar layer of silicon dioxide 54 deposited over the structure. This is an alternative to simply removing portions of oxidized conformal layer 52, nitride layer 22, and buffer layer 20 to obtain the structure shown in FIG. 9.

After silicon dioxide layer 54 is deposited, portions of silicon dioxide layer 54, oxidized conformal layer 52, and isolation oxide 50 are etched. This forms an isolation oxide 56 and also results in isolation region 26 being substantially planar with nitride layer 22, as shown in FIG. 11.

The process is then completed with the removal of nitride layer 22 and buffer layer 20, as shown in FIG. 12. Once again, transistors can now be formed on the active regions separated by isolation oxide 56.

Shown in FIG. 13 is a portion 57 of an integrated circuit structure comprising a silicon substrate 58, a buffer layer 60 analogous to buffer layer 14 of FIG. 1, a silicon nitride layer 62 analogous to nitride layer 22 of FIG. 2, a masking layer 64, analogous to masking layer 24 of FIG. 2, and a isolation region 66. In this alternative embodiment an anisotropic etch is performed, on a structure which is the same as that shown in FIG. 1, to leave masking layer 64 and nitride layer 62 overlying buffer layer 60, and to define isolation region 66 of substrate 58. Additionally, the anisotropic etch proceeds in the vertical direction faster than in the horizontal thus yielding a straight nitride layer sidewall 68, as illustrated in FIG. 13. Buffer layer 60 is not etched at this time in contrast to FIG. 2, wherein analogous buffer layer 14 is etched to leave buffer layer 20 overlying substrate 12.

Referring to FIG. 14, the process continues with a low pressure chemical vapor deposition of silicon dioxide, which is conformal, and which overlies nitride layer 62 and isolation region 66. After the conformal silicon dioxide layer is deposited, an anisotropic etch is performed to form a sidewall spacer 70 laterally adjacent to nitride layer sidewall 68, and covering a first portion 72 of the isolation region 66, and exposing a portion of the buffer layer, which is also anisotropically etched during this step to expose a first portion 74 of substrate 58, and to leave portions of the buffer layer 76 overlying substrate 58. The formation of sidewall spacers by depositing a layer of spacer material which conforms to the underlying contour, and then anisotropically etching is well known. If the anisotropic etch used to form sidewall spacer 70 is selective to buffer layer 60, then two separate anisotropic etch steps can be used. With the first etch, sidewall spacer 70 is formed and in the second etch buffer layer 60 is etched to expose first portion 74. The resulting structure in such a case is the same as the structure shown in FIG. 14.

The process continues, as shown in FIG. 15, with a selective anisotropic etch of exposed first portion 74 to form a trench region 78 in substrate 58 having a trench bottom surface 80 and a trench sidewall 82. At this step it should be noted, that masking layer 64 may be optional if substrate 58 is etched with an etchant which is selective with respect to nitride layer 62. Additionally, trench region 78 can be doped using an ion implantation or diffusion step.

Following trench formation, sidewall spacer 70, which is disposable, is removed with an isotropic etch. In this same step, buffer layer 76 is etched, a recess 84 is formed underneath an edge portion of nitride layer 62, because the etch is isotropic, and a portion 86 of substrate 12 is exposed. Additionally, remaining portions of masking layer 64 are also removed during this step, which results in the structure shown in FIG. 16, and which is identical to the structure shown in FIG. 5. Additionally, if disposable spacer 70 and buffer layer 76 are composed of materials that do not etch in the same etchant, then separate etching steps may be used to first remove sidewall spacer 70 and then etch buffer layer 76 to form recess 84. The resulting structure in such a case would be the same as the structure shown in both FIG. 16 and in FIG. 5.

Following the formation of recess 84, processing continues with the steps previously described in FIG. 6 through FIG. 12.

Shown in FIG. 17 is a portion 87 of an integrated circuit structure comprising a silicon substrate 88, a buffer layer 90 analogous to buffer layer 14 of FIG. 1, a silicon nitride layer 92 analogous to nitride layer 16 of FIG. 1, a masking layer 94 analogous to masking layer 24 of FIG. 2, and a trench region 98. In this alternative embodiment an anisotropic etch is performed, on a structure which is the same as that shown in FIG. 1, to leave masking layer 94 overlying nitride layer 92, to expose a portion 96 of nitride layer 92, and to define trench region 98.

The process continues, as shown in FIG. 18, with a selective anisotropic etch of exposed portion 96 to form a nitride layer sidewall 100. Using an isotropic etch nitride layer sidewall 100 is then laterally recessed underneath masking layer 94 to leave portions of the silicon nitride layer 102 overlying buffer layer 90 and underlying masking layer 94, and exposing a portion 104 of the buffer layer 90, and defining an isolation region 106 of substrate 88. Alternatively, a structure similar to that shown in FIG. 18 could be achieved with only an isotropic etch.

Referring to FIG. 19, the process continues with a selective anisotropic etch of exposed portion 104 to leave portions of the buffer layer 108 overlying substrate 88, and exposing a first portion 110 of substrate 88.

Exposed first portion 110 in trench region 98 is then selectively anisotropically etched to form a trench 112 in substrate 88 having a trench sidewall 114 and a trench bottom surface 116, as shown in FIG. 20. Additionally, trench 112 can be doped using an ion implantation or diffusion step.

After trench formation, masking layer 94 is removed with a selective isotropic etch. In this same step, buffer layer 108 is etched, a recess 118 is formed underneath an edge portion of nitride layer 102, because the etch is isotropic, and a portion 120 of substrate 88 is exposed. The resulting structure, as shown in FIG. 21, is the same as both FIG. 5 and FIG. 16. Additionally, if masking layer 94 and buffer layer 108 are composed of materials that do not etch in the same etchant, then separate etching steps may be used to remove masking layer 94 and to etch buffer layer 108 to form recess 118. The resulting structure in such a case would be the same as the structure shown in FIG. 21, FIG. 16, and FIG. 5. Alternatively, in FIG. 18, recess 118 may be formed when exposed portion 104 is etched to leave buffer layer 108 overlying substrate 88. The resulting structure in such a case would once again be the same as the structure shown in FIG. 21, FIG. 16, and FIG. 5.

Following the formation of recess 118 to result in the structure shown in FIG. 21, processing continues with the steps previously described in FIG. 6 through FIG. 12.

The foregoing description and illustrations contained herein demonstrate many of the advantages associated with the present invention. One advantage is that a trench is formed which is self-aligned to, but offset from, the edge of the oxidation resistant layer, as shown in FIG. 5, wherein the trench is shown to be self-aligned to, but offset from the edge of nitride layer 22. Therefore, a portion of the trench sidewall can be laterally oxidized without the final width of the oxide isolation becoming larger than the intended width. In addition, the techniques used to form the offset trench also allow dopants, which may be introduced into the trench, to be offset from the edge of the nitride layer. Therefore, dopant encroachment of the active area can be minimized. Additionally, the disposable sidewall spacer technique also minimizes field thinning in isolation regions with narrow widths. Another advantage is that the offset trench structure, along with its inherent benefits, can be easily combined with a recess structure, as shown in FIG. 5, FIG. 16, and FIG. 21. Therefore, a polysilicon filled recess, with its known advantages, can be successfully coupled with the offset trench structure to further reduce lateral oxidation. This beneficial combination results in a nearly planar recessed oxide isolation that has a final physical isolation width which is nearly the same as the originally defined lithographic dimension. This defined lithographic dimension may be the smallest feature size that the lithographic equipment is capable of defining. A disadvantage of prior art recessed field oxides is that during the formation thereof, they often expanded beyond the originally defined dimension. In such a case the resulting field oxide was often larger than was necessary to provide the requisite isolation. Therefore, field oxide encroachment is substantially reduced over existing recessed oxide isolation schemes. In addition, thin oxide layer 46 and polysilicon layer 48 provide critical stress relief during the oxidation process. Consequently, substrate defect generation is substantially reduced over existing recessed oxide isolation schemes. Therefore, devices with increased packing densities, high reliability, and improved performance can be achieved with this invention.

Thus it is apparent that there has been provided, in accordance with the invention, a method for forming recessed oxide isolation that fully meets the need and advantages set forth previously. Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. For example, in some applications thin oxide layer 46 may be optional and the conformal layer of oxidizable material may be deposited directly on the trench sidewall and trench bottom surface. In addition, the invention is not limited to the deposition and etch methods described. For example, in some applications an isotropic etch, instead of an anisotropic etch, may be used for trench formation. It is also important to note that the present invention is not limited in any way to specific layer thicknesses or other dimensions as specifically mentioned. Furthermore, this invention is not limited to those materials specifically described. For example, a conformal layer of silicon rich-oxide could be substituted for polysilicon layer 48. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.