Semiconductor Device With Input Protection Circuit

2. Field of the Invention

The present invention relates to improvement of a CMOS semiconductor device having an input protection circuit.

2. Description of the Related Art

Conventionally, two types of input protection circuits are known, one in which a diode is connected between an input terminal and a V.sub.DD line and a diode is connected between an input terminal and a V.sub.SS line; and the other in which a dummy transistor is connected between an input terminal and a V.sub.DD line and a dummy transistor is connected between an input terminal and a V.sub.SS line.

The first type of input protection circuit has the structure shown in FIG. 1. In FIG. 1, reference numeral 21 is an input terminal, T: a MOSFET, D.sub.1 : a diode of V.sub.DD side, D.sub.2 : a diode of V.sub.SS side, T.sub.1 : a P channel type MOSFET provided around the input protection circuit, and T.sub.2 : an N channel type MOSFET provided around the input protection circuit.

According to this type of the input protection circuit, if a plus surge V.sub.S+ (wherein V.sub.SS is used as a reference voltage, for example, V.sub.SS <V.sub.DD <V.sub.S+) is inputted to the input terminal 21, the plus surge V.sub.S+ passes through the diode D.sub.1 of the V.sub.DD side, and is absorbed in the V.sub.DD line. Moreover, if a minus surge V.sub.S- (wherein V.sub.SS is used as a reference voltage, for example, V.sub.S- <V.sub.SS <V.sub.DD) is inputted to the input terminal 21, the minus surge V.sub.S- passes through the diode D.sub.2 of the V.sub.SS side, and is absorbed in the V.sub.SS line.

The second conventional input protection circuit has the structure shown in FIG. 2. In FIG. 2, T.sub.3 is a dummy transistor of V.sub.DD side, and T.sub.4 is a dummy transistor of V.sub.SS side.

According to this type of input protection circuit, if the plus surge V.sub.S+ (wherein V.sub.SS is used as a reference voltage) is inputted to the input terminal 21, the plus surge V.sub.S+ passes through the dummy transistor T.sub.3 of the V.sub.DD side, and is absorbed in the V.sub.DD line. Moreover, if a minus surge V.sub.S- (wherein V.sub.SS is used as a reference voltage) is inputted to the input terminal 21, the plus surge V.sub.S- passes through the dummy transistor T.sub.4 of the V.sub.SS side, and is absorbed in the V.sub.SS line.

The first conventional input protection circuit, however, has the following disadvantage.

That is, if the pulse surge V.sub.S+ (V.sub.SS =reference voltage) is inputted to the input terminal 21, the plus surge V.sub.S+ is absorbed in the V.sub.DD line as shown by a solid line arrow. Thereafter, the plus surge V.sub.S+ passes through the V.sub.DD line and finally reaches a drain of the N channel type MOSFET T.sub.2. Then, the plus surge V.sub.S+ passes through a Zener diode comprising N.sup.+ and P.sup.-, and is absorbed in the V.sub.SS line. As a result, current caused by the surge flows in the drain of the N channel type MOSFET T.sub.2, and the drain is destroyed.

Similarly, in a case where the plus surge V.sub.S+ (V.sub.SS =reference voltage) is inputted to the V.sub.DD line, current caused by the surge flows in the drain of MOSFET T.sub.2, and the drain is destroyed.

If the minus surge V.sub.S- (V.sub.DD =reference voltage) is inputted to the input terminal 21, the minus surge V.sub.S- is absorbed in the V.sub.SS line as shown by a broken line arrow. Thereafter, the minus surge V.sub.S- passes through the V.sub.SS line and finally reaches to the drain of the N channel type MOSFET T.sub.2. Then, the minus surge V.sub.S- passes through the Zener diode comprising N.sup.+ and P.sup.-, and is absorbed in the V.sub.DD line. As a result, current caused by the surge flows in the drain of the N channel type MOSFET T.sub.2, and the drain is destroyed.

Similarly, in a case where the minus surge V.sub.S- (V.sub.DD =reference voltage) is inputted to the V.sub.SS line, current caused by the surge flows in the drain of MOSFET T.sub.2, and the drain is destroyed.

As mentioned above, according to the first conventional input protection circuit, MOSFET T can be protected. N channel MOSFET T.sub.2 provided around the MOSFET T, however, cannot be protected with respect to the plus surge V.sub.S+ (V.sub.SS =reference voltage) to be inputted to the input terminal 21 or the V.sub.DD line and the minus surge V.sub.S- (V.sub.DD =reference voltage) to be inputted to the input terminal 21.

As compared with the input protection circuit, the second conventional input protection circuit is improved in the following respect.

That is, if the plus surge V.sub.S+ (V.sub.SS =reference voltage) is inputted to the input terminal 21, as shown by an arrow a of a solid line, the plus surge V.sub.S+ finally reaches the drain of the N channel type MOSFET T.sub.2 and the drain of the dummy transistor T.sub.4 of the V.sub.SS side. Then, the plus surge V.sub.S+ passes through a Zener diode comprising N.sup.+ and P.sup.- of the drain sides of the transistors T.sub.2 and is T.sub.4, and absorbed in the V.sub.SS line. As a result, in the drains of the transistors T.sub.2 and T.sub.4, density of current caused by the surge is relaxed and the drains are prevented from being destroyed. However, in this case, since the dimension of the dummy transistor T.sub.4 of the V.sub.SS side must be made larger than that of the N channel type MOSFET T.sub.2, this is disadvantageous to the integration of the element.

If the plus surge V.sub.S+ (V.sub.SS =reference voltage) is inputted from the V.sub.DD line, the plus surge V.sub.S+ finally reaches the drain of the N channel type MOSFET T.sub.2 as shown in an arrow b of a solid line. Then, the plus surge V.sub.S+ passes through only Zener diode comprising N.sup.+ and P.sup.- of the drain side of the transistor T.sub.2, and is absorbed in the V.sub.SS line. Due to this, the drain of the N channel type MOSFET T.sub.2 is destroyed.

Moreover, if the minus surge V.sub.S- (V.sub.DD =reference voltage) is inputted to the input terminal 21, the minus surge V.sub.S- is absorbed in the V.sub.SS line as shown by an arrow of a broken line. Thereafter, the minus surge V.sub.S- passes through the V.sub.SS line and finally reaches to the drain of the N channel type MOSFET T.sub.2. Then, the minus surge V.sub.S- passes through the Zener diode comprising N.sup.+ and P.sup.-, and absorbed in the V.sub.DD line. As a result, current caused by the surge flows in the drain of the N channel type MOSFET T.sub.2, and the drain is destroyed.

Similarly, in a case where the minus surge V.sub.S- (V.sub.DD =reference voltage) is inputted to the V.sub.SS line, current caused by the surge flows in the drain of MOSFET T.sub.2, and the drain is destroyed.

As mentioned above, according to the second conventional input protection circuit, MOSFET T can be protected. An N channel MOSFET T.sub.2 provided around the MOSFET T, however, cannot be protected relating to particularly the minus surge V.sub.S -.

The present invention has been made in order to eliminate the above disadvantages, and an object of the present invention is to provide a semiconductor device wherein an input protection circuit can be formed without being enlarged and an N channel type MOSFET formed in the vicinity of the input protection circuit can be protected.

The semiconductor device of the present invention comprises a semiconductor substrate of a first conductive type and a MOS transistor of a second conductive type, and an input protection circuit. The MOS transistor of the second conductive type is formed in the semiconductor substrate, and its drain is connected to a first power source. A first impurity layer of the first conductive type is formed around the drain of the MOS transistor of the second conductive type. The input protection circuit comprises first and second diodes. The first diode has a second impurity layer of the first conductive type and a third impurity layer of the second conductive layer. The third impurity layer is connected to an input terminal, and the second impurity layer is connected to a second power source. The second diode has a fourth impurity layer of the first conductive type and a fifth impurity layer of the second conductive type. The fifth impurity layer is connected to the first power source, and the fourth impurity layer is connected to the second power source. Moreover, the impurity concentration of the fourth impurity layer is set to be higher than that of the first impurity layer.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIGS. 1 and 2 are cross sectional views showing conventional semiconductor devices;

FIG. 3 is a cross sectional view showing a semiconductor device according to one embodiment of the present invention;

FIG. 4 is an equivalent circuit diagram of an input protection circuit of the semiconductor device of FIG. 3;

FIGS. 5 to 12 are views showing a passage of a surge current in the semiconductor device of FIG. 3;

FIG. 13 is a graph showing a voltage-current characteristic of a diode forming the input protection circuit of the semiconductor device of FIG. 3; and

FIG. 14 is a cross sectional view showing a semiconductor device according to another embodiment of the present invention.

An embodiment of the present invention will be explained with reference to the drawings. In the explanation, the same reference numerals are added to the corresponding portions of FIGS. 1 and 2.

FIG. 3 shows a semiconductor device of the present invention in which an input protection circuit is formed. In the drawing, H denotes the input protection circuit. The structure of the input protection circuit of the present invention will be explained.

A P.sup.- impurity layer 12 is formed in a P type semiconductor substrate 11. N.sup.+ impurity layers 14 and 15 are formed in the P.sup.- impurity layer 12. A P.sup.+ impurity layer 13 is formed between the N.sup.+ impurity layers 14 and 15 to have a constant distance from the impurity layers 14 and 15.

The N.sup.+ impurity layer 14 is connected to an input terminal 21. The N.sup.+ impurity layer 15 is connected to a V.sub.DD line (for example, a power source line). The P.sup.+ impurity layer 13 is connected to a V.sub.SS line (for example, a ground line).

FIG. 4 shows an equivalent circuit of the protection circuit H. A cathode of a diode D.sub.1 is connected to the input terminal 21, and an anode of the diode D.sub.1 is connected to the V.sub.SS line. A cathode of a diode D.sub.2 is connected to the V.sub.DD line, and an anode of the diode D.sub.2 is connected to the V.sub.SS line. The anode of the diode D.sub.1 and that of the diode D.sub.2 are shared by the P.sup.+ impurity layer 13.

Thereby, the diode D.sub.1 is connected to only the V.sub.SS side of the input terminal 21. As a result, as compared with the case in which the diode or the transistor is connected to both V.sub.SS and V.sub.DD sides, the percentage of the input protection circuit, which occupies on the semiconductor substrate, can be reduced. Moreover, the current caused by Zener brake due to the surge can be sufficiently absorbed and dispersed if the dimension of the protection circuit H is set. Therefore, as compared with the prior art, strength against the surge can be improved.

Next, various cases in which surge voltage is generated will be explained.

FIG. 5 shows passage of the corresponding surge when a plus surge V.sub.S+ (wherein V.sub.SS is a reference voltage, for example, V.sub.SS <V.sub.DD <V.sub.S+) is inputted to the input terminal 21. In this case, the plus surge V.sub.S+ passes through the Zener diode comprising N.sup.+ impurity layer 14 and P.sup.- impurity layer 12, and is absorbed in the V.sub.SS line. Therefore, no surge current flows to the N channel MOSFET T.sub.2.

FIG. 6 shows a passage of the corresponding surge when the plus surge V.sub.S+ (wherein V.sub.SS is a reference voltage) is inputted to the V.sub.DD line. In this case, the plus surge V.sub.S+ passes through the Zener diode comprising N.sup.+ impurity layer 15 of the protection circuit H and P.sup.- impurity layer 12, and is absorbed in the V.sub.SS line. At the same time, the plus surge V.sub.S+ passes through the Zener diode comprising an N.sup.+ impurity layer 22 of the N channel MOSFET T.sub.2 and a P.sup.- impurity layer 23, and is absorbed in the V.sub.SS line.

FIG. 7 shows a passage of the corresponding surge when a minus surge V.sub.S- (wherein V.sub.SS is a reference voltage) is inputted to the input terminal 21. In this case, the minus surge V.sub.S- passes through the diode comprising N.sup.+ impurity layer 14 of the protection circuit and P.sup.- impurity layer 12, and is absorbed in the V.sub.SS line. That is, the surge current passes through the forward diode comprising N.sup.+ impurity layer 14 of the protection circuit and P.sup.- impurity layer 12 from the V.sub.SS line, and flows up to the input terminal 21. Therefore, no surge current flows to the N channel MOSFET T.sub.2.

FIG. 8 shows a passage of the corresponding surge when a minus surge V.sub.S- (wherein V.sub.SS is a reference voltage) is inputted to the V.sub.DD line. In this case, the minus surge V.sub.S- passes through a diode comprising an N well 16 forming P channel MOSFET T1 and a P type substrate 11, and is absorbed in the V.sub.SS line. Therefore, no surge current flows to the N channel MOSFET T.sub.2.

FIG. 9 shows a passage of the corresponding surge when a plus surge V.sub.S+ (wherein V.sub.DD is a reference voltage, for example, V.sub.S+ >V.sub.DD) is inputted to the input terminal 21. In this case, the plus surge V.sub.S+ passes through the Zener diode comprising N.sup.+ impurity layer 14 of the protection circuit H and P.sup.- impurity layer 12. The plus surge V.sub.S+ further passes through the forward diode comprising the P type substrate 11 and the N well 16, and is absorbed in the V.sub.DD line. Therefore, no surge current flows to the N channel MOSFET T.sub.2.

FIG. 10 shows a passage of the corresponding surge when a plus surge V.sub.S+ (wherein V.sub.DD is a reference voltage) is inputted to the V.sub.SS line. In this case, the plus surge V.sub.S+ passes through the forward diode comprising the P type substrate 11 and the N well 16, and is absorbed in the V.sub.DD line. Therefore, no surge current flows to the N channel MOSFET T.sub.2.

FIG. 11 shows a passage of the corresponding surge when the minus surge V.sub.S- (wherein V.sub.DD is a reference voltage) is inputted to the input terminal 21. In this case, the minus surge V.sub.S- flows the diode comprising the N.sup.+ impurity layer 14 of the protection circuit H and the P.sup.- impurity layer 12. Thereafter, the minus surge V.sub.S- passes through the Zener diode comprising the P.sup.- impurity layer 12 and the N.sup.+ impurity layer 15 and the Zener diode comprising the N.sup.+ impurity layer 22 of the N channel MOSFET T.sub.2 and the P.sup.- impurity layer 23, and is absorbed in the V.sub.DD line.

FIG. 12 shows a passage of the corresponding surge when a minus surge V.sub.S- (wherein V.sub.DD is a reference voltage) is inputted to the V.sub.SS line. In this case, the minus surge V.sub.S- passes through the Zener diode comprising the P.sup.- impurity layer 12 of the protection circuit H and the N.sup.+ impurity layer 15 and the Zener diode comprising the N.sup.+ impurity layer 22 of the N channel MOSFET T.sub.2 and the P.sup.- impurity layer 23, and is absorbed in the V.sub.DD line.

As mentioned above, according to the semiconductor device having the input protection circuit of the present invention, since the surge current does not concentrate in the drain of the N channel MOSFET T.sub.2, protection against the surge of the transistor can be improved. Moreover, since only one diode of the V.sub.SS side is connected to the input terminal 21, the protection circuit H is not unnecessarily enlarged. Therefore, the space on the semiconductor substrate can be effectively used. In other words, according to the present invention, the well to be formed in the semiconductor substrate may be only one well formed in the P.sup.- impurity layer 12. Due to this, the input protection circuit can be formed with half the area as compared with the prior art.

In three cases, that is, a) the plus surge V.sub.S+ (V.sub.SS reference) to be inputted from the V.sub.DD line; b) the minus surge V.sub.S- (V.sub.DD reference) to be inputted from the input terminal 21; and c) the minus surge V.sub.S- (V.sub.DD reference) to be inputted from the V.sub.SS line, Zener current flows in the Zener diode comprising the N.sup.+ impurity layer 22 of the N channel MOSFET T.sub.2 and the P.sup.- impurity layer 23. In this case, however, since the Zener current also flows in the protection diode D.sub.2, the dimension of the Zener diode comprising the N.sup.+ impurity layer 22 and the P.sup.- impurity layer 23 is substantially enlarged and the MOSFET T.sub.2 cannot be easily destroyed.

Moreover, in order to limit the Zener current flowing in the N channel type MOSFET T.sub.2 and concentrate the Zener current in the protection circuit H, the following structure may be provided.

That is, concentration of the P.sup.- impurity layer 12 of the protection circuit is higher than that of the P.sup.- impurity layer 23 of the N channel MOSFET T.sub.2. In other words, as shown in FIG. 13, the Zener current (shown by an arrow a) of each of the N.sup.+ impurity layer 15 of the protection circuit H and the P.sup.- impurity layer 12 is lower than that (shown by an arrow b) of each of the N.sup.+ impurity layer 22 of the N channel MOSFET T.sub.2 and the P.sup.- impurity layer 23. In FIG. 13, A shows a voltage-current characteristic curve of the diode comprising the N.sup.+ impurity layer 15 of the protection circuit H and the P.sup.- impurity layer 12. B shows a voltage-current characteristic curve of the diode comprising the N.sup.+ impurity layer 22 of the N channel MOSFET T.sub.2 and the P.sup.- impurity layer 23. C shows a voltage-current characteristic curve of the diode comprising the N well 16 and the P type substrate 11.

FIG. 14 shows a semiconductor device wherein an input protection circuit is formed according to another embodiment of the present invention. The structure of the input protection circuit will be briefly explained as follows.

In the P type substrate 11, P.sup.- impurity layers 12a, 12b, 12c, 12d and N.sup.+ impurity layers 14 and 15 are formed. The N.sup.+ impurity layer 14 is formed to be in contact with the P.sup.- impurity layer 12a and the P.sup.- impurity layer 12b. The N.sup.+ impurity layer 15 is formed to be in contact with the P.sup.- impurity layer 12c and the P.sup.- impurity layer 12d. The P.sup.+ impurity layer 13 is formed to be in contact with the P.sup.- impurity layer 12b and the P.sup.- impurity layer 12c. The N.sup.+ impurity layer 14 is connected to the input terminal 21 and the N.sup.+ impurity layer 15 is connected to the V.sub.DD line (for example, power source line), and the P.sup.+ impurity layer 13 is connected to the V.sub.SS line (for example, ground line).

The comparison between FIG. 4 and FIG. 14 will be explained as follows.

The diode D.sub.1 comprises the P.sup.- impurity layer 12b and the N.sup.+ impurity layer 14. The diode D.sub.2 comprises the P.sup.- impurity layer 12c and the N.sup.+ impurity 15. Impurity concentration of P.sup.- impurity layers 12b and 12c is higher than that of the P.sup.- impurity layer 23 (see FIG. 3).

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, and representative devices, shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.