Method for Improving the Interface Characteristics of CaF.sub.2 on Silicon

This invention generally relates to the improvement of interface quality of CaF.sub.2 on silicon.

Without limiting the scope of the invention, its background is described in connection with semiconductor devices, as an example.

Heretofore, in this field, the epitaxial growth of insulators on semiconductors has been an important step in the fabrication of various electronic devices, such as metal-insulator-semiconductor field effect transistors (MISFETs), silicon on insulator (SOI) technology, three dimensional integrated circuits, etc., as well as novel devices that cannot be achieved with amorphous insulators. Epitaxial growth of Group II fluoride on silicon has been studied extensively because of its technological and scientific interest. As one of the most promising candidates in this area, the CaF.sub.2 /Si couple has attracted considerable attention. From a materials preparation point of view, CaF.sub.2 is a relevant choice among the fluorides for deposition on silicon because it fits several important criteria for a good epitaxial system, i.e. small lattice mismatch and similar cubic structure. Previous studies have shown that the chemical and structural properties of the CaF.sub.2 /Si interface vary under different deposition conditions and that these variations can significantly change the electrical characteristics of a system incorporating this interface.

In the past, epitaxial CaF.sub.2 films have been grown by molecular beam epitaxy (MBE) with substrates held at a fixed temperature from 500.degree. C. to 800.degree. C. Many state-of-the-art characterization techniques, including high-resolution transmission electron microscopy (HRTEM), medium energy ion scattering (MEIS), x-ray photoemission spectroscopy (XPS) and x-ray standing wave (XSW), have been applied in the past to understand the interface structure between CaF.sub.2 and Si. The exact atomic model governing the initial stage of epitaxial growth is still widely disputed. In co-assigned patent application Ser. No. 07/704,535, a method is described that allows the growth of A-type films, i.e. the orientation of the CaF.sub.2 film is identical to the Si substrate.

One of the problems faced has been the poor interface quality between the CaF.sub.2 and Si surfaces, in particular, the presence of a high level of interface charge density.

It is herein recognized that a need exists for a method of reducing the interface charge density between a silicon surface and CaF.sub.2 film. The present invention is directed toward meeting those needs.

Generally, and in one form of the invention, a method is disclosed for the growth of CaF.sub.2 on a silicon surface, comprising the steps of maintaining the silicon surface at a substantially fixed temperature below approximately 500.degree. C., depositing CaF.sub.2 on the surface, and then annealing the CaF.sub.2 in a reducing gas at a temperature at or below 600.degree. C.

In another form of the invention, a method is disclosed for growing CaF.sub.2 on a silicon surface, comprising the steps of maintaining the silicon surface at a first temperature below approximately 500.degree. C., starting deposition of CaF.sub.2 on the silicon surface, ramping the first temperature to a second temperature over a first time period, maintaining the second temperature until the CaF.sub.2 has deposited to a desired thickness, stopping the deposition, and then annealing the CaF.sub.2 in a reducing gas at a temperature at or below 600.degree. C.

In yet another form of the invention, a method is disclosed for the growth of CaF.sub.2 on a silicon surface, comprising the steps of maintaining the silicon surface at a substantially fixed temperature above approximately 500.degree. C., depositing CaF.sub.2 on the surface, and then annealing the CaF.sub.2 in a reducing gas at a temperature at or below 600.degree. C .

The foregoing and further aspects of the invention are illustrated in the accompanying drawings wherein like elements are denoted by like reference designators and in which:

FIG. 1 is a process flow diagram of the first preferred embodiment method of the invention;

FIG. 2 is a plot of the capacitance-voltage characteristics of capacitors fabricated using CaF.sub.2 deposited on silicon at 400.degree. C.;

FIG. 3 is a plot of the capacitance-voltage characteristics of capacitors fabricated using CaF.sub.2 deposited on silicon at 800.degree. C.

In a first preferred embodiment process of the present invention, A-type CaF.sub.2 films were epitaxially deposited onto (111)Si substrates according to the process flow of FIG. 1. A (111)Si substrate is cleaned in step 10 prior to CaF.sub.2 deposition by annealing the substrate in an MBE chamber at 950.degree. C. for 10 minutes, plus another 10 minutes with a Si flux equivalent to a deposition rate of 0.01 monolayer/sec, for example. In step 12, reflection high-energy electron diffraction (RHEED) and Auger spectroscopy, for example, are used to characterize the cleaning process. In step 14, CaF.sub.2 is deposited onto the (111)Si substrate surface by molecular beam epitaxy (MBE) from an effusion cell with a deposition rate of 4 nm/min and to a film thickness of 100 nm. As shown in step 16, the temperature of the substrate is controlled and maintained at a predetermined fixed temperature of 400.degree. C. The film was then annealed, as shown in step 18, in reducing gas (e.g. forming gas) at 450.degree. C., 600.degree. C., and 800.degree. C. for 30 minutes, and then patterned with Al dots for capacitance measurements. FIG. 2 shows that the as-deposited film exhibits an unpinned C-V curve. The effective positive charge at the interface is approximately 1.times.10.sup.12 cm.sup.-2 before annealing. After annealing at 450.degree. C. and 600.degree. C., the positive charge at the interface is reduced to 5.times.10.sup.10 cm.sup.-2 and 8.times.10.sup.10 cm.sup.-2, respectively. However, the capacitor annealed at 800.degree. C. shows a nearly flat C-V curve, suggesting increased interface states.

In a second preferred embodiment process of the present invention, B-type CaF.sub.2 films were epitaxially deposited onto (111)Si substrates according to the process flow of FIG. 1. A (111)Si substrate is cleaned in step 10 prior to CaF.sub.2 deposition by annealing the substrate in an MBE chamber at 950.degree. C. for 10 minutes, plus another 10 minutes with a Si flux equivalent to a deposition rate of 0.01 monolayer/sec, for example. In step 12, reflection high-energy electron diffraction (RHEED) and Auger spectroscopy, for example, are used to characterize the cleaning process. In step 14, CaF.sub.2 is deposited onto the (111)Si substrate surface by molecular beam epitaxy (MBE) from an effusion cell with a deposition rate of 4 nm/min and to a film thickness of 100 nm. As shown in step 16, the temperature of the substrate is controlled and maintained at a predetermined fixed temperature of 800.degree. C. The film was annealed, as shown in step 18, in forming gas (10% H.sub.2 in N.sub.2) at 450.degree. C., 600.degree. C., and 800.degree. C. for 30 minutes, and then patterned with Al dots for capacitance measurements. FIG. 3 shows that the as-deposited film exhibits a pinned C-V curve, suggesting an unacceptable amount of interface states. However, after annealing, the positive interface charge is reduced to 1.7.times.10.sup.11 cm.sup.-2, 6.9.times.10.sup.11 cm.sup.-2, and 1.2.times.10.sup.12 cm.sup.-2 for annealing temperatures of 450.degree. C., 600.degree. C., and 800.degree. C., respectively. Improved C-V characteristics are also observed when CaF.sub.2 films are annealed in F.sub.2 gas. However, the capacitors are not as stable as those annealed in hydrogen.

The pinning and unpinning of these capacitors may be caused by the dissociation of interfacial Ca-F-Si bonds during high temperature growth and the formation of a hydrogen or fluorine terminated Si interface after annealing in the H.sub.2 or F.sub.2. It is generally agreed that, for CaF.sub.2 grown at high temperatures, the CaF.sub.2 /Si interface is predominantly Ca-Si bonds (see R. M. Tromp and M. C. Reuter, Physical Review Letters, 61, 1756 (1988), and J. L. Batstone and J. M. Phillips, Physical Review Letters, 61,2275 (1988), and J. Zegenhagen and J. R. Patel, Physical Review B, 41, 5315 (1990)). For the CaF.sub.2 grown at low temperatures, more Si-F bonds exist. Recent studies also showed that F at the SiO.sub.2 /Si interface can suppress formation of interface states and improve the reliability of metal-oxide-semiconductor (MOS) devices (see Y. Nishioka, et. al, IEEE Electron Device Letters, 10 141 (1989)), implying that the existence of Si-F bonds is not the cause of interface state formation. Similar fluorine doping has also been applied to terminate dangling bonds at the heterojunction and in the SiC emitter of a heterojunction bipolar transistor (see T. Sugii, et. al, IEEE Transactions on Electron Devices, 37, 2331 (1990). These reports and the applicants' observation that good C-V characteristics can be obtained from CaF.sub.2 films grown at low temperatures suggest that F atoms may passivate Si surfaces at low temperatures, and thus form a CaF.sub.2 /Si interface of low interface state density. During high-temperature growth or prolonged annealing in vacuum, these F atoms dissociate from the interfacial Ca-F-Si bonds and result in increased interface state density. When CaF.sub.2 /Si(111) is annealed in H.sub.2 or F.sub.2 at an appropriate temperature, H or F may terminate the dangling bonds of Si and/or Ca atoms and thus improve the C-V characteristics of the capacitors.

It should be noted that the inventive process of annealing the substrate on which the CaF.sub.2 is deposited can also be done during and/or after the process of forming semiconductor devices on the substrate.

A few preferred embodiments have been described in detail hereinabove. It is to be understood that the scope of the invention also comprehends embodiments different from those described, yet within the scope of the claims.

Words of inclusion are to be interpreted as nonexhaustive in considering the scope of the invention.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. In particular, the use of silicon in the (111) orientation in the description of the preferred embodiments is not intended to suggest that other orientations are excluded from the benefits of the invention. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.